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Vladimir Olteanbee9fd22022-01-03 14:47:36 +02001// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
Yuantian Tang353f36d2019-04-10 16:43:34 +08002/*
Vladimir Olteanbee9fd22022-01-03 14:47:36 +02003 * Device Tree file for NXP LS1028A RDB Board.
Yuantian Tang353f36d2019-04-10 16:43:34 +08004 *
Vladimir Olteanbee9fd22022-01-03 14:47:36 +02005 * Copyright 2018-2021 NXP
6 *
7 * Harninder Rai <harninder.rai@nxp.com>
Yuantian Tang353f36d2019-04-10 16:43:34 +08008 *
9 */
10
11/dts-v1/;
Yuantian Tang353f36d2019-04-10 16:43:34 +080012#include "fsl-ls1028a.dtsi"
13
14/ {
Vladimir Olteanbee9fd22022-01-03 14:47:36 +020015 model = "LS1028A RDB Board";
Yuantian Tang353f36d2019-04-10 16:43:34 +080016 compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
Vladimir Olteanbee9fd22022-01-03 14:47:36 +020017
Kuldeep Singh5e2fb3e2019-11-06 16:38:00 +053018 aliases {
Vladimir Olteanbee9fd22022-01-03 14:47:36 +020019 crypto = &crypto;
20 serial0 = &duart0;
21 serial1 = &duart1;
22 mmc0 = &esdhc;
23 mmc1 = &esdhc1;
24 rtc1 = &ftm_alarm0;
Kuldeep Singh5e2fb3e2019-11-06 16:38:00 +053025 spi0 = &fspi;
Michael Wallec816dd02021-10-13 18:14:15 +020026 ethernet0 = &enetc_port0;
27 ethernet1 = &enetc_port2;
Michael Walle82a3c9e2021-02-25 16:51:11 +010028 ethernet2 = &mscc_felix_port0;
29 ethernet3 = &mscc_felix_port1;
30 ethernet4 = &mscc_felix_port2;
31 ethernet5 = &mscc_felix_port3;
Kuldeep Singh5e2fb3e2019-11-06 16:38:00 +053032 };
Vladimir Olteanbee9fd22022-01-03 14:47:36 +020033
34 chosen {
35 stdout-path = "serial0:115200n8";
36 };
37
38 memory@80000000 {
39 device_type = "memory";
40 reg = <0x0 0x80000000 0x1 0x0000000>;
41 };
42
43 sys_mclk: clock-mclk {
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
46 clock-frequency = <25000000>;
47 };
48
49 reg_1p8v: regulator-1p8v {
50 compatible = "regulator-fixed";
51 regulator-name = "1P8V";
52 regulator-min-microvolt = <1800000>;
53 regulator-max-microvolt = <1800000>;
54 regulator-always-on;
55 };
56
57 sb_3v3: regulator-sb3v3 {
58 compatible = "regulator-fixed";
59 regulator-name = "3v3_vbus";
60 regulator-min-microvolt = <3300000>;
61 regulator-max-microvolt = <3300000>;
62 regulator-boot-on;
63 regulator-always-on;
64 };
65
66 sound {
67 compatible = "simple-audio-card";
68 simple-audio-card,format = "i2s";
69 simple-audio-card,widgets =
70 "Microphone", "Microphone Jack",
71 "Headphone", "Headphone Jack",
72 "Speaker", "Speaker Ext",
73 "Line", "Line In Jack";
74 simple-audio-card,routing =
75 "MIC_IN", "Microphone Jack",
76 "Microphone Jack", "Mic Bias",
77 "LINE_IN", "Line In Jack",
78 "Headphone Jack", "HP_OUT",
79 "Speaker Ext", "LINE_OUT";
80
81 simple-audio-card,cpu {
82 sound-dai = <&sai4>;
83 frame-master;
84 bitclock-master;
85 };
86
87 simple-audio-card,codec {
88 sound-dai = <&sgtl5000>;
89 frame-master;
90 bitclock-master;
91 system-clock-frequency = <25000000>;
92 };
93 };
94};
95
96&can0 {
97 status = "okay";
98
99 can-transceiver {
100 max-bitrate = <5000000>;
101 };
102};
103
104&can1 {
105 status = "okay";
106
107 can-transceiver {
108 max-bitrate = <5000000>;
109 };
Yuantian Tang353f36d2019-04-10 16:43:34 +0800110};
111
Vladimir Oltean5009b112022-01-03 14:47:31 +0200112&duart0 {
113 status = "okay";
114};
115
116&duart1 {
117 status = "okay";
118};
119
120&enetc_mdio_pf3 {
Vladimir Oltean4a5362f2022-01-03 14:47:32 +0200121 sgmii_phy0: ethernet-phy@2 {
122 reg = <0x2>;
Vladimir Oltean5009b112022-01-03 14:47:31 +0200123 };
124
Vladimir Oltean4a5362f2022-01-03 14:47:32 +0200125 /* VSC8514 QSGMII quad PHY */
126 qsgmii_phy0: ethernet-phy@10 {
Vladimir Oltean5009b112022-01-03 14:47:31 +0200127 reg = <0x10>;
128 };
129
Vladimir Oltean4a5362f2022-01-03 14:47:32 +0200130 qsgmii_phy1: ethernet-phy@11 {
Vladimir Oltean5009b112022-01-03 14:47:31 +0200131 reg = <0x11>;
132 };
133
Vladimir Oltean4a5362f2022-01-03 14:47:32 +0200134 qsgmii_phy2: ethernet-phy@12 {
Vladimir Oltean5009b112022-01-03 14:47:31 +0200135 reg = <0x12>;
136 };
137
Vladimir Oltean4a5362f2022-01-03 14:47:32 +0200138 qsgmii_phy3: ethernet-phy@13 {
Vladimir Oltean5009b112022-01-03 14:47:31 +0200139 reg = <0x13>;
140 };
141};
142
143&enetc_port0 {
Vladimir Oltean4a5362f2022-01-03 14:47:32 +0200144 phy-handle = <&sgmii_phy0>;
Vladimir Oltean5009b112022-01-03 14:47:31 +0200145 phy-mode = "sgmii";
Vladimir Oltean4a5362f2022-01-03 14:47:32 +0200146 managed = "in-band-status";
147 status = "okay";
Vladimir Oltean5009b112022-01-03 14:47:31 +0200148};
149
150&enetc_port2 {
151 status = "okay";
152};
153
Michael Wallec816dd02021-10-13 18:14:15 +0200154&esdhc {
Vladimir Olteanbee9fd22022-01-03 14:47:36 +0200155 sd-uhs-sdr104;
156 sd-uhs-sdr50;
157 sd-uhs-sdr25;
158 sd-uhs-sdr12;
Yuantian Tang353f36d2019-04-10 16:43:34 +0800159 status = "okay";
160};
161
162&esdhc1 {
Yinbo Zhu23da1112019-07-16 15:09:10 +0800163 mmc-hs200-1_8v;
Vladimir Olteanbee9fd22022-01-03 14:47:36 +0200164 mmc-hs400-1_8v;
165 bus-width = <8>;
166 status = "okay";
Yuantian Tang353f36d2019-04-10 16:43:34 +0800167};
168
Kuldeep Singh5e2fb3e2019-11-06 16:38:00 +0530169&fspi {
170 status = "okay";
171
172 mt35xu02g0: flash@0 {
Vladimir Olteanbee9fd22022-01-03 14:47:36 +0200173 compatible = "jedec,spi-nor";
Kuldeep Singh5e2fb3e2019-11-06 16:38:00 +0530174 #address-cells = <1>;
175 #size-cells = <1>;
Kuldeep Singh5e2fb3e2019-11-06 16:38:00 +0530176 spi-max-frequency = <50000000>;
Vladimir Olteanbee9fd22022-01-03 14:47:36 +0200177 /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
178 spi-rx-bus-width = <8>; /* 8 SPI Rx lines */
179 spi-tx-bus-width = <1>; /* 1 SPI Tx line */
Kuldeep Singh5e2fb3e2019-11-06 16:38:00 +0530180 reg = <0>;
181 };
182};
183
Yuantian Tang353f36d2019-04-10 16:43:34 +0800184&i2c0 {
185 status = "okay";
Chuanhua Hane120d122019-07-10 21:16:52 +0800186
Vladimir Olteanbee9fd22022-01-03 14:47:36 +0200187 i2c-mux@77 {
188 compatible = "nxp,pca9847";
Chuanhua Hane120d122019-07-10 21:16:52 +0800189 reg = <0x77>;
190 #address-cells = <1>;
191 #size-cells = <0>;
192
Vladimir Olteanbee9fd22022-01-03 14:47:36 +0200193 i2c@1 {
194 #address-cells = <1>;
195 #size-cells = <0>;
196 reg = <0x1>;
197
198 sgtl5000: audio-codec@a {
199 #sound-dai-cells = <0>;
200 compatible = "fsl,sgtl5000";
201 reg = <0xa>;
202 VDDA-supply = <&reg_1p8v>;
203 VDDIO-supply = <&reg_1p8v>;
204 clocks = <&sys_mclk>;
205 sclk-strength = <3>;
206 };
207 };
208
209 i2c@2 {
210 #address-cells = <1>;
211 #size-cells = <0>;
212 reg = <0x02>;
213
214 current-monitor@40 {
215 compatible = "ti,ina220";
216 reg = <0x40>;
217 shunt-resistor = <500>;
218 };
219 };
220
Chuanhua Hane120d122019-07-10 21:16:52 +0800221 i2c@3 {
222 #address-cells = <1>;
223 #size-cells = <0>;
224 reg = <0x3>;
225
Vladimir Olteanbee9fd22022-01-03 14:47:36 +0200226 temperature-sensor@4c {
227 compatible = "nxp,sa56004";
228 reg = <0x4c>;
229 vcc-supply = <&sb_3v3>;
230 };
231
Chuanhua Hane120d122019-07-10 21:16:52 +0800232 rtc@51 {
Vladimir Oltean41496cc2022-01-03 14:47:28 +0200233 compatible = "nxp,pcf2129";
Chuanhua Hane120d122019-07-10 21:16:52 +0800234 reg = <0x51>;
235 };
236 };
237 };
Yuantian Tang353f36d2019-04-10 16:43:34 +0800238};
239
Alex Margineancc32fd92021-01-25 14:23:56 +0200240&mscc_felix {
241 status = "okay";
242};
243
244&mscc_felix_port0 {
245 label = "swp0";
Vladimir Oltean4a5362f2022-01-03 14:47:32 +0200246 managed = "in-band-status";
247 phy-handle = <&qsgmii_phy0>;
Alex Margineancc32fd92021-01-25 14:23:56 +0200248 phy-mode = "qsgmii";
249 status = "okay";
250};
251
252&mscc_felix_port1 {
253 label = "swp1";
Vladimir Oltean4a5362f2022-01-03 14:47:32 +0200254 managed = "in-band-status";
255 phy-handle = <&qsgmii_phy1>;
Alex Margineancc32fd92021-01-25 14:23:56 +0200256 phy-mode = "qsgmii";
257 status = "okay";
258};
259
260&mscc_felix_port2 {
261 label = "swp2";
Vladimir Oltean4a5362f2022-01-03 14:47:32 +0200262 managed = "in-band-status";
263 phy-handle = <&qsgmii_phy2>;
Alex Margineancc32fd92021-01-25 14:23:56 +0200264 phy-mode = "qsgmii";
265 status = "okay";
266};
267
268&mscc_felix_port3 {
269 label = "swp3";
Vladimir Oltean4a5362f2022-01-03 14:47:32 +0200270 managed = "in-band-status";
271 phy-handle = <&qsgmii_phy3>;
Alex Margineancc32fd92021-01-25 14:23:56 +0200272 phy-mode = "qsgmii";
273 status = "okay";
274};
275
276&mscc_felix_port4 {
Michael Wallec816dd02021-10-13 18:14:15 +0200277 ethernet = <&enetc_port2>;
Alex Margineancc32fd92021-01-25 14:23:56 +0200278 status = "okay";
279};
280
Vladimir Olteanbee9fd22022-01-03 14:47:36 +0200281&optee {
282 status = "okay";
283};
284
285&sai4 {
286 status = "okay";
287};
288
Vladimir Oltean5009b112022-01-03 14:47:31 +0200289&sata {
290 status = "okay";
291};
Alex Margineancc32fd92021-01-25 14:23:56 +0200292
Vladimir Oltean5009b112022-01-03 14:47:31 +0200293&usb0 {
294 status = "okay";
295};
Alex Margineancc32fd92021-01-25 14:23:56 +0200296
Vladimir Oltean5009b112022-01-03 14:47:31 +0200297&usb1 {
Vladimir Olteanbee9fd22022-01-03 14:47:36 +0200298 dr_mode = "otg";
Vladimir Oltean5009b112022-01-03 14:47:31 +0200299 status = "okay";
Alex Margineanb32e9a72019-07-03 12:11:43 +0300300};