Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 6a11fdf0536e02ac9cd4a3da0535a271c694715f / . / arch / arm / dts / rk3588s.dtsi
blob: fca8503aed8cf4aa26a308d73be1311c6de18b43 [file] [log] [blame]
Jagan Teki515773b2023-01-30 20:27:42 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4 */
5
6#include <dt-bindings/clock/rockchip,rk3588-cru.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/power/rk3588-power.h>
10#include <dt-bindings/reset/rockchip,rk3588-cru.h>
11
12/ {
13 compatible = "rockchip,rk3588";
14
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 cpu-map {
24 cluster0 {
25 core0 {
26 cpu = <&cpu_l0>;
27 };
28 core1 {
29 cpu = <&cpu_l1>;
30 };
31 core2 {
32 cpu = <&cpu_l2>;
33 };
34 core3 {
35 cpu = <&cpu_l3>;
36 };
37 };
38 cluster1 {
39 core0 {
40 cpu = <&cpu_b0>;
41 };
42 core1 {
43 cpu = <&cpu_b1>;
44 };
45 };
46 cluster2 {
47 core0 {
48 cpu = <&cpu_b2>;
49 };
50 core1 {
51 cpu = <&cpu_b3>;
52 };
53 };
54 };
55
56 cpu_l0: cpu@0 {
57 device_type = "cpu";
58 compatible = "arm,cortex-a55";
59 reg = <0x0>;
60 enable-method = "psci";
61 capacity-dmips-mhz = <530>;
62 clocks = <&scmi_clk SCMI_CLK_CPUL>;
63 cpu-idle-states = <&CPU_SLEEP>;
64 i-cache-size = <32768>;
65 i-cache-line-size = <64>;
66 i-cache-sets = <128>;
67 d-cache-size = <32768>;
68 d-cache-line-size = <64>;
69 d-cache-sets = <128>;
70 next-level-cache = <&l2_cache_l0>;
71 dynamic-power-coefficient = <228>;
72 #cooling-cells = <2>;
73 };
74
75 cpu_l1: cpu@100 {
76 device_type = "cpu";
77 compatible = "arm,cortex-a55";
78 reg = <0x100>;
79 enable-method = "psci";
80 capacity-dmips-mhz = <530>;
81 clocks = <&scmi_clk SCMI_CLK_CPUL>;
82 cpu-idle-states = <&CPU_SLEEP>;
83 i-cache-size = <32768>;
84 i-cache-line-size = <64>;
85 i-cache-sets = <128>;
86 d-cache-size = <32768>;
87 d-cache-line-size = <64>;
88 d-cache-sets = <128>;
89 next-level-cache = <&l2_cache_l1>;
90 dynamic-power-coefficient = <228>;
91 #cooling-cells = <2>;
92 };
93
94 cpu_l2: cpu@200 {
95 device_type = "cpu";
96 compatible = "arm,cortex-a55";
97 reg = <0x200>;
98 enable-method = "psci";
99 capacity-dmips-mhz = <530>;
100 clocks = <&scmi_clk SCMI_CLK_CPUL>;
101 cpu-idle-states = <&CPU_SLEEP>;
102 i-cache-size = <32768>;
103 i-cache-line-size = <64>;
104 i-cache-sets = <128>;
105 d-cache-size = <32768>;
106 d-cache-line-size = <64>;
107 d-cache-sets = <128>;
108 next-level-cache = <&l2_cache_l2>;
109 dynamic-power-coefficient = <228>;
110 #cooling-cells = <2>;
111 };
112
113 cpu_l3: cpu@300 {
114 device_type = "cpu";
115 compatible = "arm,cortex-a55";
116 reg = <0x300>;
117 enable-method = "psci";
118 capacity-dmips-mhz = <530>;
119 clocks = <&scmi_clk SCMI_CLK_CPUL>;
120 cpu-idle-states = <&CPU_SLEEP>;
121 i-cache-size = <32768>;
122 i-cache-line-size = <64>;
123 i-cache-sets = <128>;
124 d-cache-size = <32768>;
125 d-cache-line-size = <64>;
126 d-cache-sets = <128>;
127 next-level-cache = <&l2_cache_l3>;
128 dynamic-power-coefficient = <228>;
129 #cooling-cells = <2>;
130 };
131
132 cpu_b0: cpu@400 {
133 device_type = "cpu";
134 compatible = "arm,cortex-a76";
135 reg = <0x400>;
136 enable-method = "psci";
137 capacity-dmips-mhz = <1024>;
138 clocks = <&scmi_clk SCMI_CLK_CPUB01>;
139 cpu-idle-states = <&CPU_SLEEP>;
140 i-cache-size = <65536>;
141 i-cache-line-size = <64>;
142 i-cache-sets = <256>;
143 d-cache-size = <65536>;
144 d-cache-line-size = <64>;
145 d-cache-sets = <256>;
146 next-level-cache = <&l2_cache_b0>;
147 dynamic-power-coefficient = <416>;
148 #cooling-cells = <2>;
149 };
150
151 cpu_b1: cpu@500 {
152 device_type = "cpu";
153 compatible = "arm,cortex-a76";
154 reg = <0x500>;
155 enable-method = "psci";
156 capacity-dmips-mhz = <1024>;
157 clocks = <&scmi_clk SCMI_CLK_CPUB01>;
158 cpu-idle-states = <&CPU_SLEEP>;
159 i-cache-size = <65536>;
160 i-cache-line-size = <64>;
161 i-cache-sets = <256>;
162 d-cache-size = <65536>;
163 d-cache-line-size = <64>;
164 d-cache-sets = <256>;
165 next-level-cache = <&l2_cache_b1>;
166 dynamic-power-coefficient = <416>;
167 #cooling-cells = <2>;
168 };
169
170 cpu_b2: cpu@600 {
171 device_type = "cpu";
172 compatible = "arm,cortex-a76";
173 reg = <0x600>;
174 enable-method = "psci";
175 capacity-dmips-mhz = <1024>;
176 clocks = <&scmi_clk SCMI_CLK_CPUB23>;
177 cpu-idle-states = <&CPU_SLEEP>;
178 i-cache-size = <65536>;
179 i-cache-line-size = <64>;
180 i-cache-sets = <256>;
181 d-cache-size = <65536>;
182 d-cache-line-size = <64>;
183 d-cache-sets = <256>;
184 next-level-cache = <&l2_cache_b2>;
185 dynamic-power-coefficient = <416>;
186 #cooling-cells = <2>;
187 };
188
189 cpu_b3: cpu@700 {
190 device_type = "cpu";
191 compatible = "arm,cortex-a76";
192 reg = <0x700>;
193 enable-method = "psci";
194 capacity-dmips-mhz = <1024>;
195 clocks = <&scmi_clk SCMI_CLK_CPUB23>;
196 cpu-idle-states = <&CPU_SLEEP>;
197 i-cache-size = <65536>;
198 i-cache-line-size = <64>;
199 i-cache-sets = <256>;
200 d-cache-size = <65536>;
201 d-cache-line-size = <64>;
202 d-cache-sets = <256>;
203 next-level-cache = <&l2_cache_b3>;
204 dynamic-power-coefficient = <416>;
205 #cooling-cells = <2>;
206 };
207
208 idle-states {
209 entry-method = "psci";
210 CPU_SLEEP: cpu-sleep {
211 compatible = "arm,idle-state";
212 local-timer-stop;
213 arm,psci-suspend-param = <0x0010000>;
214 entry-latency-us = <100>;
215 exit-latency-us = <120>;
216 min-residency-us = <1000>;
217 };
218 };
219
220 l2_cache_l0: l2-cache-l0 {
221 compatible = "cache";
222 cache-size = <131072>;
223 cache-line-size = <64>;
224 cache-sets = <512>;
225 next-level-cache = <&l3_cache>;
226 };
227
228 l2_cache_l1: l2-cache-l1 {
229 compatible = "cache";
230 cache-size = <131072>;
231 cache-line-size = <64>;
232 cache-sets = <512>;
233 next-level-cache = <&l3_cache>;
234 };
235
236 l2_cache_l2: l2-cache-l2 {
237 compatible = "cache";
238 cache-size = <131072>;
239 cache-line-size = <64>;
240 cache-sets = <512>;
241 next-level-cache = <&l3_cache>;
242 };
243
244 l2_cache_l3: l2-cache-l3 {
245 compatible = "cache";
246 cache-size = <131072>;
247 cache-line-size = <64>;
248 cache-sets = <512>;
249 next-level-cache = <&l3_cache>;
250 };
251
252 l2_cache_b0: l2-cache-b0 {
253 compatible = "cache";
254 cache-size = <524288>;
255 cache-line-size = <64>;
256 cache-sets = <1024>;
257 next-level-cache = <&l3_cache>;
258 };
259
260 l2_cache_b1: l2-cache-b1 {
261 compatible = "cache";
262 cache-size = <524288>;
263 cache-line-size = <64>;
264 cache-sets = <1024>;
265 next-level-cache = <&l3_cache>;
266 };
267
268 l2_cache_b2: l2-cache-b2 {
269 compatible = "cache";
270 cache-size = <524288>;
271 cache-line-size = <64>;
272 cache-sets = <1024>;
273 next-level-cache = <&l3_cache>;
274 };
275
276 l2_cache_b3: l2-cache-b3 {
277 compatible = "cache";
278 cache-size = <524288>;
279 cache-line-size = <64>;
280 cache-sets = <1024>;
281 next-level-cache = <&l3_cache>;
282 };
283
284 l3_cache: l3-cache {
285 compatible = "cache";
286 cache-size = <3145728>;
287 cache-line-size = <64>;
288 cache-sets = <4096>;
289 };
290 };
291
292 firmware {
293 optee: optee {
294 compatible = "linaro,optee-tz";
295 method = "smc";
296 };
297
298 scmi: scmi {
299 compatible = "arm,scmi-smc";
300 arm,smc-id = <0x82000010>;
301 shmem = <&scmi_shmem>;
302 #address-cells = <1>;
303 #size-cells = <0>;
304
305 scmi_clk: protocol@14 {
306 reg = <0x14>;
307 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>,
308 <&scmi_clk SCMI_CLK_CPUB23>;
309 assigned-clock-rates = <1200000000>,
310 <1200000000>;
311 #clock-cells = <1>;
312 };
313
314 scmi_reset: protocol@16 {
315 reg = <0x16>;
316 #reset-cells = <1>;
317 };
318 };
319 };
320
321 pmu-a55 {
322 compatible = "arm,cortex-a55-pmu";
323 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>;
324 };
325
326 pmu-a76 {
327 compatible = "arm,cortex-a76-pmu";
328 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>;
329 };
330
331 psci {
332 compatible = "arm,psci-1.0";
333 method = "smc";
334 };
335
336 spll: clock-0 {
337 compatible = "fixed-clock";
338 clock-frequency = <702000000>;
339 clock-output-names = "spll";
340 #clock-cells = <0>;
341 };
342
343 timer {
344 compatible = "arm,armv8-timer";
345 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
346 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
347 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
348 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
349 <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
350 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
351 };
352
353 xin24m: clock-1 {
354 compatible = "fixed-clock";
355 clock-frequency = <24000000>;
356 clock-output-names = "xin24m";
357 #clock-cells = <0>;
358 };
359
360 xin32k: clock-2 {
361 compatible = "fixed-clock";
362 clock-frequency = <32768>;
363 clock-output-names = "xin32k";
364 #clock-cells = <0>;
365 };
366
367 pmu_sram: sram@10f000 {
368 compatible = "mmio-sram";
369 reg = <0x0 0x0010f000 0x0 0x100>;
370 ranges = <0 0x0 0x0010f000 0x100>;
371 #address-cells = <1>;
372 #size-cells = <1>;
373
374 scmi_shmem: sram@0 {
375 compatible = "arm,scmi-shmem";
376 reg = <0x0 0x100>;
377 };
378 };
379
380 sys_grf: syscon@fd58c000 {
381 compatible = "rockchip,rk3588-sys-grf", "syscon";
382 reg = <0x0 0xfd58c000 0x0 0x1000>;
383 };
384
385 php_grf: syscon@fd5b0000 {
386 compatible = "rockchip,rk3588-php-grf", "syscon";
387 reg = <0x0 0xfd5b0000 0x0 0x1000>;
388 };
389
390 ioc: syscon@fd5f0000 {
391 compatible = "rockchip,rk3588-ioc", "syscon";
392 reg = <0x0 0xfd5f0000 0x0 0x10000>;
393 };
394
395 system_sram1: sram@fd600000 {
396 compatible = "mmio-sram";
397 reg = <0x0 0xfd600000 0x0 0x100000>;
398 ranges = <0x0 0x0 0xfd600000 0x100000>;
399 #address-cells = <1>;
400 #size-cells = <1>;
401 };
402
403 cru: clock-controller@fd7c0000 {
404 compatible = "rockchip,rk3588-cru";
405 reg = <0x0 0xfd7c0000 0x0 0x5c000>;
406 assigned-clocks =
407 <&cru PLL_PPLL>, <&cru PLL_AUPLL>,
408 <&cru PLL_NPLL>, <&cru PLL_GPLL>,
409 <&cru ACLK_CENTER_ROOT>,
410 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>,
411 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>,
412 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>,
413 <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>,
414 <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,
415 <&cru CLK_GPU>;
416 assigned-clock-rates =
417 <100000000>, <786432000>,
418 <850000000>, <1188000000>,
419 <702000000>,
420 <400000000>, <500000000>,
421 <800000000>, <100000000>,
422 <400000000>, <100000000>,
423 <200000000>, <500000000>,
424 <375000000>, <150000000>,
425 <200000000>;
426 rockchip,grf = <&php_grf>;
427 #clock-cells = <1>;
428 #reset-cells = <1>;
429 };
430
431 i2c0: i2c@fd880000 {
432 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
433 reg = <0x0 0xfd880000 0x0 0x1000>;
434 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>;
435 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
436 clock-names = "i2c", "pclk";
437 pinctrl-0 = <&i2c0m0_xfer>;
438 pinctrl-names = "default";
439 #address-cells = <1>;
440 #size-cells = <0>;
441 status = "disabled";
442 };
443
444 uart0: serial@fd890000 {
445 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
446 reg = <0x0 0xfd890000 0x0 0x100>;
447 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
448 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
449 clock-names = "baudclk", "apb_pclk";
450 dmas = <&dmac0 6>, <&dmac0 7>;
451 dma-names = "tx", "rx";
452 pinctrl-0 = <&uart0m1_xfer>;
453 pinctrl-names = "default";
454 reg-shift = <2>;
455 reg-io-width = <4>;
456 status = "disabled";
457 };
458
459 pwm0: pwm@fd8b0000 {
460 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
461 reg = <0x0 0xfd8b0000 0x0 0x10>;
462 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
463 clock-names = "pwm", "pclk";
464 pinctrl-0 = <&pwm0m0_pins>;
465 pinctrl-names = "default";
466 #pwm-cells = <3>;
467 status = "disabled";
468 };
469
470 pwm1: pwm@fd8b0010 {
471 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
472 reg = <0x0 0xfd8b0010 0x0 0x10>;
473 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
474 clock-names = "pwm", "pclk";
475 pinctrl-0 = <&pwm1m0_pins>;
476 pinctrl-names = "default";
477 #pwm-cells = <3>;
478 status = "disabled";
479 };
480
481 pwm2: pwm@fd8b0020 {
482 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
483 reg = <0x0 0xfd8b0020 0x0 0x10>;
484 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
485 clock-names = "pwm", "pclk";
486 pinctrl-0 = <&pwm2m0_pins>;
487 pinctrl-names = "default";
488 #pwm-cells = <3>;
489 status = "disabled";
490 };
491
492 pwm3: pwm@fd8b0030 {
493 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
494 reg = <0x0 0xfd8b0030 0x0 0x10>;
495 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
496 clock-names = "pwm", "pclk";
497 pinctrl-0 = <&pwm3m0_pins>;
498 pinctrl-names = "default";
499 #pwm-cells = <3>;
500 status = "disabled";
501 };
502
503 pmu: power-management@fd8d8000 {
504 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd";
505 reg = <0x0 0xfd8d8000 0x0 0x400>;
506
507 power: power-controller {
508 compatible = "rockchip,rk3588-power-controller";
509 #address-cells = <1>;
510 #power-domain-cells = <1>;
511 #size-cells = <0>;
512 status = "okay";
513
514 /* These power domains are grouped by VD_NPU */
515 power-domain@RK3588_PD_NPU {
516 reg = <RK3588_PD_NPU>;
517 #power-domain-cells = <0>;
518 #address-cells = <1>;
519 #size-cells = <0>;
520
521 power-domain@RK3588_PD_NPUTOP {
522 reg = <RK3588_PD_NPUTOP>;
523 clocks = <&cru HCLK_NPU_ROOT>,
524 <&cru PCLK_NPU_ROOT>,
525 <&cru CLK_NPU_DSU0>,
526 <&cru HCLK_NPU_CM0_ROOT>;
527 pm_qos = <&qos_npu0_mwr>,
528 <&qos_npu0_mro>,
529 <&qos_mcu_npu>;
530 #power-domain-cells = <0>;
531 #address-cells = <1>;
532 #size-cells = <0>;
533
534 power-domain@RK3588_PD_NPU1 {
535 reg = <RK3588_PD_NPU1>;
536 clocks = <&cru HCLK_NPU_ROOT>,
537 <&cru PCLK_NPU_ROOT>,
538 <&cru CLK_NPU_DSU0>;
539 pm_qos = <&qos_npu1>;
540 #power-domain-cells = <0>;
541 };
542 power-domain@RK3588_PD_NPU2 {
543 reg = <RK3588_PD_NPU2>;
544 clocks = <&cru HCLK_NPU_ROOT>,
545 <&cru PCLK_NPU_ROOT>,
546 <&cru CLK_NPU_DSU0>;
547 pm_qos = <&qos_npu2>;
548 #power-domain-cells = <0>;
549 };
550 };
551 };
552 /* These power domains are grouped by VD_GPU */
553 power-domain@RK3588_PD_GPU {
554 reg = <RK3588_PD_GPU>;
555 clocks = <&cru CLK_GPU>,
556 <&cru CLK_GPU_COREGROUP>,
557 <&cru CLK_GPU_STACKS>;
558 pm_qos = <&qos_gpu_m0>,
559 <&qos_gpu_m1>,
560 <&qos_gpu_m2>,
561 <&qos_gpu_m3>;
562 #power-domain-cells = <0>;
563 };
564 /* These power domains are grouped by VD_VCODEC */
565 power-domain@RK3588_PD_VCODEC {
566 reg = <RK3588_PD_VCODEC>;
567 #address-cells = <1>;
568 #size-cells = <0>;
569 #power-domain-cells = <0>;
570
571 power-domain@RK3588_PD_RKVDEC0 {
572 reg = <RK3588_PD_RKVDEC0>;
573 clocks = <&cru HCLK_RKVDEC0>,
574 <&cru HCLK_VDPU_ROOT>,
575 <&cru ACLK_VDPU_ROOT>,
576 <&cru ACLK_RKVDEC0>,
577 <&cru ACLK_RKVDEC_CCU>;
578 pm_qos = <&qos_rkvdec0>;
579 #power-domain-cells = <0>;
580 };
581 power-domain@RK3588_PD_RKVDEC1 {
582 reg = <RK3588_PD_RKVDEC1>;
583 clocks = <&cru HCLK_RKVDEC1>,
584 <&cru HCLK_VDPU_ROOT>,
585 <&cru ACLK_VDPU_ROOT>,
586 <&cru ACLK_RKVDEC1>;
587 pm_qos = <&qos_rkvdec1>;
588 #power-domain-cells = <0>;
589 };
590 power-domain@RK3588_PD_VENC0 {
591 reg = <RK3588_PD_VENC0>;
592 clocks = <&cru HCLK_RKVENC0>,
593 <&cru ACLK_RKVENC0>;
594 pm_qos = <&qos_rkvenc0_m0ro>,
595 <&qos_rkvenc0_m1ro>,
596 <&qos_rkvenc0_m2wo>;
597 #address-cells = <1>;
598 #size-cells = <0>;
599 #power-domain-cells = <0>;
600
601 power-domain@RK3588_PD_VENC1 {
602 reg = <RK3588_PD_VENC1>;
603 clocks = <&cru HCLK_RKVENC1>,
604 <&cru HCLK_RKVENC0>,
605 <&cru ACLK_RKVENC0>,
606 <&cru ACLK_RKVENC1>;
607 pm_qos = <&qos_rkvenc1_m0ro>,
608 <&qos_rkvenc1_m1ro>,
609 <&qos_rkvenc1_m2wo>;
610 #power-domain-cells = <0>;
611 };
612 };
613 };
614 /* These power domains are grouped by VD_LOGIC */
615 power-domain@RK3588_PD_VDPU {
616 reg = <RK3588_PD_VDPU>;
617 clocks = <&cru HCLK_VDPU_ROOT>,
618 <&cru ACLK_VDPU_LOW_ROOT>,
619 <&cru ACLK_VDPU_ROOT>,
620 <&cru ACLK_JPEG_DECODER_ROOT>,
621 <&cru ACLK_IEP2P0>,
622 <&cru HCLK_IEP2P0>,
623 <&cru ACLK_JPEG_ENCODER0>,
624 <&cru HCLK_JPEG_ENCODER0>,
625 <&cru ACLK_JPEG_ENCODER1>,
626 <&cru HCLK_JPEG_ENCODER1>,
627 <&cru ACLK_JPEG_ENCODER2>,
628 <&cru HCLK_JPEG_ENCODER2>,
629 <&cru ACLK_JPEG_ENCODER3>,
630 <&cru HCLK_JPEG_ENCODER3>,
631 <&cru ACLK_JPEG_DECODER>,
632 <&cru HCLK_JPEG_DECODER>,
633 <&cru ACLK_RGA2>,
634 <&cru HCLK_RGA2>;
635 pm_qos = <&qos_iep>,
636 <&qos_jpeg_dec>,
637 <&qos_jpeg_enc0>,
638 <&qos_jpeg_enc1>,
639 <&qos_jpeg_enc2>,
640 <&qos_jpeg_enc3>,
641 <&qos_rga2_mro>,
642 <&qos_rga2_mwo>;
643 #address-cells = <1>;
644 #size-cells = <0>;
645 #power-domain-cells = <0>;
646
647
648 power-domain@RK3588_PD_AV1 {
649 reg = <RK3588_PD_AV1>;
650 clocks = <&cru PCLK_AV1>,
651 <&cru ACLK_AV1>,
652 <&cru HCLK_VDPU_ROOT>;
653 pm_qos = <&qos_av1>;
654 #power-domain-cells = <0>;
655 };
656 power-domain@RK3588_PD_RKVDEC0 {
657 reg = <RK3588_PD_RKVDEC0>;
658 clocks = <&cru HCLK_RKVDEC0>,
659 <&cru HCLK_VDPU_ROOT>,
660 <&cru ACLK_VDPU_ROOT>,
661 <&cru ACLK_RKVDEC0>;
662 pm_qos = <&qos_rkvdec0>;
663 #power-domain-cells = <0>;
664 };
665 power-domain@RK3588_PD_RKVDEC1 {
666 reg = <RK3588_PD_RKVDEC1>;
667 clocks = <&cru HCLK_RKVDEC1>,
668 <&cru HCLK_VDPU_ROOT>,
669 <&cru ACLK_VDPU_ROOT>;
670 pm_qos = <&qos_rkvdec1>;
671 #power-domain-cells = <0>;
672 };
673 power-domain@RK3588_PD_RGA30 {
674 reg = <RK3588_PD_RGA30>;
675 clocks = <&cru ACLK_RGA3_0>,
676 <&cru HCLK_RGA3_0>;
677 pm_qos = <&qos_rga3_0>;
678 #power-domain-cells = <0>;
679 };
680 };
681 power-domain@RK3588_PD_VOP {
682 reg = <RK3588_PD_VOP>;
683 clocks = <&cru PCLK_VOP_ROOT>,
684 <&cru HCLK_VOP_ROOT>,
685 <&cru ACLK_VOP>;
686 pm_qos = <&qos_vop_m0>,
687 <&qos_vop_m1>;
688 #address-cells = <1>;
689 #size-cells = <0>;
690 #power-domain-cells = <0>;
691
692 power-domain@RK3588_PD_VO0 {
693 reg = <RK3588_PD_VO0>;
694 clocks = <&cru PCLK_VO0_ROOT>,
695 <&cru PCLK_VO0_S_ROOT>,
696 <&cru HCLK_VO0_S_ROOT>,
697 <&cru ACLK_VO0_ROOT>,
698 <&cru HCLK_HDCP0>,
699 <&cru ACLK_HDCP0>,
700 <&cru HCLK_VOP_ROOT>;
701 pm_qos = <&qos_hdcp0>;
702 #power-domain-cells = <0>;
703 };
704 };
705 power-domain@RK3588_PD_VO1 {
706 reg = <RK3588_PD_VO1>;
707 clocks = <&cru PCLK_VO1_ROOT>,
708 <&cru PCLK_VO1_S_ROOT>,
709 <&cru HCLK_VO1_S_ROOT>,
710 <&cru HCLK_HDCP1>,
711 <&cru ACLK_HDCP1>,
712 <&cru ACLK_HDMIRX_ROOT>,
713 <&cru HCLK_VO1USB_TOP_ROOT>;
714 pm_qos = <&qos_hdcp1>,
715 <&qos_hdmirx>;
716 #power-domain-cells = <0>;
717 };
718 power-domain@RK3588_PD_VI {
719 reg = <RK3588_PD_VI>;
720 clocks = <&cru HCLK_VI_ROOT>,
721 <&cru PCLK_VI_ROOT>,
722 <&cru HCLK_ISP0>,
723 <&cru ACLK_ISP0>,
724 <&cru HCLK_VICAP>,
725 <&cru ACLK_VICAP>;
726 pm_qos = <&qos_isp0_mro>,
727 <&qos_isp0_mwo>,
728 <&qos_vicap_m0>,
729 <&qos_vicap_m1>;
730 #address-cells = <1>;
731 #size-cells = <0>;
732 #power-domain-cells = <0>;
733
734 power-domain@RK3588_PD_ISP1 {
735 reg = <RK3588_PD_ISP1>;
736 clocks = <&cru HCLK_ISP1>,
737 <&cru ACLK_ISP1>,
738 <&cru HCLK_VI_ROOT>,
739 <&cru PCLK_VI_ROOT>;
740 pm_qos = <&qos_isp1_mwo>,
741 <&qos_isp1_mro>;
742 #power-domain-cells = <0>;
743 };
744 power-domain@RK3588_PD_FEC {
745 reg = <RK3588_PD_FEC>;
746 clocks = <&cru HCLK_FISHEYE0>,
747 <&cru ACLK_FISHEYE0>,
748 <&cru HCLK_FISHEYE1>,
749 <&cru ACLK_FISHEYE1>,
750 <&cru PCLK_VI_ROOT>;
751 pm_qos = <&qos_fisheye0>,
752 <&qos_fisheye1>;
753 #power-domain-cells = <0>;
754 };
755 };
756 power-domain@RK3588_PD_RGA31 {
757 reg = <RK3588_PD_RGA31>;
758 clocks = <&cru HCLK_RGA3_1>,
759 <&cru ACLK_RGA3_1>;
760 pm_qos = <&qos_rga3_1>;
761 #power-domain-cells = <0>;
762 };
763 power-domain@RK3588_PD_USB {
764 reg = <RK3588_PD_USB>;
765 clocks = <&cru PCLK_PHP_ROOT>,
766 <&cru ACLK_USB_ROOT>,
767 <&cru HCLK_USB_ROOT>,
768 <&cru HCLK_HOST0>,
769 <&cru HCLK_HOST_ARB0>,
770 <&cru HCLK_HOST1>,
771 <&cru HCLK_HOST_ARB1>;
772 pm_qos = <&qos_usb3_0>,
773 <&qos_usb3_1>,
774 <&qos_usb2host_0>,
775 <&qos_usb2host_1>;
776 #power-domain-cells = <0>;
777 };
778 power-domain@RK3588_PD_GMAC {
779 reg = <RK3588_PD_GMAC>;
780 clocks = <&cru PCLK_PHP_ROOT>,
781 <&cru ACLK_PCIE_ROOT>,
782 <&cru ACLK_PHP_ROOT>;
783 #power-domain-cells = <0>;
784 };
785 power-domain@RK3588_PD_PCIE {
786 reg = <RK3588_PD_PCIE>;
787 clocks = <&cru PCLK_PHP_ROOT>,
788 <&cru ACLK_PCIE_ROOT>,
789 <&cru ACLK_PHP_ROOT>;
790 #power-domain-cells = <0>;
791 };
792 power-domain@RK3588_PD_SDIO {
793 reg = <RK3588_PD_SDIO>;
794 clocks = <&cru HCLK_SDIO>,
795 <&cru HCLK_NVM_ROOT>;
796 pm_qos = <&qos_sdio>;
797 #power-domain-cells = <0>;
798 };
799 power-domain@RK3588_PD_AUDIO {
800 reg = <RK3588_PD_AUDIO>;
801 clocks = <&cru HCLK_AUDIO_ROOT>,
802 <&cru PCLK_AUDIO_ROOT>;
803 #power-domain-cells = <0>;
804 };
805 power-domain@RK3588_PD_SDMMC {
806 reg = <RK3588_PD_SDMMC>;
807 pm_qos = <&qos_sdmmc>;
808 #power-domain-cells = <0>;
809 };
810 };
811 };
812
813 qos_gpu_m0: qos@fdf35000 {
814 compatible = "rockchip,rk3588-qos", "syscon";
815 reg = <0x0 0xfdf35000 0x0 0x20>;
816 };
817
818 qos_gpu_m1: qos@fdf35200 {
819 compatible = "rockchip,rk3588-qos", "syscon";
820 reg = <0x0 0xfdf35200 0x0 0x20>;
821 };
822
823 qos_gpu_m2: qos@fdf35400 {
824 compatible = "rockchip,rk3588-qos", "syscon";
825 reg = <0x0 0xfdf35400 0x0 0x20>;
826 };
827
828 qos_gpu_m3: qos@fdf35600 {
829 compatible = "rockchip,rk3588-qos", "syscon";
830 reg = <0x0 0xfdf35600 0x0 0x20>;
831 };
832
833 qos_rga3_1: qos@fdf36000 {
834 compatible = "rockchip,rk3588-qos", "syscon";
835 reg = <0x0 0xfdf36000 0x0 0x20>;
836 };
837
838 qos_sdio: qos@fdf39000 {
839 compatible = "rockchip,rk3588-qos", "syscon";
840 reg = <0x0 0xfdf39000 0x0 0x20>;
841 };
842
843 qos_sdmmc: qos@fdf3d800 {
844 compatible = "rockchip,rk3588-qos", "syscon";
845 reg = <0x0 0xfdf3d800 0x0 0x20>;
846 };
847
848 qos_usb3_1: qos@fdf3e000 {
849 compatible = "rockchip,rk3588-qos", "syscon";
850 reg = <0x0 0xfdf3e000 0x0 0x20>;
851 };
852
853 qos_usb3_0: qos@fdf3e200 {
854 compatible = "rockchip,rk3588-qos", "syscon";
855 reg = <0x0 0xfdf3e200 0x0 0x20>;
856 };
857
858 qos_usb2host_0: qos@fdf3e400 {
859 compatible = "rockchip,rk3588-qos", "syscon";
860 reg = <0x0 0xfdf3e400 0x0 0x20>;
861 };
862
863 qos_usb2host_1: qos@fdf3e600 {
864 compatible = "rockchip,rk3588-qos", "syscon";
865 reg = <0x0 0xfdf3e600 0x0 0x20>;
866 };
867
868 qos_fisheye0: qos@fdf40000 {
869 compatible = "rockchip,rk3588-qos", "syscon";
870 reg = <0x0 0xfdf40000 0x0 0x20>;
871 };
872
873 qos_fisheye1: qos@fdf40200 {
874 compatible = "rockchip,rk3588-qos", "syscon";
875 reg = <0x0 0xfdf40200 0x0 0x20>;
876 };
877
878 qos_isp0_mro: qos@fdf40400 {
879 compatible = "rockchip,rk3588-qos", "syscon";
880 reg = <0x0 0xfdf40400 0x0 0x20>;
881 };
882
883 qos_isp0_mwo: qos@fdf40500 {
884 compatible = "rockchip,rk3588-qos", "syscon";
885 reg = <0x0 0xfdf40500 0x0 0x20>;
886 };
887
888 qos_vicap_m0: qos@fdf40600 {
889 compatible = "rockchip,rk3588-qos", "syscon";
890 reg = <0x0 0xfdf40600 0x0 0x20>;
891 };
892
893 qos_vicap_m1: qos@fdf40800 {
894 compatible = "rockchip,rk3588-qos", "syscon";
895 reg = <0x0 0xfdf40800 0x0 0x20>;
896 };
897
898 qos_isp1_mwo: qos@fdf41000 {
899 compatible = "rockchip,rk3588-qos", "syscon";
900 reg = <0x0 0xfdf41000 0x0 0x20>;
901 };
902
903 qos_isp1_mro: qos@fdf41100 {
904 compatible = "rockchip,rk3588-qos", "syscon";
905 reg = <0x0 0xfdf41100 0x0 0x20>;
906 };
907
908 qos_rkvenc0_m0ro: qos@fdf60000 {
909 compatible = "rockchip,rk3588-qos", "syscon";
910 reg = <0x0 0xfdf60000 0x0 0x20>;
911 };
912
913 qos_rkvenc0_m1ro: qos@fdf60200 {
914 compatible = "rockchip,rk3588-qos", "syscon";
915 reg = <0x0 0xfdf60200 0x0 0x20>;
916 };
917
918 qos_rkvenc0_m2wo: qos@fdf60400 {
919 compatible = "rockchip,rk3588-qos", "syscon";
920 reg = <0x0 0xfdf60400 0x0 0x20>;
921 };
922
923 qos_rkvenc1_m0ro: qos@fdf61000 {
924 compatible = "rockchip,rk3588-qos", "syscon";
925 reg = <0x0 0xfdf61000 0x0 0x20>;
926 };
927
928 qos_rkvenc1_m1ro: qos@fdf61200 {
929 compatible = "rockchip,rk3588-qos", "syscon";
930 reg = <0x0 0xfdf61200 0x0 0x20>;
931 };
932
933 qos_rkvenc1_m2wo: qos@fdf61400 {
934 compatible = "rockchip,rk3588-qos", "syscon";
935 reg = <0x0 0xfdf61400 0x0 0x20>;
936 };
937
938 qos_rkvdec0: qos@fdf62000 {
939 compatible = "rockchip,rk3588-qos", "syscon";
940 reg = <0x0 0xfdf62000 0x0 0x20>;
941 };
942
943 qos_rkvdec1: qos@fdf63000 {
944 compatible = "rockchip,rk3588-qos", "syscon";
945 reg = <0x0 0xfdf63000 0x0 0x20>;
946 };
947
948 qos_av1: qos@fdf64000 {
949 compatible = "rockchip,rk3588-qos", "syscon";
950 reg = <0x0 0xfdf64000 0x0 0x20>;
951 };
952
953 qos_iep: qos@fdf66000 {
954 compatible = "rockchip,rk3588-qos", "syscon";
955 reg = <0x0 0xfdf66000 0x0 0x20>;
956 };
957
958 qos_jpeg_dec: qos@fdf66200 {
959 compatible = "rockchip,rk3588-qos", "syscon";
960 reg = <0x0 0xfdf66200 0x0 0x20>;
961 };
962
963 qos_jpeg_enc0: qos@fdf66400 {
964 compatible = "rockchip,rk3588-qos", "syscon";
965 reg = <0x0 0xfdf66400 0x0 0x20>;
966 };
967
968 qos_jpeg_enc1: qos@fdf66600 {
969 compatible = "rockchip,rk3588-qos", "syscon";
970 reg = <0x0 0xfdf66600 0x0 0x20>;
971 };
972
973 qos_jpeg_enc2: qos@fdf66800 {
974 compatible = "rockchip,rk3588-qos", "syscon";
975 reg = <0x0 0xfdf66800 0x0 0x20>;
976 };
977
978 qos_jpeg_enc3: qos@fdf66a00 {
979 compatible = "rockchip,rk3588-qos", "syscon";
980 reg = <0x0 0xfdf66a00 0x0 0x20>;
981 };
982
983 qos_rga2_mro: qos@fdf66c00 {
984 compatible = "rockchip,rk3588-qos", "syscon";
985 reg = <0x0 0xfdf66c00 0x0 0x20>;
986 };
987
988 qos_rga2_mwo: qos@fdf66e00 {
989 compatible = "rockchip,rk3588-qos", "syscon";
990 reg = <0x0 0xfdf66e00 0x0 0x20>;
991 };
992
993 qos_rga3_0: qos@fdf67000 {
994 compatible = "rockchip,rk3588-qos", "syscon";
995 reg = <0x0 0xfdf67000 0x0 0x20>;
996 };
997
998 qos_vdpu: qos@fdf67200 {
999 compatible = "rockchip,rk3588-qos", "syscon";
1000 reg = <0x0 0xfdf67200 0x0 0x20>;
1001 };
1002
1003 qos_npu1: qos@fdf70000 {
1004 compatible = "rockchip,rk3588-qos", "syscon";
1005 reg = <0x0 0xfdf70000 0x0 0x20>;
1006 };
1007
1008 qos_npu2: qos@fdf71000 {
1009 compatible = "rockchip,rk3588-qos", "syscon";
1010 reg = <0x0 0xfdf71000 0x0 0x20>;
1011 };
1012
1013 qos_npu0_mwr: qos@fdf72000 {
1014 compatible = "rockchip,rk3588-qos", "syscon";
1015 reg = <0x0 0xfdf72000 0x0 0x20>;
1016 };
1017
1018 qos_npu0_mro: qos@fdf72200 {
1019 compatible = "rockchip,rk3588-qos", "syscon";
1020 reg = <0x0 0xfdf72200 0x0 0x20>;
1021 };
1022
1023 qos_mcu_npu: qos@fdf72400 {
1024 compatible = "rockchip,rk3588-qos", "syscon";
1025 reg = <0x0 0xfdf72400 0x0 0x20>;
1026 };
1027
1028 qos_hdcp0: qos@fdf80000 {
1029 compatible = "rockchip,rk3588-qos", "syscon";
1030 reg = <0x0 0xfdf80000 0x0 0x20>;
1031 };
1032
1033 qos_hdcp1: qos@fdf81000 {
1034 compatible = "rockchip,rk3588-qos", "syscon";
1035 reg = <0x0 0xfdf81000 0x0 0x20>;
1036 };
1037
1038 qos_hdmirx: qos@fdf81200 {
1039 compatible = "rockchip,rk3588-qos", "syscon";
1040 reg = <0x0 0xfdf81200 0x0 0x20>;
1041 };
1042
1043 qos_vop_m0: qos@fdf82000 {
1044 compatible = "rockchip,rk3588-qos", "syscon";
1045 reg = <0x0 0xfdf82000 0x0 0x20>;
1046 };
1047
1048 qos_vop_m1: qos@fdf82200 {
1049 compatible = "rockchip,rk3588-qos", "syscon";
1050 reg = <0x0 0xfdf82200 0x0 0x20>;
1051 };
1052
1053 gmac1: ethernet@fe1c0000 {
1054 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
1055 reg = <0x0 0xfe1c0000 0x0 0x10000>;
1056 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>,
1057 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
1058 interrupt-names = "macirq", "eth_wake_irq";
1059 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
1060 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>,
1061 <&cru CLK_GMAC1_PTP_REF>;
1062 clock-names = "stmmaceth", "clk_mac_ref",
1063 "pclk_mac", "aclk_mac",
1064 "ptp_ref";
1065 power-domains = <&power RK3588_PD_GMAC>;
1066 resets = <&cru SRST_A_GMAC1>;
1067 reset-names = "stmmaceth";
1068 rockchip,grf = <&sys_grf>;
1069 rockchip,php-grf = <&php_grf>;
1070 snps,axi-config = <&gmac1_stmmac_axi_setup>;
1071 snps,mixed-burst;
1072 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
1073 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
1074 snps,tso;
1075 status = "disabled";
1076
1077 mdio1: mdio {
1078 compatible = "snps,dwmac-mdio";
1079 #address-cells = <0x1>;
1080 #size-cells = <0x0>;
1081 };
1082
1083 gmac1_stmmac_axi_setup: stmmac-axi-config {
1084 snps,blen = <0 0 0 0 16 8 4>;
1085 snps,wr_osr_lmt = <4>;
1086 snps,rd_osr_lmt = <8>;
1087 };
1088
1089 gmac1_mtl_rx_setup: rx-queues-config {
1090 snps,rx-queues-to-use = <2>;
1091 queue0 {};
1092 queue1 {};
1093 };
1094
1095 gmac1_mtl_tx_setup: tx-queues-config {
1096 snps,tx-queues-to-use = <2>;
1097 queue0 {};
1098 queue1 {};
1099 };
1100 };
1101
Jonas Karlman58c23012023-04-17 19:07:21 +0000[diff] [blame]1102 sdmmc: mmc@fe2c0000 {
1103 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
1104 reg = <0x0 0xfe2c0000 0x0 0x4000>;
1105 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
1106 clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>,
1107 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
1108 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1109 fifo-depth = <0x100>;
1110 max-frequency = <200000000>;
1111 pinctrl-names = "default";
1112 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1113 power-domains = <&power RK3588_PD_SDMMC>;
1114 status = "disabled";
1115 };
1116
Jagan Teki515773b2023-01-30 20:27:42 +0530[diff] [blame]1117 sdhci: mmc@fe2e0000 {
1118 compatible = "rockchip,rk3588-dwcmshc";
1119 reg = <0x0 0xfe2e0000 0x0 0x10000>;
1120 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
1121 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>;
1122 assigned-clock-rates = <200000000>, <24000000>, <200000000>;
1123 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
1124 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
1125 <&cru TMCLK_EMMC>;
1126 clock-names = "core", "bus", "axi", "block", "timer";
1127 max-frequency = <200000000>;
1128 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
1129 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
1130 <&cru SRST_T_EMMC>;
1131 reset-names = "core", "bus", "axi", "block", "timer";
1132 status = "disabled";
1133 };
1134
1135 gic: interrupt-controller@fe600000 {
1136 compatible = "arm,gic-v3";
1137 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
1138 <0x0 0xfe680000 0 0x100000>; /* GICR */
1139 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
1140 interrupt-controller;
1141 mbi-alias = <0x0 0xfe610000>;
1142 mbi-ranges = <424 56>;
1143 msi-controller;
1144 #interrupt-cells = <4>;
1145
1146 ppi-partitions {
1147 ppi_partition0: interrupt-partition-0 {
1148 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
1149 };
1150
1151 ppi_partition1: interrupt-partition-1 {
1152 affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>;
1153 };
1154 };
1155 };
1156
1157 dmac0: dma-controller@fea10000 {
1158 compatible = "arm,pl330", "arm,primecell";
1159 reg = <0x0 0xfea10000 0x0 0x4000>;
1160 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>,
1161 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>;
1162 arm,pl330-periph-burst;
1163 clocks = <&cru ACLK_DMAC0>;
1164 clock-names = "apb_pclk";
1165 #dma-cells = <1>;
1166 };
1167
1168 dmac1: dma-controller@fea30000 {
1169 compatible = "arm,pl330", "arm,primecell";
1170 reg = <0x0 0xfea30000 0x0 0x4000>;
1171 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>,
1172 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>;
1173 arm,pl330-periph-burst;
1174 clocks = <&cru ACLK_DMAC1>;
1175 clock-names = "apb_pclk";
1176 #dma-cells = <1>;
1177 };
1178
1179 i2c1: i2c@fea90000 {
1180 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1181 reg = <0x0 0xfea90000 0x0 0x1000>;
1182 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
1183 clock-names = "i2c", "pclk";
1184 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>;
1185 pinctrl-0 = <&i2c1m0_xfer>;
1186 pinctrl-names = "default";
1187 #address-cells = <1>;
1188 #size-cells = <0>;
1189 status = "disabled";
1190 };
1191
1192 i2c2: i2c@feaa0000 {
1193 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1194 reg = <0x0 0xfeaa0000 0x0 0x1000>;
1195 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
1196 clock-names = "i2c", "pclk";
1197 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>;
1198 pinctrl-0 = <&i2c2m0_xfer>;
1199 pinctrl-names = "default";
1200 #address-cells = <1>;
1201 #size-cells = <0>;
1202 status = "disabled";
1203 };
1204
1205 i2c3: i2c@feab0000 {
1206 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1207 reg = <0x0 0xfeab0000 0x0 0x1000>;
1208 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
1209 clock-names = "i2c", "pclk";
1210 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>;
1211 pinctrl-0 = <&i2c3m0_xfer>;
1212 pinctrl-names = "default";
1213 #address-cells = <1>;
1214 #size-cells = <0>;
1215 status = "disabled";
1216 };
1217
1218 i2c4: i2c@feac0000 {
1219 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1220 reg = <0x0 0xfeac0000 0x0 0x1000>;
1221 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
1222 clock-names = "i2c", "pclk";
1223 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>;
1224 pinctrl-0 = <&i2c4m0_xfer>;
1225 pinctrl-names = "default";
1226 #address-cells = <1>;
1227 #size-cells = <0>;
1228 status = "disabled";
1229 };
1230
1231 i2c5: i2c@fead0000 {
1232 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1233 reg = <0x0 0xfead0000 0x0 0x1000>;
1234 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
1235 clock-names = "i2c", "pclk";
1236 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>;
1237 pinctrl-0 = <&i2c5m0_xfer>;
1238 pinctrl-names = "default";
1239 #address-cells = <1>;
1240 #size-cells = <0>;
1241 status = "disabled";
1242 };
1243
1244 spi0: spi@feb00000 {
1245 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1246 reg = <0x0 0xfeb00000 0x0 0x1000>;
1247 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>;
1248 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
1249 clock-names = "spiclk", "apb_pclk";
1250 dmas = <&dmac0 14>, <&dmac0 15>;
1251 dma-names = "tx", "rx";
1252 num-cs = <2>;
1253 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1254 pinctrl-names = "default";
1255 #address-cells = <1>;
1256 #size-cells = <0>;
1257 status = "disabled";
1258 };
1259
1260 spi1: spi@feb10000 {
1261 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1262 reg = <0x0 0xfeb10000 0x0 0x1000>;
1263 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>;
1264 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
1265 clock-names = "spiclk", "apb_pclk";
1266 dmas = <&dmac0 16>, <&dmac0 17>;
1267 dma-names = "tx", "rx";
1268 num-cs = <2>;
1269 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
1270 pinctrl-names = "default";
1271 #address-cells = <1>;
1272 #size-cells = <0>;
1273 status = "disabled";
1274 };
1275
1276 spi2: spi@feb20000 {
1277 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1278 reg = <0x0 0xfeb20000 0x0 0x1000>;
1279 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>;
1280 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
1281 clock-names = "spiclk", "apb_pclk";
1282 dmas = <&dmac1 15>, <&dmac1 16>;
1283 dma-names = "tx", "rx";
1284 num-cs = <2>;
1285 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
1286 pinctrl-names = "default";
1287 #address-cells = <1>;
1288 #size-cells = <0>;
1289 status = "disabled";
1290 };
1291
1292 spi3: spi@feb30000 {
1293 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1294 reg = <0x0 0xfeb30000 0x0 0x1000>;
1295 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>;
1296 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
1297 clock-names = "spiclk", "apb_pclk";
1298 dmas = <&dmac1 17>, <&dmac1 18>;
1299 dma-names = "tx", "rx";
1300 num-cs = <2>;
1301 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
1302 pinctrl-names = "default";
1303 #address-cells = <1>;
1304 #size-cells = <0>;
1305 status = "disabled";
1306 };
1307
1308 uart1: serial@feb40000 {
1309 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1310 reg = <0x0 0xfeb40000 0x0 0x100>;
1311 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>;
1312 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
1313 clock-names = "baudclk", "apb_pclk";
1314 dmas = <&dmac0 8>, <&dmac0 9>;
1315 dma-names = "tx", "rx";
1316 pinctrl-0 = <&uart1m1_xfer>;
1317 pinctrl-names = "default";
1318 reg-io-width = <4>;
1319 reg-shift = <2>;
1320 status = "disabled";
1321 };
1322
1323 uart2: serial@feb50000 {
1324 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1325 reg = <0x0 0xfeb50000 0x0 0x100>;
1326 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>;
1327 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
1328 clock-names = "baudclk", "apb_pclk";
1329 dmas = <&dmac0 10>, <&dmac0 11>;
1330 dma-names = "tx", "rx";
1331 pinctrl-0 = <&uart2m1_xfer>;
1332 pinctrl-names = "default";
1333 reg-io-width = <4>;
1334 reg-shift = <2>;
1335 status = "disabled";
1336 };
1337
1338 uart3: serial@feb60000 {
1339 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1340 reg = <0x0 0xfeb60000 0x0 0x100>;
1341 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>;
1342 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
1343 clock-names = "baudclk", "apb_pclk";
1344 dmas = <&dmac0 12>, <&dmac0 13>;
1345 dma-names = "tx", "rx";
1346 pinctrl-0 = <&uart3m1_xfer>;
1347 pinctrl-names = "default";
1348 reg-io-width = <4>;
1349 reg-shift = <2>;
1350 status = "disabled";
1351 };
1352
1353 uart4: serial@feb70000 {
1354 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1355 reg = <0x0 0xfeb70000 0x0 0x100>;
1356 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>;
1357 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
1358 clock-names = "baudclk", "apb_pclk";
1359 dmas = <&dmac1 9>, <&dmac1 10>;
1360 dma-names = "tx", "rx";
1361 pinctrl-0 = <&uart4m1_xfer>;
1362 pinctrl-names = "default";
1363 reg-io-width = <4>;
1364 reg-shift = <2>;
1365 status = "disabled";
1366 };
1367
1368 uart5: serial@feb80000 {
1369 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1370 reg = <0x0 0xfeb80000 0x0 0x100>;
1371 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>;
1372 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
1373 clock-names = "baudclk", "apb_pclk";
1374 dmas = <&dmac1 11>, <&dmac1 12>;
1375 dma-names = "tx", "rx";
1376 pinctrl-0 = <&uart5m1_xfer>;
1377 pinctrl-names = "default";
1378 reg-io-width = <4>;
1379 reg-shift = <2>;
1380 status = "disabled";
1381 };
1382
1383 uart6: serial@feb90000 {
1384 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1385 reg = <0x0 0xfeb90000 0x0 0x100>;
1386 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>;
1387 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
1388 clock-names = "baudclk", "apb_pclk";
1389 dmas = <&dmac1 13>, <&dmac1 14>;
1390 dma-names = "tx", "rx";
1391 pinctrl-0 = <&uart6m1_xfer>;
1392 pinctrl-names = "default";
1393 reg-io-width = <4>;
1394 reg-shift = <2>;
1395 status = "disabled";
1396 };
1397
1398 uart7: serial@feba0000 {
1399 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1400 reg = <0x0 0xfeba0000 0x0 0x100>;
1401 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>;
1402 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
1403 clock-names = "baudclk", "apb_pclk";
1404 dmas = <&dmac2 7>, <&dmac2 8>;
1405 dma-names = "tx", "rx";
1406 pinctrl-0 = <&uart7m1_xfer>;
1407 pinctrl-names = "default";
1408 reg-io-width = <4>;
1409 reg-shift = <2>;
1410 status = "disabled";
1411 };
1412
1413 uart8: serial@febb0000 {
1414 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1415 reg = <0x0 0xfebb0000 0x0 0x100>;
1416 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>;
1417 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
1418 clock-names = "baudclk", "apb_pclk";
1419 dmas = <&dmac2 9>, <&dmac2 10>;
1420 dma-names = "tx", "rx";
1421 pinctrl-0 = <&uart8m1_xfer>;
1422 pinctrl-names = "default";
1423 reg-io-width = <4>;
1424 reg-shift = <2>;
1425 status = "disabled";
1426 };
1427
1428 uart9: serial@febc0000 {
1429 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1430 reg = <0x0 0xfebc0000 0x0 0x100>;
1431 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>;
1432 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
1433 clock-names = "baudclk", "apb_pclk";
1434 dmas = <&dmac2 11>, <&dmac2 12>;
1435 dma-names = "tx", "rx";
1436 pinctrl-0 = <&uart9m1_xfer>;
1437 pinctrl-names = "default";
1438 reg-io-width = <4>;
1439 reg-shift = <2>;
1440 status = "disabled";
1441 };
1442
1443 pwm4: pwm@febd0000 {
1444 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1445 reg = <0x0 0xfebd0000 0x0 0x10>;
1446 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1447 clock-names = "pwm", "pclk";
1448 pinctrl-0 = <&pwm4m0_pins>;
1449 pinctrl-names = "default";
1450 #pwm-cells = <3>;
1451 status = "disabled";
1452 };
1453
1454 pwm5: pwm@febd0010 {
1455 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1456 reg = <0x0 0xfebd0010 0x0 0x10>;
1457 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1458 clock-names = "pwm", "pclk";
1459 pinctrl-0 = <&pwm5m0_pins>;
1460 pinctrl-names = "default";
1461 #pwm-cells = <3>;
1462 status = "disabled";
1463 };
1464
1465 pwm6: pwm@febd0020 {
1466 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1467 reg = <0x0 0xfebd0020 0x0 0x10>;
1468 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1469 clock-names = "pwm", "pclk";
1470 pinctrl-0 = <&pwm6m0_pins>;
1471 pinctrl-names = "default";
1472 #pwm-cells = <3>;
1473 status = "disabled";
1474 };
1475
1476 pwm7: pwm@febd0030 {
1477 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1478 reg = <0x0 0xfebd0030 0x0 0x10>;
1479 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1480 clock-names = "pwm", "pclk";
1481 pinctrl-0 = <&pwm7m0_pins>;
1482 pinctrl-names = "default";
1483 #pwm-cells = <3>;
1484 status = "disabled";
1485 };
1486
1487 pwm8: pwm@febe0000 {
1488 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1489 reg = <0x0 0xfebe0000 0x0 0x10>;
1490 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1491 clock-names = "pwm", "pclk";
1492 pinctrl-0 = <&pwm8m0_pins>;
1493 pinctrl-names = "default";
1494 #pwm-cells = <3>;
1495 status = "disabled";
1496 };
1497
1498 pwm9: pwm@febe0010 {
1499 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1500 reg = <0x0 0xfebe0010 0x0 0x10>;
1501 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1502 clock-names = "pwm", "pclk";
1503 pinctrl-0 = <&pwm9m0_pins>;
1504 pinctrl-names = "default";
1505 #pwm-cells = <3>;
1506 status = "disabled";
1507 };
1508
1509 pwm10: pwm@febe0020 {
1510 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1511 reg = <0x0 0xfebe0020 0x0 0x10>;
1512 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1513 clock-names = "pwm", "pclk";
1514 pinctrl-0 = <&pwm10m0_pins>;
1515 pinctrl-names = "default";
1516 #pwm-cells = <3>;
1517 status = "disabled";
1518 };
1519
1520 pwm11: pwm@febe0030 {
1521 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1522 reg = <0x0 0xfebe0030 0x0 0x10>;
1523 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1524 clock-names = "pwm", "pclk";
1525 pinctrl-0 = <&pwm11m0_pins>;
1526 pinctrl-names = "default";
1527 #pwm-cells = <3>;
1528 status = "disabled";
1529 };
1530
1531 pwm12: pwm@febf0000 {
1532 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1533 reg = <0x0 0xfebf0000 0x0 0x10>;
1534 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1535 clock-names = "pwm", "pclk";
1536 pinctrl-0 = <&pwm12m0_pins>;
1537 pinctrl-names = "default";
1538 #pwm-cells = <3>;
1539 status = "disabled";
1540 };
1541
1542 pwm13: pwm@febf0010 {
1543 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1544 reg = <0x0 0xfebf0010 0x0 0x10>;
1545 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1546 clock-names = "pwm", "pclk";
1547 pinctrl-0 = <&pwm13m0_pins>;
1548 pinctrl-names = "default";
1549 #pwm-cells = <3>;
1550 status = "disabled";
1551 };
1552
1553 pwm14: pwm@febf0020 {
1554 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1555 reg = <0x0 0xfebf0020 0x0 0x10>;
1556 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1557 clock-names = "pwm", "pclk";
1558 pinctrl-0 = <&pwm14m0_pins>;
1559 pinctrl-names = "default";
1560 #pwm-cells = <3>;
1561 status = "disabled";
1562 };
1563
1564 pwm15: pwm@febf0030 {
1565 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1566 reg = <0x0 0xfebf0030 0x0 0x10>;
1567 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1568 clock-names = "pwm", "pclk";
1569 pinctrl-0 = <&pwm15m0_pins>;
1570 pinctrl-names = "default";
1571 #pwm-cells = <3>;
1572 status = "disabled";
1573 };
1574
1575 i2c6: i2c@fec80000 {
1576 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1577 reg = <0x0 0xfec80000 0x0 0x1000>;
1578 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
1579 clock-names = "i2c", "pclk";
1580 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>;
1581 pinctrl-0 = <&i2c6m0_xfer>;
1582 pinctrl-names = "default";
1583 #address-cells = <1>;
1584 #size-cells = <0>;
1585 status = "disabled";
1586 };
1587
1588 i2c7: i2c@fec90000 {
1589 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1590 reg = <0x0 0xfec90000 0x0 0x1000>;
1591 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
1592 clock-names = "i2c", "pclk";
1593 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
1594 pinctrl-0 = <&i2c7m0_xfer>;
1595 pinctrl-names = "default";
1596 #address-cells = <1>;
1597 #size-cells = <0>;
1598 status = "disabled";
1599 };
1600
1601 i2c8: i2c@feca0000 {
1602 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1603 reg = <0x0 0xfeca0000 0x0 0x1000>;
1604 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>;
1605 clock-names = "i2c", "pclk";
1606 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>;
1607 pinctrl-0 = <&i2c8m0_xfer>;
1608 pinctrl-names = "default";
1609 #address-cells = <1>;
1610 #size-cells = <0>;
1611 status = "disabled";
1612 };
1613
1614 spi4: spi@fecb0000 {
1615 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1616 reg = <0x0 0xfecb0000 0x0 0x1000>;
1617 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>;
1618 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>;
1619 clock-names = "spiclk", "apb_pclk";
1620 dmas = <&dmac2 13>, <&dmac2 14>;
1621 dma-names = "tx", "rx";
1622 num-cs = <2>;
1623 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
1624 pinctrl-names = "default";
1625 #address-cells = <1>;
1626 #size-cells = <0>;
1627 status = "disabled";
1628 };
1629
1630 dmac2: dma-controller@fed10000 {
1631 compatible = "arm,pl330", "arm,primecell";
1632 reg = <0x0 0xfed10000 0x0 0x4000>;
1633 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>,
1634 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>;
1635 arm,pl330-periph-burst;
1636 clocks = <&cru ACLK_DMAC2>;
1637 clock-names = "apb_pclk";
1638 #dma-cells = <1>;
1639 };
1640
1641 system_sram2: sram@ff001000 {
1642 compatible = "mmio-sram";
1643 reg = <0x0 0xff001000 0x0 0xef000>;
1644 ranges = <0x0 0x0 0xff001000 0xef000>;
1645 #address-cells = <1>;
1646 #size-cells = <1>;
1647 };
1648
1649 pinctrl: pinctrl {
1650 compatible = "rockchip,rk3588-pinctrl";
1651 ranges;
1652 rockchip,grf = <&ioc>;
1653 #address-cells = <2>;
1654 #size-cells = <2>;
1655
1656 gpio0: gpio@fd8a0000 {
1657 compatible = "rockchip,gpio-bank";
1658 reg = <0x0 0xfd8a0000 0x0 0x100>;
1659 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
1660 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
1661 gpio-controller;
1662 gpio-ranges = <&pinctrl 0 0 32>;
1663 interrupt-controller;
1664 #gpio-cells = <2>;
1665 #interrupt-cells = <2>;
1666 };
1667
1668 gpio1: gpio@fec20000 {
1669 compatible = "rockchip,gpio-bank";
1670 reg = <0x0 0xfec20000 0x0 0x100>;
1671 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>;
1672 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
1673 gpio-controller;
1674 gpio-ranges = <&pinctrl 0 32 32>;
1675 interrupt-controller;
1676 #gpio-cells = <2>;
1677 #interrupt-cells = <2>;
1678 };
1679
1680 gpio2: gpio@fec30000 {
1681 compatible = "rockchip,gpio-bank";
1682 reg = <0x0 0xfec30000 0x0 0x100>;
1683 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>;
1684 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
1685 gpio-controller;
1686 gpio-ranges = <&pinctrl 0 64 32>;
1687 interrupt-controller;
1688 #gpio-cells = <2>;
1689 #interrupt-cells = <2>;
1690 };
1691
1692 gpio3: gpio@fec40000 {
1693 compatible = "rockchip,gpio-bank";
1694 reg = <0x0 0xfec40000 0x0 0x100>;
1695 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>;
1696 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
1697 gpio-controller;
1698 gpio-ranges = <&pinctrl 0 96 32>;
1699 interrupt-controller;
1700 #gpio-cells = <2>;
1701 #interrupt-cells = <2>;
1702 };
1703
1704 gpio4: gpio@fec50000 {
1705 compatible = "rockchip,gpio-bank";
1706 reg = <0x0 0xfec50000 0x0 0x100>;
1707 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>;
1708 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
1709 gpio-controller;
1710 gpio-ranges = <&pinctrl 0 128 32>;
1711 interrupt-controller;
1712 #gpio-cells = <2>;
1713 #interrupt-cells = <2>;
1714 };
1715 };
1716};
1717
1718#include "rk3588s-pinctrl.dtsi"