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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Stefan Roeseb0f80b92015-01-19 11:33:42 +01002
3#include <config.h>
Stefan Roeseb0f80b92015-01-19 11:33:42 +01004#include <linux/linkage.h>
5
Stefan Roese944c7a32015-08-25 13:49:41 +02006ENTRY(save_boot_params)
7 stmfd sp!, {r0 - r12, lr} /* @ save registers on stack */
8 ldr r12, =CONFIG_SPL_BOOTROM_SAVE
9 str sp, [r12]
10 b save_boot_params_ret
11ENDPROC(save_boot_params)
12
13ENTRY(return_to_bootrom)
14 ldr r12, =CONFIG_SPL_BOOTROM_SAVE
15 ldr sp, [r12]
16 mov r0, #0x0 /* @ return value: 0x0 NO_ERR */
17 ldmfd sp!, {r0 - r12, pc} /* @ restore regs and return */
18ENDPROC(return_to_bootrom)
Stefan Roeseb0f80b92015-01-19 11:33:42 +010019
20/*
21 * cache_inv - invalidate Cache line
22 * r0 - dest
23 */
24 .global cache_inv
25 .type cache_inv, %function
26 cache_inv:
27
28 stmfd sp!, {r1-r12}
29
30 mcr p15, 0, r0, c7, c6, 1
31
32 ldmfd sp!, {r1-r12}
33 bx lr
34
35
36/*
37 * flush_l1_v6 - l1 cache clean invalidate
38 * r0 - dest
39 */
40 .global flush_l1_v6
41 .type flush_l1_v6, %function
42 flush_l1_v6:
43
44 stmfd sp!, {r1-r12}
45
46 mcr p15, 0, r0, c7, c10, 5 /* @ data memory barrier */
47 mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
48 mcr p15, 0, r0, c7, c10, 4 /* @ data sync barrier */
49
50 ldmfd sp!, {r1-r12}
51 bx lr
52
53
54/*
55 * flush_l1_v7 - l1 cache clean invalidate
56 * r0 - dest
57 */
58 .global flush_l1_v7
59 .type flush_l1_v7, %function
60 flush_l1_v7:
61
62 stmfd sp!, {r1-r12}
63
64 dmb /* @data memory barrier */
65 mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
66 dsb /* @data sync barrier */
67
68 ldmfd sp!, {r1-r12}
69 bx lr