blob: 7c58f684b8a3529a2ee36fb17a571fed2f83d68d [file] [log] [blame]
wdenk8966f332002-10-31 23:30:59 +00001/*
2 * (C) Copyright 2000, 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * (C) Copyright 2001
5 * Torsten Stevens, FHG IMS, stevens@ims.fhg.de
6 * Bruno Achauer, Exet AG, bruno@exet-ag.de.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/*
28 * board/config.h - configuration options, board specific
29 * [derived from config_TQM850L.h]
30 */
31
32#ifndef __CONFIG_H
33#define __CONFIG_H
34
35/*
36 * High Level Configuration Options
37 * (easy to change)
38 */
39
40#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
41#define CONFIG_LANTEC 2 /* ...on a Lantec rev.2 board */
42
Wolfgang Denk2ae18242010-10-06 09:05:45 +020043#define CONFIG_SYS_TEXT_BASE 0x40000000
44
wdenk8966f332002-10-31 23:30:59 +000045/*
46 * Port assignments (CONFIG_LANTEC == 1):
47 * - SMC1: J11 (MDB) ?
48 * - SMC2: J6 (Feature connector)
49 * - SCC2: J9 (RJ45)
50 * - SCC3: J8 (Sub-D9)
51 *
52 * Port assignments (CONFIG_LANTEC == 2): TBD
53 */
54
55
56#undef CONFIG_8xx_CONS_SMC2 /* Console is on SMC2 */
57#define CONFIG_8xx_CONS_SCC3
58#undef CONFIG_8xx_CONS_NONE
59#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */
60#if 0
61#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
62#else
63#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
64#endif
65
66#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
67
68#undef CONFIG_BOOTARGS
69#define CONFIG_BOOTCOMMAND \
70 "setenv bootargs root=/dev/ram panic=5;bootm 40040000 400A0000"
71
72#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenk8966f332002-10-31 23:30:59 +000074
75#undef CONFIG_WATCHDOG /* watchdog disabled */
76
77#define CONFIG_STATUS_LED 1 /* Status LED enabled */
78
Jon Loeliger7be044e2007-07-09 21:24:19 -050079/*
80 * BOOTP options
81 */
82#define CONFIG_BOOTP_SUBNETMASK
83#define CONFIG_BOOTP_GATEWAY
84#define CONFIG_BOOTP_HOSTNAME
85#define CONFIG_BOOTP_BOOTPATH
86#define CONFIG_BOOTP_BOOTFILESIZE
wdenk8966f332002-10-31 23:30:59 +000087
Jon Loeliger348f2582007-07-08 13:46:18 -050088
89/*
90 * Command line configuration.
91 */
Jean-Christophe PLAGNIOL-VILLARD4e620412007-10-24 18:16:01 +020092#include <config_cmd_default.h>
Jon Loeliger348f2582007-07-08 13:46:18 -050093
Jean-Christophe PLAGNIOL-VILLARD4e620412007-10-24 18:16:01 +020094#define CONFIG_CMD_ASKENV
95#define CONFIG_CMD_CACHE
96#define CONFIG_CMD_CDP
97#define CONFIG_CMD_DATE
98#define CONFIG_CMD_DHCP
99#define CONFIG_CMD_DIAG
100#define CONFIG_CMD_FAT
101#define CONFIG_CMD_IMMAP
102#define CONFIG_CMD_PING
103#define CONFIG_CMD_PORTIO
104#define CONFIG_CMD_REGINFO
105#define CONFIG_CMD_SAVES
106#define CONFIG_CMD_SDRAM
107#define CONFIG_CMD_SNTP
108
Jon Loeliger348f2582007-07-08 13:46:18 -0500109#undef CONFIG_CMD_XIMG
110
111#if !(CONFIG_LANTEC >= 2)
112 #undef CONFIG_CMD_DATE
113 #undef CONFIG_CMD_NET
114#endif
115
wdenk8966f332002-10-31 23:30:59 +0000116
117#if CONFIG_LANTEC >= 2
118#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
119#endif
120
wdenk8966f332002-10-31 23:30:59 +0000121/*
122 * Miscellaneous configurable options
123 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_LONGHELP /* undef to save memory */
125#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger348f2582007-07-08 13:46:18 -0500126#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk8966f332002-10-31 23:30:59 +0000128#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk8966f332002-10-31 23:30:59 +0000130#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
132#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
133#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk8966f332002-10-31 23:30:59 +0000134
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
136#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenk8966f332002-10-31 23:30:59 +0000137
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk8966f332002-10-31 23:30:59 +0000139
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk8966f332002-10-31 23:30:59 +0000141
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk8966f332002-10-31 23:30:59 +0000143
144/*
145 * Low Level Configuration Settings
146 * (address mappings, register initial values, etc.)
147 * You should know what you are doing if you make changes here.
148 */
149/*-----------------------------------------------------------------------
150 * Internal Memory Mapped Register
151 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_IMMR 0xFFF00000
wdenk8966f332002-10-31 23:30:59 +0000153
154/*-----------------------------------------------------------------------
155 * Definitions for initial stack pointer and data area (in DPRAM)
156 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
158#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
159#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
160#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
161#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk8966f332002-10-31 23:30:59 +0000162
163/*-----------------------------------------------------------------------
164 * Start addresses for the final memory configuration
165 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk8966f332002-10-31 23:30:59 +0000167 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_SDRAM_BASE 0x00000000
169#define CONFIG_SYS_FLASH_BASE 0x40000000
170#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
171#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
172#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk8966f332002-10-31 23:30:59 +0000173
174/*
175 * For booting Linux, the board info and command line data
176 * have to be in the first 8 MB of memory, since this is
177 * the maximum mapped by the Linux kernel during initialization.
178 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk8966f332002-10-31 23:30:59 +0000180
181/*-----------------------------------------------------------------------
182 * FLASH organization
183 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
185#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
wdenk8966f332002-10-31 23:30:59 +0000186
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
188#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk8966f332002-10-31 23:30:59 +0000189
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200190#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200191#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
192#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
wdenk8966f332002-10-31 23:30:59 +0000193
194/*-----------------------------------------------------------------------
195 * Cache Configuration
196 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger348f2582007-07-08 13:46:18 -0500198#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenk8966f332002-10-31 23:30:59 +0000200#endif
201
202/*-----------------------------------------------------------------------
203 * SYPCR - System Protection Control 11-9
204 * SYPCR can only be written once after reset!
205 *-----------------------------------------------------------------------
206 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
207 */
208#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk8966f332002-10-31 23:30:59 +0000210 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
211#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenk8966f332002-10-31 23:30:59 +0000213#endif
214
215/*-----------------------------------------------------------------------
216 * SIUMCR - SIU Module Configuration 11-6
217 *-----------------------------------------------------------------------
218 * PCMCIA config., multi-function pin tri-state
219 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_DLK)
wdenk8966f332002-10-31 23:30:59 +0000221
222/*-----------------------------------------------------------------------
223 * Clock Setting - Has the Lantec board a 32kHz clock ??? [XXX]
224 *-----------------------------------------------------------------------
225 */
226#define CONFIG_8xx_GCLK_FREQ 33000000
227
228/*-----------------------------------------------------------------------
229 * TBSCR - Time Base Status and Control 11-26
230 *-----------------------------------------------------------------------
231 * Clear Reference Interrupt Status, Timebase freezing enabled
232 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenk8966f332002-10-31 23:30:59 +0000234
235/*-----------------------------------------------------------------------
236 * RTCSC - Real-Time Clock Status and Control Register 11-27
237 *-----------------------------------------------------------------------
238 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenk8966f332002-10-31 23:30:59 +0000240
241/*-----------------------------------------------------------------------
242 * PISCR - Periodic Interrupt Status and Control 11-31
243 *-----------------------------------------------------------------------
244 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
245 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenk8966f332002-10-31 23:30:59 +0000247
248/*-----------------------------------------------------------------------
249 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
250 *-----------------------------------------------------------------------
251 * Reset PLL lock status sticky bit, timer expired status bit and timer
252 * interrupt status bit
253 *
254 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
255 */
256 /* up to 50 MHz we use a 1:1 clock */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenk8966f332002-10-31 23:30:59 +0000258
259/*-----------------------------------------------------------------------
260 * SCCR - System Clock and reset Control Register 15-27
261 *-----------------------------------------------------------------------
262 * Set clock output, timebase and RTC source and divider,
263 * power management and some other internal clocks
264 */
265#define SCCR_MASK SCCR_EBDF11
266 /* up to 50 MHz we use a 1:1 clock */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_SCCR (SCCR_TBS | \
wdenk8966f332002-10-31 23:30:59 +0000268 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
269 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
270 SCCR_DFALCD00)
271
272/*-----------------------------------------------------------------------
273 *
274 *-----------------------------------------------------------------------
275 *
276 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_DER 0
wdenk8966f332002-10-31 23:30:59 +0000278
279/*
280 * Init Memory Controller:
281 *
282 * BR0/5 and OR0/5 (FLASH)
283 */
284
285#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
286#define FLASH_BASE5_PRELIM 0x60000000 /* FLASH bank #1 */
287
288/* used to re-map FLASH both when starting from SRAM or FLASH:
289 * restrict access enough to keep SRAM working (if any)
290 * but not too much to meddle with FLASH accesses
291 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
293#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenk8966f332002-10-31 23:30:59 +0000294
295/* FLASH timing */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | \
wdenk8bde7f72003-06-27 21:31:46 +0000297 OR_SCY_5_CLK | OR_TRLX)
wdenk8966f332002-10-31 23:30:59 +0000298
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
300#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
301#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenk8966f332002-10-31 23:30:59 +0000302
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_OR5_REMAP CONFIG_SYS_OR0_REMAP
304#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_OR0_PRELIM
305#define CONFIG_SYS_BR5_PRELIM ((FLASH_BASE5_PRELIM & BR_BA_MSK) | BR_V )
wdenk8966f332002-10-31 23:30:59 +0000306
307/*
308 * BR2/3 and OR2/3 (SDRAM)
309 *
310 */
311#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
312#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
313
314/* SDRAM timing: Multiplexed addresses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM)
wdenk8966f332002-10-31 23:30:59 +0000316
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_OR3_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
318#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenk8966f332002-10-31 23:30:59 +0000319
320/*
321 * Memory Periodic Timer Prescaler
322 */
323
324/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
326#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenk8966f332002-10-31 23:30:59 +0000327
328/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
330#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenk8966f332002-10-31 23:30:59 +0000331
332/*
333 * MAMR settings for SDRAM
334 */
335/* periodic timer for refresh */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
wdenk8966f332002-10-31 23:30:59 +0000337
338/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_MAMR_8COL \
340 ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk8966f332002-10-31 23:30:59 +0000341 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
342 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
343
344/*
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200345 * JFFS2 partitions
346 *
347 */
348/* No command line, one static partition, whole device */
Stefan Roese68d7d652009-03-19 13:30:36 +0100349#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200350#define CONFIG_JFFS2_DEV "nor0"
351#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
352#define CONFIG_JFFS2_PART_OFFSET 0x00000000
353
354/* mtdparts command line support */
355/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100356#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200357#define MTDIDS_DEFAULT ""
358#define MTDPARTS_DEFAULT ""
359*/
360
wdenk8966f332002-10-31 23:30:59 +0000361#endif /* __CONFIG_H */