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TsiChung Liew536e7da2008-10-22 11:38:21 +00001/*
2 * Configuation settings for the Freescale MCF53017EVB.
3 *
4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/*
27 * board/config.h - configuration options, board specific
28 */
29
30#ifndef _M53017EVB_H
31#define _M53017EVB_H
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37#define CONFIG_MCF5301x /* define processor family */
38#define CONFIG_M53015 /* define processor type */
39
40#define CONFIG_MCFUART
41#define CONFIG_SYS_UART_PORT (0)
42#define CONFIG_BAUDRATE 115200
43#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
44
45#undef CONFIG_WATCHDOG
46#define CONFIG_WATCHDOG_TIMEOUT 5000
47
48/* Command line configuration */
49#include <config_cmd_default.h>
50
51#define CONFIG_CMD_CACHE
52#define CONFIG_CMD_DATE
53#define CONFIG_CMD_ELF
54#define CONFIG_CMD_FLASH
55#undef CONFIG_CMD_I2C
56#define CONFIG_CMD_MEMORY
57#define CONFIG_CMD_MISC
58#define CONFIG_CMD_MII
59#define CONFIG_CMD_NET
60#define CONFIG_CMD_PING
61#define CONFIG_CMD_REGINFO
62
63#define CONFIG_SYS_UNIFY_CACHE
64
65#define CONFIG_MCFFEC
66#ifdef CONFIG_MCFFEC
67# define CONFIG_NET_MULTI 1
68# define CONFIG_MII 1
69# define CONFIG_MII_INIT 1
70# define CONFIG_SYS_DISCOVER_PHY
71# define CONFIG_SYS_RX_ETH_BUFFER 8
TsiChung Liew9e8e9272010-03-10 18:24:07 -060072# define CONFIG_SYS_TX_ETH_BUFFER 8
73# define CONFIG_SYS_FEC_BUF_USE_SRAM
TsiChung Liew536e7da2008-10-22 11:38:21 +000074# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
75# define CONFIG_HAS_ETH1
76
77# define CONFIG_SYS_FEC0_PINMUX 0
78# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
79# define CONFIG_SYS_FEC1_PINMUX 0
80# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE
81# define MCFFEC_TOUT_LOOP 50000
TsiChung Liew052c0892009-07-08 07:41:24 +000082
83# define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2"
84
TsiChung Liew536e7da2008-10-22 11:38:21 +000085/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
86# ifndef CONFIG_SYS_DISCOVER_PHY
87# define FECDUPLEX FULL
88# define FECSPEED _100BASET
89# else
90# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
91# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
92# endif
93# endif /* CONFIG_SYS_DISCOVER_PHY */
94#endif
95
96#define CONFIG_MCFRTC
97#undef RTC_DEBUG
98#define CONFIG_SYS_RTC_CNT (0x8000)
99#define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
100
101/* Timer */
102#define CONFIG_MCFTMR
103#undef CONFIG_MCFPIT
104
105/* I2C */
106#define CONFIG_FSL_I2C
107#define CONFIG_HARD_I2C /* I2C with hw support */
108#undef CONFIG_SOFT_I2C /* I2C bit-banged */
109#define CONFIG_SYS_I2C_SPEED 80000
110#define CONFIG_SYS_I2C_SLAVE 0x7F
111#define CONFIG_SYS_I2C_OFFSET 0x58000
112#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
113
114#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
115#define CONFIG_UDP_CHECKSUM
116
117#ifdef CONFIG_MCFFEC
118# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
119# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
120# define CONFIG_IPADDR 192.162.1.2
121# define CONFIG_NETMASK 255.255.255.0
122# define CONFIG_SERVERIP 192.162.1.1
123# define CONFIG_GATEWAYIP 192.162.1.1
124# define CONFIG_OVERWRITE_ETHADDR_ONCE
125#endif /* FEC_ENET */
126
127#define CONFIG_HOSTNAME M53017
128#define CONFIG_EXTRA_ENV_SETTINGS \
129 "netdev=eth0\0" \
130 "loadaddr=40010000\0" \
131 "u-boot=u-boot.bin\0" \
132 "load=tftp ${loadaddr) ${u-boot}\0" \
133 "upd=run load; run prog\0" \
134 "prog=prot off 0 3ffff;" \
135 "era 0 3ffff;" \
136 "cp.b ${loadaddr} 0 ${filesize};" \
137 "save\0" \
138 ""
139
140#define CONFIG_PRAM 512 /* 512 KB */
141#define CONFIG_SYS_PROMPT "-> "
142#define CONFIG_SYS_LONGHELP /* undef to save memory */
143
144#ifdef CONFIG_CMD_KGDB
145# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
146#else
147# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
148#endif
149
150#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
151#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
152#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */
153#define CONFIG_SYS_LOAD_ADDR 0x40010000
154
155#define CONFIG_SYS_HZ 1000
156#define CONFIG_SYS_CLK 80000000
157#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
158
159#define CONFIG_SYS_MBAR 0xFC000000
160
161/*
162 * Low Level Configuration Settings
163 * (address mappings, register initial values, etc.)
164 * You should know what you are doing if you make changes here.
165 */
166/*
167 * Definitions for initial stack pointer and data area (in DPRAM)
168 */
169#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
170#define CONFIG_SYS_INIT_RAM_END 0x20000 /* End of used area in internal SRAM */
TsiChung Liew9e8e9272010-03-10 18:24:07 -0600171#define CONFIG_SYS_INIT_RAM_CTRL 0x221
TsiChung Liew536e7da2008-10-22 11:38:21 +0000172#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
173#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
174#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
175
176/*
177 * Start addresses for the final memory configuration
178 * (Set up by the startup code)
179 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
180 */
181#define CONFIG_SYS_SDRAM_BASE 0x40000000
182#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
183#define CONFIG_SYS_SDRAM_CFG1 0x43711630
184#define CONFIG_SYS_SDRAM_CFG2 0x56670000
TsiChung Liew9e8e9272010-03-10 18:24:07 -0600185#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
TsiChung Liew536e7da2008-10-22 11:38:21 +0000186#define CONFIG_SYS_SDRAM_EMOD 0x80010000
187#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
188
189#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
190#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
191
192#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
193#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
194
195#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
196#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
197
198/*
199 * For booting Linux, the board info and command line data
200 * have to be in the first 8 MB of memory, since this is
201 * the maximum mapped by the Linux kernel during initialization ??
202 */
203#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
TsiChung Liewd6e4baf2009-01-27 12:57:47 +0000204#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000205
206/*-----------------------------------------------------------------------
207 * FLASH organization
208 */
209#define CONFIG_SYS_FLASH_CFI
210#ifdef CONFIG_SYS_FLASH_CFI
211# define CONFIG_FLASH_CFI_DRIVER 1
TsiChung Liewbbf6bbf2009-06-11 12:50:05 +0000212# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
213# define CONFIG_FLASH_SPANSION_S29WS_N 1
TsiChung Liew4567c7b2009-06-12 11:31:31 +0000214# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
TsiChung Liew536e7da2008-10-22 11:38:21 +0000215# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
216# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
217# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
218# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
219#endif
220
221#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
222
223/* Configuration for environment
224 * Environment is embedded in u-boot in the second sector of the flash
225 */
226#define CONFIG_ENV_OFFSET 0x8000
227#define CONFIG_ENV_SIZE 0x1000
228#define CONFIG_ENV_SECT_SIZE 0x8000
229#define CONFIG_ENV_IS_IN_FLASH 1
230
231/*-----------------------------------------------------------------------
232 * Cache Configuration
233 */
234#define CONFIG_SYS_CACHELINE_SIZE 16
235
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600236#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
237 CONFIG_SYS_INIT_RAM_END - 8)
238#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
239 CONFIG_SYS_INIT_RAM_END - 4)
240#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
241#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
242 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
243 CF_ACR_EN | CF_ACR_SM_ALL)
244#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
245 CF_CACR_DCM_P)
246
TsiChung Liew536e7da2008-10-22 11:38:21 +0000247/*-----------------------------------------------------------------------
248 * Chipselect bank definitions
249 */
250/*
251 * CS0 - NOR Flash
252 * CS1 - Ext SRAM
253 * CS2 - Available
254 * CS3 - Available
255 * CS4 - Available
256 * CS5 - Available
257 */
258#define CONFIG_SYS_CS0_BASE 0
259#define CONFIG_SYS_CS0_MASK 0x00FF0001
260#define CONFIG_SYS_CS0_CTRL 0x00001FA0
261
262#define CONFIG_SYS_CS1_BASE 0xC0000000
263#define CONFIG_SYS_CS1_MASK 0x00070001
264#define CONFIG_SYS_CS1_CTRL 0x00001FA0
265
266#endif /* _M53017EVB_H */