blob: 0bbad161f6f8b0bad80435fbf49f1f4bde6fa083 [file] [log] [blame]
Sergei Poselenov5d108ac2008-04-30 11:42:50 +02001/*
2 * (C) Copyright 2008
3 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
4 *
5 * Wolfgang Denk <wd@denx.de>
6 * Copyright 2004 Freescale Semiconductor.
7 * (C) Copyright 2002,2003 Motorola,Inc.
8 * Xianghua Xiao <X.Xiao@motorola.com>
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29/*
30 * Socrates
31 */
32
33#ifndef __CONFIG_H
34#define __CONFIG_H
35
u-boot@bugs.denx.dee99b6072008-09-11 15:40:01 +020036/* new uImage format support */
37#define CONFIG_FIT 1
38#define CONFIG_OF_LIBFDT 1
39#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
40
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020041/* High Level Configuration Options */
42#define CONFIG_BOOKE 1 /* BOOKE */
43#define CONFIG_E500 1 /* BOOKE e500 family */
44#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
45#define CONFIG_MPC8544 1
46#define CONFIG_SOCRATES 1
47
Wolfgang Denk2ae18242010-10-06 09:05:45 +020048#define CONFIG_SYS_TEXT_BASE 0xfff80000
49
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020050#define CONFIG_PCI
51
52#define CONFIG_TSEC_ENET /* tsec ethernet support */
53
54#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
Detlev Zundel3e79b582008-08-15 15:42:12 +020055#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020056
57#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
58
59/*
60 * Only possible on E500 Version 2 or newer cores.
61 */
62#define CONFIG_ENABLE_36BIT_PHYS 1
63
64/*
65 * sysclk for MPC85xx
66 *
67 * Two valid values are:
68 * 33000000
69 * 66000000
70 *
71 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
72 * is likely the desired value here, so that is now the default.
73 * The board, however, can run at 66MHz. In any event, this value
74 * must match the settings of some switches. Details can be found
75 * in the README.mpc85xxads.
76 */
77
78#ifndef CONFIG_SYS_CLK_FREQ
79#define CONFIG_SYS_CLK_FREQ 66666666
80#endif
81
82/*
83 * These can be toggled for performance analysis, otherwise use default.
84 */
85#define CONFIG_L2_CACHE /* toggle L2 cache */
86#define CONFIG_BTB /* toggle branch predition */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020087
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020089
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
91#define CONFIG_SYS_MEMTEST_START 0x00400000
92#define CONFIG_SYS_MEMTEST_END 0x00C00000
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020093
94/*
95 * Base addresses -- Note these are effective addresses where the
96 * actual resources get mapped (not physical addresses)
97 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
99#define CONFIG_SYS_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
100#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
101#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200102
Kumar Galabe0bd822008-08-26 22:56:56 -0500103/* DDR Setup */
104#define CONFIG_FSL_DDR2
105#undef CONFIG_FSL_DDR_INTERACTIVE
106#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
107#define CONFIG_DDR_SPD
108
109#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
110#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
111
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
113#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Galabe0bd822008-08-26 22:56:56 -0500114#define CONFIG_VERY_BIG_RAM
115
116#define CONFIG_NUM_DDR_CONTROLLERS 1
117#define CONFIG_DIMM_SLOTS_PER_CTLR 1
118#define CONFIG_CHIP_SELECTS_PER_CTRL 2
119
120/* I2C addresses of SPD EEPROMs */
Anatolij Gustschin562788b2008-09-17 11:45:51 +0200121#define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200122
123#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
124
125/* Hardcoded values, to use instead of SPD */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
127#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
128#define CONFIG_SYS_DDR_TIMING_0 0x00260802
129#define CONFIG_SYS_DDR_TIMING_1 0x3935D322
130#define CONFIG_SYS_DDR_TIMING_2 0x14904CC8
131#define CONFIG_SYS_DDR_MODE 0x00480432
132#define CONFIG_SYS_DDR_INTERVAL 0x030C0100
133#define CONFIG_SYS_DDR_CONFIG_2 0x04400000
134#define CONFIG_SYS_DDR_CONFIG 0xC3008000
135#define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000
136#define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200137
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200138/*
139 * Flash on the LocalBus
140 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_FLASH0 0xFE000000
144#define CONFIG_SYS_FLASH1 0xFC000000
145#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200146
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */
148#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200149
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */
151#define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */
152#define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */
153#define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200154
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200156#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200157
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
159#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
160#undef CONFIG_SYS_FLASH_CHECKSUM
161#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
162#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200163
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200164#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200165
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
167#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
168#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
169#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200170
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_INIT_RAM_LOCK 1
172#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
173#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End used area in RAM */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200174
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data*/
176#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
177#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200178
Detlev Zundel47106ce2010-04-14 11:32:20 +0200179#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */
Detlev Zundel3e79b582008-08-15 15:42:12 +0200181
182/* FPGA and NAND */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_FPGA_BASE 0xc0000000
184#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */
185#define CONFIG_SYS_HMI_BASE 0xc0010000
186#define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */
187#define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */
Detlev Zundel3e79b582008-08-15 15:42:12 +0200188
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
190#define CONFIG_SYS_MAX_NAND_DEVICE 1
Detlev Zundel3e79b582008-08-15 15:42:12 +0200191#define CONFIG_CMD_NAND
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200192
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200193/* LIME GDC */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_LIME_BASE 0xc8000000
195#define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */
196#define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */
197#define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200198
199#define CONFIG_VIDEO
200#define CONFIG_VIDEO_MB862xx
Anatolij Gustschin5d16ca82009-10-23 12:03:14 +0200201#define CONFIG_VIDEO_MB862xx_ACCEL
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200202#define CONFIG_CFB_CONSOLE
203#define CONFIG_VIDEO_LOGO
204#define CONFIG_VIDEO_BMP_LOGO
205#define CONFIG_CONSOLE_EXTRA_INFO
206#define VIDEO_FB_16BPP_PIXEL_SWAP
Wolfgang Grandegger229b6dc2009-10-23 12:03:15 +0200207#define VIDEO_FB_16BPP_WORD_SWAP
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200208#define CONFIG_VGA_AS_SINGLE_DEVICE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_CONSOLE_IS_IN_ENV
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200210#define CONFIG_VIDEO_SW_CURSOR
211#define CONFIG_SPLASH_SCREEN
212#define CONFIG_VIDEO_BMP_GZIP
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200214
Wolfgang Grandeggerc28d3bb2009-10-23 12:03:13 +0200215/* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */
216#define CONFIG_SYS_MB862xx_CCF 0x10000
217/* SDRAM parameter */
218#define CONFIG_SYS_MB862xx_MMR 0x4157BA63
219
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200220/* Serial Port */
221
222#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_NS16550
224#define CONFIG_SYS_NS16550_SERIAL
225#define CONFIG_SYS_NS16550_REG_SIZE 1
226#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200227
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
229#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200230
231#define CONFIG_BAUDRATE 115200
232
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_BAUDRATE_TABLE \
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200234 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
235
236#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillips5be58f52010-07-14 19:47:18 -0500237#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
239#ifdef CONFIG_SYS_HUSH_PARSER
240#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200241#endif
242
243
244/*
245 * I2C
246 */
247#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
248#define CONFIG_HARD_I2C /* I2C with hardware support */
249#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_I2C_SPEED 102124 /* I2C speed and slave address */
251#define CONFIG_SYS_I2C_SLAVE 0x7F
252#define CONFIG_SYS_I2C_OFFSET 0x3000
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200253
Detlev Zundel3e79b582008-08-15 15:42:12 +0200254#define CONFIG_I2C_MULTI_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_I2C2_OFFSET 0x3100
Detlev Zundel3e79b582008-08-15 15:42:12 +0200256
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200257/* I2C RTC */
Sergei Poselenove18575d2008-05-07 15:10:49 +0200258#define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_I2C_RTC_ADDR 0x32 /* at address 0x32 */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200260
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200261/* I2C W83782G HW-Monitoring IC */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_I2C_W83782G_ADDR 0x28 /* W83782G address */
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200263
Sergei Poselenov2f7468a2008-05-27 10:36:07 +0200264/* I2C temp sensor */
265/* Socrates uses Maxim's DS75, which is compatible with LM75 */
266#define CONFIG_DTT_LM75 1
267#define CONFIG_DTT_SENSORS {4} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_DTT_MAX_TEMP 125
269#define CONFIG_SYS_DTT_LOW_TEMP -55
270#define CONFIG_SYS_DTT_HYSTERESIS 3
271#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
Sergei Poselenov2f7468a2008-05-27 10:36:07 +0200272
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200273/*
274 * General PCI
275 * Memory space is mapped 1-1.
276 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200278
Sergei Poselenov5e1882d2008-05-27 13:47:00 +0200279/* PCI is clocked by the external source at 33 MHz */
280#define CONFIG_PCI_CLK_FREQ 33000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
282#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
283#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
284#define CONFIG_SYS_PCI1_IO_BASE 0xE2000000
285#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
286#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200287
288#if defined(CONFIG_PCI)
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200289#define CONFIG_PCI_PNP /* do pci plug-and-play */
Sergei Poselenovd39e6852008-06-06 15:42:39 +0200290#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200291#endif /* CONFIG_PCI */
292
293
294#define CONFIG_NET_MULTI 1
295#define CONFIG_MII 1 /* MII PHY management */
296#define CONFIG_TSEC1 1
297#define CONFIG_TSEC1_NAME "TSEC0"
Sergei Poselenov2f845dc2008-05-08 17:46:23 +0200298#define CONFIG_TSEC3 1
299#define CONFIG_TSEC3_NAME "TSEC1"
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200300#undef CONFIG_MPC85XX_FEC
301
302#define TSEC1_PHY_ADDR 0
Sergei Poselenov2f845dc2008-05-08 17:46:23 +0200303#define TSEC3_PHY_ADDR 1
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200304
305#define TSEC1_PHYIDX 0
Sergei Poselenov2f845dc2008-05-08 17:46:23 +0200306#define TSEC3_PHYIDX 0
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200307#define TSEC1_FLAGS TSEC_GIGABIT
Sergei Poselenov2f845dc2008-05-08 17:46:23 +0200308#define TSEC3_FLAGS TSEC_GIGABIT
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200309
Sergei Poselenov2f845dc2008-05-08 17:46:23 +0200310/* Options are: TSEC[0,1] */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200311#define CONFIG_ETHPRIME "TSEC0"
312#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
313
Sergei Poselenove18575d2008-05-07 15:10:49 +0200314#define CONFIG_HAS_ETH0
315#define CONFIG_HAS_ETH1
316
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200317/*
318 * Environment
319 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200320#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200321#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200323#define CONFIG_ENV_SIZE 0x4000
324#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
325#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200326
327#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200329
330#define CONFIG_TIMESTAMP /* Print image info with ts */
331
332
333/*
334 * BOOTP options
335 */
336#define CONFIG_BOOTP_BOOTFILESIZE
337#define CONFIG_BOOTP_BOOTPATH
338#define CONFIG_BOOTP_GATEWAY
339#define CONFIG_BOOTP_HOSTNAME
340
341
342/*
343 * Command line configuration.
344 */
345#include <config_cmd_default.h>
346
Detlev Zundel47106ce2010-04-14 11:32:20 +0200347#define CONFIG_CMD_BMP
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200348#define CONFIG_CMD_DATE
349#define CONFIG_CMD_DHCP
Sergei Poselenov2f7468a2008-05-27 10:36:07 +0200350#define CONFIG_CMD_DTT
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200351#undef CONFIG_CMD_EEPROM
Detlev Zundel47106ce2010-04-14 11:32:20 +0200352#define CONFIG_CMD_EXT2 /* EXT2 Support */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200353#define CONFIG_CMD_I2C
Detlev Zundel3e79b582008-08-15 15:42:12 +0200354#define CONFIG_CMD_SDRAM
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200355#define CONFIG_CMD_MII
Detlev Zundel47106ce2010-04-14 11:32:20 +0200356#undef CONFIG_CMD_NFS
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200357#define CONFIG_CMD_PING
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200358#define CONFIG_CMD_SNTP
Sergei Poselenov791e1db2008-05-27 11:49:13 +0200359#define CONFIG_CMD_USB
Becky Bruce199e2622010-06-17 11:37:25 -0500360#define CONFIG_CMD_REGINFO
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200361
362#if defined(CONFIG_PCI)
363 #define CONFIG_CMD_PCI
364#endif
365
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200366#undef CONFIG_WATCHDOG /* watchdog disabled */
367
368/*
369 * Miscellaneous configurable options
370 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371#define CONFIG_SYS_LONGHELP /* undef to save memory */
372#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
373#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200374
375#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200377#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200379#endif
380
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buf Size */
382#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
383#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
384#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200385
386/*
387 * For booting Linux, the board info and command line data
388 * have to be in the first 8 MB of memory, since this is
389 * the maximum mapped by the Linux kernel during initialization.
390 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200392
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200393#if defined(CONFIG_CMD_KGDB)
394#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
395#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
396#endif
397
398
399#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
400
Detlev Zundel3e79b582008-08-15 15:42:12 +0200401#define CONFIG_BOOTDELAY 1 /* -1 disables auto-boot */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200402
403#define CONFIG_PREBOOT "echo;" \
Detlev Zundel3e79b582008-08-15 15:42:12 +0200404 "echo Welcome on the ABB Socrates Board;" \
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200405 "echo"
406
407#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
408
409#define CONFIG_EXTRA_ENV_SETTINGS \
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200410 "netdev=eth0\0" \
411 "consdev=ttyS0\0" \
Detlev Zundel3e79b582008-08-15 15:42:12 +0200412 "uboot_file=/home/tftp/syscon3/u-boot.bin\0" \
413 "bootfile=/home/tftp/syscon3/uImage\0" \
414 "fdt_file=/home/tftp/syscon3/socrates.dtb\0" \
415 "initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \
416 "uboot_addr=FFFA0000\0" \
417 "kernel_addr=FE000000\0" \
418 "fdt_addr=FE1E0000\0" \
419 "ramdisk_addr=FE200000\0" \
420 "fdt_addr_r=B00000\0" \
421 "kernel_addr_r=200000\0" \
422 "ramdisk_addr_r=400000\0" \
423 "rootpath=/opt/eldk/ppc_85xxDP\0" \
424 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200425 "nfsargs=setenv bootargs root=/dev/nfs rw " \
426 "nfsroot=$serverip:$rootpath\0" \
Detlev Zundel3e79b582008-08-15 15:42:12 +0200427 "addcons=setenv bootargs $bootargs " \
428 "console=$consdev,$baudrate\0" \
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200429 "addip=setenv bootargs $bootargs " \
430 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
431 ":$hostname:$netdev:off panic=1\0" \
Detlev Zundel3e79b582008-08-15 15:42:12 +0200432 "boot_nor=run ramargs addcons;" \
Sergei Poselenove18575d2008-05-07 15:10:49 +0200433 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
Sergei Poselenove18575d2008-05-07 15:10:49 +0200434 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
435 "tftp ${fdt_addr_r} ${fdt_file}; " \
436 "run nfsargs addip addcons;" \
437 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
Detlev Zundel3e79b582008-08-15 15:42:12 +0200438 "update_uboot=tftp 100000 ${uboot_file};" \
439 "protect off fffa0000 ffffffff;" \
440 "era fffa0000 ffffffff;" \
441 "cp.b 100000 fffa0000 ${filesize};" \
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200442 "setenv filesize;saveenv\0" \
Detlev Zundel3e79b582008-08-15 15:42:12 +0200443 "update_kernel=tftp 100000 ${bootfile};" \
444 "era fe000000 fe1dffff;" \
445 "cp.b 100000 fe000000 ${filesize};" \
446 "setenv filesize;saveenv\0" \
447 "update_fdt=tftp 100000 ${fdt_file};" \
448 "era fe1e0000 fe1fffff;" \
449 "cp.b 100000 fe1e0000 ${filesize};" \
450 "setenv filesize;saveenv\0" \
451 "update_initrd=tftp 100000 ${initrd_file};" \
452 "era fe200000 fe9fffff;" \
453 "cp.b 100000 fe200000 ${filesize};" \
454 "setenv filesize;saveenv\0" \
455 "clean_data=era fea00000 fff5ffff\0" \
456 "usbargs=setenv bootargs root=/dev/sda1 rw\0" \
457 "load_usb=usb start;" \
458 "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \
459 "boot_usb=run load_usb usbargs addcons;" \
460 "bootm ${kernel_addr_r} - ${fdt_addr};" \
461 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200462 ""
Detlev Zundel3e79b582008-08-15 15:42:12 +0200463#define CONFIG_BOOTCOMMAND "run boot_nor"
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200464
Sergei Poselenove18575d2008-05-07 15:10:49 +0200465/* pass open firmware flat tree */
466#define CONFIG_OF_LIBFDT 1
467#define CONFIG_OF_BOARD_SETUP 1
468
Sergei Poselenov791e1db2008-05-27 11:49:13 +0200469/* USB support */
470#define CONFIG_USB_OHCI_NEW 1
471#define CONFIG_PCI_OHCI 1
472#define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */
Yuri Tikhonove90fb6a2008-09-04 11:19:05 +0200473#define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200474#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
475#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
476#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
Sergei Poselenov791e1db2008-05-27 11:49:13 +0200477#define CONFIG_DOS_PARTITION 1
478#define CONFIG_USB_STORAGE 1
479
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200480#endif /* __CONFIG_H */