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Markus Klotzbücheraf646e82006-02-07 20:48:45 +01001/*
2 * (C) Copyright 2002
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * Configuation settings for the Zylonite board.
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37#define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */
Marek Vasut3ba8bf72010-09-09 09:50:39 +020038#define CONFIG_CPU_PXA320
Markus Klotzbücheraf646e82006-02-07 20:48:45 +010039#define CONFIG_ZYLONITE 1 /* Zylonite board */
Markus Klotzbücher57dc57f2006-02-19 16:03:49 +010040
Markus Klotzbücheraf646e82006-02-07 20:48:45 +010041/* #define CONFIG_LCD 1 */
42#ifdef CONFIG_LCD
43#define CONFIG_SHARP_LM8V31
44#endif
Jean-Christophe PLAGNIOL-VILLARDb03d92e2009-02-20 03:47:50 +010045#undef CONFIG_MMC
Markus Klotzbücheraf646e82006-02-07 20:48:45 +010046#define BOARD_LATE_INIT 1
47
48#undef CONFIG_SKIP_RELOCATE_UBOOT
49#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
50
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020051/* we will never enable dcache, because we have to setup MMU first */
52#define CONFIG_SYS_NO_DCACHE
53
Markus Klotzbücheraf646e82006-02-07 20:48:45 +010054/*
55 * Size of malloc() pool
56 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
58#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
Markus Klotzbücheraf646e82006-02-07 20:48:45 +010059
60/*
61 * Hardware drivers
62 */
Markus Klotzbücher6ece03f2006-02-10 17:08:26 +010063
64#undef TURN_ON_ETHERNET
65#ifdef TURN_ON_ETHERNET
Ben Warren7194ab82009-10-04 22:37:03 -070066# define CONFIG_SMC91111 1
Markus Klotzbücher6ece03f2006-02-10 17:08:26 +010067# define CONFIG_SMC91111_BASE 0x14000300
68# define CONFIG_SMC91111_EXT_PHY
69# define CONFIG_SMC_USE_32_BIT
Markus Klotzbücher8fb18572006-02-20 15:59:07 +010070# undef CONFIG_SMC_USE_IOFUNCS /* just for use with the kernel */
Markus Klotzbücher6ece03f2006-02-10 17:08:26 +010071#endif
Markus Klotzbücheraf646e82006-02-07 20:48:45 +010072
73/*
74 * select serial console configuration
75 */
Jean-Christophe PLAGNIOL-VILLARD379be582009-05-16 22:48:46 +020076#define CONFIG_PXA_SERIAL
Markus Klotzbücherb3c36e62006-02-09 13:19:25 +010077#define CONFIG_FFUART 1
Markus Klotzbücheraf646e82006-02-07 20:48:45 +010078
79/* allow to overwrite serial and ethaddr */
80#define CONFIG_ENV_OVERWRITE
81
82#define CONFIG_BAUDRATE 115200
83
Jon Loeligerdca3b3d2007-07-04 22:33:46 -050084
85/*
Jon Loeliger079a1362007-07-10 10:12:10 -050086 * BOOTP options
87 */
88#define CONFIG_BOOTP_BOOTFILESIZE
89#define CONFIG_BOOTP_BOOTPATH
90#define CONFIG_BOOTP_GATEWAY
91#define CONFIG_BOOTP_HOSTNAME
92
93
94/*
Jon Loeligerdca3b3d2007-07-04 22:33:46 -050095 * Command line configuration.
96 */
97#include <config_cmd_default.h>
98
Markus Klotzbücher6ece03f2006-02-10 17:08:26 +010099#ifdef TURN_ON_ETHERNET
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500100 #define CONFIG_CMD_PING
Markus Klotzbücher6ece03f2006-02-10 17:08:26 +0100101#else
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500102 #define CONFIG_CMD_SAVEENV
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500103 #define CONFIG_CMD_NAND
104
105 #undef CONFIG_CMD_NET
106 #undef CONFIG_CMD_FLASH
107 #undef CONFIG_CMD_IMLS
Markus Klotzbücher6ece03f2006-02-10 17:08:26 +0100108#endif
109
Markus Klotzbücheraf646e82006-02-07 20:48:45 +0100110
Markus Klotzbücher8fb18572006-02-20 15:59:07 +0100111#define CONFIG_BOOTDELAY -1
Markus Klotzbücheraf646e82006-02-07 20:48:45 +0100112#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
113#define CONFIG_NETMASK 255.255.0.0
114#define CONFIG_IPADDR 192.168.0.21
115#define CONFIG_SERVERIP 192.168.0.250
116#define CONFIG_BOOTCOMMAND "bootm 80000"
117#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
118#define CONFIG_CMDLINE_TAG
119#define CONFIG_TIMESTAMP
120
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500121#if defined(CONFIG_CMD_KGDB)
Markus Klotzbücheraf646e82006-02-07 20:48:45 +0100122#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
123#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
124#endif
125
126/*
127 * Miscellaneous configurable options
128 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_HUSH_PARSER 1
130#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Markus Klotzbücheraf646e82006-02-07 20:48:45 +0100131
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_LONGHELP /* undef to save memory */
133#ifdef CONFIG_SYS_HUSH_PARSER
134#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
Markus Klotzbücheraf646e82006-02-07 20:48:45 +0100135#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Markus Klotzbücheraf646e82006-02-07 20:48:45 +0100137#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
139#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
140#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
141#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
142#define CONFIG_SYS_DEVICE_NULLDEV 1
Markus Klotzbücheraf646e82006-02-07 20:48:45 +0100143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_MEMTEST_START 0x9c000000 /* memtest works on */
145#define CONFIG_SYS_MEMTEST_END 0x9c400000 /* 4 ... 8 MB in DRAM */
Markus Klotzbücheraf646e82006-02-07 20:48:45 +0100146
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
Markus Klotzbücheraf646e82006-02-07 20:48:45 +0100148
Micha Kalfon94a33122009-02-11 19:50:11 +0200149#define CONFIG_SYS_HZ 1000
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200150
151/* Monahans Core Frequency */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */
153#define CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO 1 /* valid values: 1, 2 */
Markus Klotzbücheraf646e82006-02-07 20:48:45 +0100154
155 /* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
Markus Klotzbücheraf646e82006-02-07 20:48:45 +0100157
Jean-Christophe PLAGNIOL-VILLARDb03d92e2009-02-20 03:47:50 +0100158#ifdef CONFIG_MMC
159#define CONFIG_PXA_MMC
160#define CONFIG_CMD_MMC
161#define CONFIG_SYS_MMC_BASE 0xF0000000
162#endif
Markus Klotzbücheraf646e82006-02-07 20:48:45 +0100163
164/*
165 * Stack sizes
166 *
167 * The stack sizes are set up in start.S using the settings below
168 */
169#define CONFIG_STACKSIZE (128*1024) /* regular stack */
170#ifdef CONFIG_USE_IRQ
171#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
172#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
173#endif
174
175/*
176 * Physical Memory Map
177 */
178#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
179#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
180#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
181#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
182#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
183#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
184#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
185#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
186#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
187
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_DRAM_BASE 0x80000000 /* at CS0 */
189#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB Ram */
Markus Klotzbücheraf646e82006-02-07 20:48:45 +0100190
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#undef CONFIG_SYS_SKIP_DRAM_SCRUB
Markus Klotzbücheraf646e82006-02-07 20:48:45 +0100192
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200193#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
194#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
Markus Klotzbücheraf646e82006-02-07 20:48:45 +0100195
196/*
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200197 * NAND Flash
Markus Klotzbücheraf646e82006-02-07 20:48:45 +0100198 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_NAND0_BASE 0x0
200#undef CONFIG_SYS_NAND1_BASE
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200201
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }
203#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200204
205/* nand timeout values */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_NAND_PROG_ERASE_TO 3000
207#define CONFIG_SYS_NAND_OTHER_TO 100
208#define CONFIG_SYS_NAND_SENDCMD_RETRY 3
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200209#undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */
210
211/* NAND Timing Parameters (in ns) */
212#define NAND_TIMING_tCH 10
213#define NAND_TIMING_tCS 0
214#define NAND_TIMING_tWH 20
215#define NAND_TIMING_tWP 40
216
217#define NAND_TIMING_tRH 20
218#define NAND_TIMING_tRP 40
219
220#define NAND_TIMING_tR 11123
221#define NAND_TIMING_tWHR 100
222#define NAND_TIMING_tAR 10
223
224/* NAND debugging */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_DFC_DEBUG1 /* usefull */
226#undef CONFIG_SYS_DFC_DEBUG2 /* noisy */
227#undef CONFIG_SYS_DFC_DEBUG3 /* extremly noisy */
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200228
229#define CONFIG_MTD_DEBUG
230#define CONFIG_MTD_DEBUG_VERBOSE 1
231
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_NO_FLASH 1
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200233
Jean-Christophe PLAGNIOL-VILLARD51bfee12008-09-10 22:47:58 +0200234#define CONFIG_ENV_IS_IN_NAND 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200235#define CONFIG_ENV_OFFSET 0x40000
236#define CONFIG_ENV_OFFSET_REDUND 0x44000
237#define CONFIG_ENV_SIZE 0x4000
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200238
Markus Klotzbücheraf646e82006-02-07 20:48:45 +0100239
240#endif /* __CONFIG_H */