blob: 19a288c582045e42ceaddf822371d0f4b27ac347 [file] [log] [blame]
wdenke2211742002-11-02 23:30:20 +00001/*
2 * (C) Copyright 2001
3 * Frank Gottschling, ELTEC Elektronik AG, fgottschling@eltec.de
4 *
5 * (C) Copyright 2001
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
8 * Configuation settings for the miniHiPerCam.
9 *
10 * -----------------------------------------------------------------
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenkc837dcb2004-01-20 23:12:12 +000021 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenke2211742002-11-02 23:30:20 +000022 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30/*
31 * board/config.h - configuration options, board specific
32 */
33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37/*
38 * High Level Configuration Options
39 * (easy to change)
40 */
41#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000042#define CONFIG_MHPC 1 /* on a miniHiPerCam */
43#define CONFIG_BOARD_EARLY_INIT_F 1 /* do special hardware init. */
44#define CONFIG_MISC_INIT_R 1
wdenke2211742002-11-02 23:30:20 +000045
46#define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED
47#undef CONFIG_8xx_CONS_SMC1
wdenkc837dcb2004-01-20 23:12:12 +000048#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
wdenke2211742002-11-02 23:30:20 +000049#undef CONFIG_8xx_CONS_NONE
50#define CONFIG_BAUDRATE 9600
51#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
52
wdenkc837dcb2004-01-20 23:12:12 +000053#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
wdenke2211742002-11-02 23:30:20 +000054
wdenkc837dcb2004-01-20 23:12:12 +000055#define CONFIG_ENV_OVERWRITE 1
56#define CONFIG_ETHADDR 00:00:5b:ee:de:ad
wdenke2211742002-11-02 23:30:20 +000057
wdenkc837dcb2004-01-20 23:12:12 +000058#undef CONFIG_BOOTARGS
wdenke2211742002-11-02 23:30:20 +000059#define CONFIG_BOOTCOMMAND \
60 "bootp;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010061 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
62 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenke2211742002-11-02 23:30:20 +000063 "bootm"
64
65#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenke2211742002-11-02 23:30:20 +000067
68#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenkc837dcb2004-01-20 23:12:12 +000069#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
wdenke2211742002-11-02 23:30:20 +000070
wdenkc837dcb2004-01-20 23:12:12 +000071#undef CONFIG_UCODE_PATCH
wdenke2211742002-11-02 23:30:20 +000072
73/* enable I2C and select the hardware/software driver */
wdenkc837dcb2004-01-20 23:12:12 +000074#undef CONFIG_HARD_I2C /* I2C with hardware support */
wdenke2211742002-11-02 23:30:20 +000075#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
76/*
77 * Software (bit-bang) I2C driver configuration
78 */
79#define PB_SCL 0x00000020 /* PB 26 */
80#define PB_SDA 0x00000010 /* PB 27 */
81
82#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
83#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
84#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
85#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
86#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
wdenkc837dcb2004-01-20 23:12:12 +000087 else immr->im_cpm.cp_pbdat &= ~PB_SDA
wdenke2211742002-11-02 23:30:20 +000088#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
wdenkc837dcb2004-01-20 23:12:12 +000089 else immr->im_cpm.cp_pbdat &= ~PB_SCL
wdenke2211742002-11-02 23:30:20 +000090#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
91
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CONFIG_SYS_I2C_SPEED 50000
93#define CONFIG_SYS_I2C_SLAVE 0xFE
94#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C04 */
95#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
wdenkc837dcb2004-01-20 23:12:12 +000096/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
98#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
99#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
wdenke2211742002-11-02 23:30:20 +0000100
wdenkc837dcb2004-01-20 23:12:12 +0000101#define LCD_VIDEO_ADDR (SDRAM_MAX_SIZE-SDRAM_RES_SIZE)
102#define LCD_VIDEO_SIZE SDRAM_RES_SIZE /* 2MB */
103#define LCD_VIDEO_COLS 640
104#define LCD_VIDEO_ROWS 480
105#define LCD_VIDEO_FG 255
106#define LCD_VIDEO_BG 0
wdenke2211742002-11-02 23:30:20 +0000107
wdenkc837dcb2004-01-20 23:12:12 +0000108#undef CONFIG_VIDEO /* test only ! s.a devices.c and 8xx */
109#define CONFIG_CFB_CONSOLE /* framebuffer console with std input */
wdenke2211742002-11-02 23:30:20 +0000110#define CONFIG_VIDEO_LOGO
111
wdenkc837dcb2004-01-20 23:12:12 +0000112#define VIDEO_KBD_INIT_FCT 0 /* no KBD dev on MHPC - use serial */
113#define VIDEO_TSTC_FCT serial_tstc
114#define VIDEO_GETC_FCT serial_getc
wdenke2211742002-11-02 23:30:20 +0000115
wdenkc837dcb2004-01-20 23:12:12 +0000116#define CONFIG_BR0_WORKAROUND 1
wdenke2211742002-11-02 23:30:20 +0000117
Jon Loeliger8353e132007-07-08 14:14:17 -0500118
119/*
120 * Command line configuration.
121 */
122#include <config_cmd_default.h>
123
124#define CONFIG_CMD_DATE
125#define CONFIG_CMD_EEPROM
126#define CONFIG_CMD_ELF
127#define CONFIG_CMD_I2C
128#define CONFIG_CMD_JFFS2
129#define CONFIG_CMD_REGINFO
130
wdenke2211742002-11-02 23:30:20 +0000131
Jon Loeliger7be044e2007-07-09 21:24:19 -0500132/*
133 * BOOTP options
134 */
135#define CONFIG_BOOTP_SUBNETMASK
136#define CONFIG_BOOTP_GATEWAY
137#define CONFIG_BOOTP_HOSTNAME
138#define CONFIG_BOOTP_BOOTPATH
139#define CONFIG_BOOTP_BOOTFILESIZE
140
wdenke2211742002-11-02 23:30:20 +0000141
wdenke2211742002-11-02 23:30:20 +0000142/*
143 * Miscellaneous configurable options
144 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_LONGHELP /* undef to save memory */
146#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger8353e132007-07-08 14:14:17 -0500147#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000149#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000151#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
153#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
154#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000155
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
157#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenke2211742002-11-02 23:30:20 +0000158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_LOAD_ADDR 0x300000 /* default load address */
wdenke2211742002-11-02 23:30:20 +0000160
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenke2211742002-11-02 23:30:20 +0000162
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenke2211742002-11-02 23:30:20 +0000164
165/*
166 * Low Level Configuration Settings
167 * (address mappings, register initial values, etc.)
168 * You should know what you are doing if you make changes here.
169 */
170
171/*-----------------------------------------------------------------------
172 * Physical memory map
173 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_IMMR 0xFFF00000 /* Internal Memory Mapped Register*/
wdenke2211742002-11-02 23:30:20 +0000175
176/*-----------------------------------------------------------------------
177 * Definitions for initial stack pointer and data area (in DPRAM)
178 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
180#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
181#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
182#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
183#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenke2211742002-11-02 23:30:20 +0000184
185/*-----------------------------------------------------------------------
186 * Start addresses for the final memory configuration
187 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenke2211742002-11-02 23:30:20 +0000189 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_SDRAM_BASE 0x00000000
191#define CONFIG_SYS_FLASH_BASE 0xfe000000
wdenke2211742002-11-02 23:30:20 +0000192
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */
194#undef CONFIG_SYS_MONITOR_BASE /* to run U-Boot from RAM */
195#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
196#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenke2211742002-11-02 23:30:20 +0000197
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200198/*
199 * JFFS2 partitions
200 *
201 */
202/* No command line, one static partition, whole device */
Stefan Roese68d7d652009-03-19 13:30:36 +0100203#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200204#define CONFIG_JFFS2_DEV "nor0"
205#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
206#define CONFIG_JFFS2_PART_OFFSET 0x00000000
207
208/* mtdparts command line support */
209/* Note: fake mtd_id used, no linux mtd map file */
210/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100211#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200212#define MTDIDS_DEFAULT "nor0=mhpc-0"
213#define MTDPARTS_DEFAULT "mtdparts=mhpc-0:-(jffs2)"
214*/
wdenke2211742002-11-02 23:30:20 +0000215
216/*
217 * For booting Linux, the board info and command line data
218 * have to be in the first 8 MB of memory, since this is
219 * the maximum mapped by the Linux kernel during initialization.
220 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map- for Linux */
wdenke2211742002-11-02 23:30:20 +0000222
223/*-----------------------------------------------------------------------
224 * FLASH organization
225 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
227#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
wdenke2211742002-11-02 23:30:20 +0000228
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
230#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200231#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN /* Offset of Environment */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200233#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment */
wdenke2211742002-11-02 23:30:20 +0000234
235/*-----------------------------------------------------------------------
236 * Cache Configuration
237 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger8353e132007-07-08 14:14:17 -0500239#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenke2211742002-11-02 23:30:20 +0000241#endif
242
243/*-----------------------------------------------------------------------
244 * SYPCR - System Protection Control 11-9
245 * SYPCR can only be written once after reset!
246 *-----------------------------------------------------------------------
247 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
248 */
249#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenke2211742002-11-02 23:30:20 +0000251 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
252#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk8bde7f72003-06-27 21:31:46 +0000254 SYPCR_SWP)
wdenke2211742002-11-02 23:30:20 +0000255#endif
256
257/*-----------------------------------------------------------------------
258 * SIUMCR - SIU Module Configuration 11-6
259 *-----------------------------------------------------------------------
260 * PCMCIA config., multi-function pin tri-state
261 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_SIUMCR (SIUMCR_SEME)
wdenke2211742002-11-02 23:30:20 +0000263
264/*-----------------------------------------------------------------------
265 * TBSCR - Time Base Status and Control 11-26
266 *-----------------------------------------------------------------------
267 * Clear Reference Interrupt Status, Timebase freezing enabled
268 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
wdenke2211742002-11-02 23:30:20 +0000270
271/*-----------------------------------------------------------------------
272 * PISCR - Periodic Interrupt Status and Control 11-31
273 *-----------------------------------------------------------------------
274 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
275 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
wdenke2211742002-11-02 23:30:20 +0000277
278/*-----------------------------------------------------------------------
279 * RTCSC - Real-Time Clock Status and Control Register 12-18
280 *-----------------------------------------------------------------------
281 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenke2211742002-11-02 23:30:20 +0000283
284/*-----------------------------------------------------------------------
285 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
286 *-----------------------------------------------------------------------
287 * Reset PLL lock status sticky bit, timer expired status bit and timer
288 * interrupt status bit - leave PLL multiplication factor unchanged !
289 */
290#define MPC8XX_SPEED 50000000L
wdenkc837dcb2004-01-20 23:12:12 +0000291#define MPC8XX_XIN 5000000L /* ref clk */
wdenke2211742002-11-02 23:30:20 +0000292#define MPC8XX_FACT (MPC8XX_SPEED/MPC8XX_XIN)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
wdenk8bde7f72003-06-27 21:31:46 +0000294 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenke2211742002-11-02 23:30:20 +0000295
296/*-----------------------------------------------------------------------
297 * SCCR - System Clock and reset Control Register 15-27
298 *-----------------------------------------------------------------------
299 * Set clock output, timebase and RTC source and divider,
300 * power management and some other internal clocks
301 */
302
303#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) /* SCCR_EBDF11 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_DFLCD001)
wdenke2211742002-11-02 23:30:20 +0000305
306
307/*-----------------------------------------------------------------------
308 * MAMR settings for SDRAM - 16-14
309 * => 0xC080200F
310 *-----------------------------------------------------------------------
311 * periodic timer for refresh
312 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_MAMR_PTA 0xC0
314#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_G0CLA_A11 | MAMR_TLFA_MSK)
wdenke2211742002-11-02 23:30:20 +0000315
316/*
317 * BR0 and OR0 (FLASH) used to re-map FLASH
318 */
319
320/* allow for max 8 MB of Flash */
321#define FLASH_BASE 0xFE000000 /* FLASH bank #0*/
322#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_REMAP_OR_AM 0xFF800000 /* OR addr mask */
324#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
wdenke2211742002-11-02 23:30:20 +0000325
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK) /* (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)*/
wdenke2211742002-11-02 23:30:20 +0000327
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
329#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
330#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V )
wdenke2211742002-11-02 23:30:20 +0000331
332/*
333 * BR1 and OR1 (SDRAM)
334 */
335#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
wdenkc837dcb2004-01-20 23:12:12 +0000336#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */
337#define SDRAM_RES_SIZE 0x00200000 /* 2 MB for framebuffer */
wdenke2211742002-11-02 23:30:20 +0000338
339/* SDRAM timing: drive GPL5 high on first cycle */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_OR_TIMING_SDRAM (OR_G5LS)
wdenke2211742002-11-02 23:30:20 +0000341
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_OR1_PRELIM ((~(SDRAM_MAX_SIZE)+1)| CONFIG_SYS_OR_TIMING_SDRAM )
343#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenke2211742002-11-02 23:30:20 +0000344
345/*
346 * BR2/OR2 - DIMM
347 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_OR2 (OR_ACS_DIV4)
349#define CONFIG_SYS_BR2 (BR_MS_UPMA)
wdenke2211742002-11-02 23:30:20 +0000350
351/*
352 * BR3/OR3 - DIMM
353 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_OR3 (OR_ACS_DIV4)
355#define CONFIG_SYS_BR3 (BR_MS_UPMA)
wdenke2211742002-11-02 23:30:20 +0000356
357/*
358 * BR4/OR4
359 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_OR4 0
361#define CONFIG_SYS_BR4 0
wdenke2211742002-11-02 23:30:20 +0000362
363/*
364 * BR5/OR5
365 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366#define CONFIG_SYS_OR5 0
367#define CONFIG_SYS_BR5 0
wdenke2211742002-11-02 23:30:20 +0000368
369/*
370 * BR6/OR6
371 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372#define CONFIG_SYS_OR6 0
373#define CONFIG_SYS_BR6 0
wdenke2211742002-11-02 23:30:20 +0000374
375/*
376 * BR7/OR7
377 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378#define CONFIG_SYS_OR7 0
379#define CONFIG_SYS_BR7 0
wdenke2211742002-11-02 23:30:20 +0000380
381
382/*-----------------------------------------------------------------------
383 * Debug Entry Mode
384 *-----------------------------------------------------------------------
385 *
386 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200387#define CONFIG_SYS_DER 0
wdenke2211742002-11-02 23:30:20 +0000388
389/*
390 * Internal Definitions
391 *
392 * Boot Flags
393 */
wdenkc837dcb2004-01-20 23:12:12 +0000394#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
wdenke2211742002-11-02 23:30:20 +0000395#define BOOTFLAG_WARM 0x02 /* Software reboot */
396
397#endif /* __CONFIG_H */