blob: f89fc570aa5407f527058a3a6d78e7ef7a9766fb [file] [log] [blame]
Wolfgang Denk52568c32009-05-16 10:47:46 +02001/*
2 * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
3 * (C) Copyright 2009, DAVE Srl <www.dave.eu>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * Aria board configuration file
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31#define CONFIG_ARIA 1
32/*
33 * Memory map for the ARIA board:
34 *
35 * 0x0000_0000-0x0FFF_FFFF DDR RAM (256 MB)
36 * 0x3000_0000-0x3001_FFFF On Chip SRAM (128 KB)
37 * 0x3010_0000-0x3011_FFFF On Board SRAM (128 KB) - CS6
38 * 0x3020_0000-0x3021_FFFF FPGA (128 KB) - CS2
39 * 0x8000_0000-0x803F_FFFF IMMR (4 MB)
40 * 0x8400_0000-0x82FF_FFFF PCI I/O space (16 MB)
41 * 0xA000_0000-0xAFFF_FFFF PCI memory space (256 MB)
42 * 0xB000_0000-0xBFFF_FFFF PCI memory mapped I/O space (256 MB)
43 * 0xFC00_0000-0xFFFF_FFFF NOR Boot FLASH (64 MB)
44 */
45
46/*
47 * High Level Configuration Options
48 */
49#define CONFIG_E300 1 /* E300 Family */
50#define CONFIG_MPC512X 1 /* MPC512X family */
51#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
52#define CONFIG_FSL_DIU_LOGO_BMP 1 /* Don't include FSL DIU binary bmp */
53
54/* video */
55#undef CONFIG_VIDEO
56
57#if defined(CONFIG_VIDEO)
58#define CONFIG_CFB_CONSOLE
59#define CONFIG_VGA_AS_SINGLE_DEVICE
60#endif
61
62/* CONFIG_PCI is defined at config time */
63
64#define CONFIG_SYS_MPC512X_CLKIN 33000000 /* in Hz */
65
66#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
67#define CONFIG_MISC_INIT_R
68
69#define CONFIG_SYS_IMMR 0x80000000
70#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100)
71
72#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
73#define CONFIG_SYS_MEMTEST_END 0x00400000
74
75/*
76 * DDR Setup - manually set all parameters as there's no SPD etc.
77 */
78#define CONFIG_SYS_DDR_SIZE 256 /* MB */
79#define CONFIG_SYS_DDR_BASE 0x00000000
80#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
81
82/* DDR Controller Configuration
83 *
84 * SYS_CFG:
85 * [31:31] MDDRC Soft Reset: Diabled
86 * [30:30] DRAM CKE pin: Enabled
87 * [29:29] DRAM CLK: Enabled
88 * [28:28] Command Mode: Enabled (For initialization only)
89 * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
90 * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
91 * [20:19] Read Test: DON'T USE
92 * [18:18] Self Refresh: Enabled
93 * [17:17] 16bit Mode: Disabled
94 * [16:13] Ready Delay: 2
95 * [12:12] Half DQS Delay: Disabled
96 * [11:11] Quarter DQS Delay: Disabled
97 * [10:08] Write Delay: 2
98 * [07:07] Early ODT: Disabled
99 * [06:06] On DIE Termination: Disabled
100 * [05:05] FIFO Overflow Clear: DON'T USE here
101 * [04:04] FIFO Underflow Clear: DON'T USE here
102 * [03:03] FIFO Overflow Pending: DON'T USE here
103 * [02:02] FIFO Underlfow Pending: DON'T USE here
104 * [01:01] FIFO Overlfow Enabled: Enabled
105 * [00:00] FIFO Underflow Enabled: Enabled
106 * TIME_CFG0
107 * [31:16] DRAM Refresh Time: 0 CSB clocks
108 * [15:8] DRAM Command Time: 0 CSB clocks
109 * [07:00] DRAM Precharge Time: 0 CSB clocks
110 * TIME_CFG1
111 * [31:26] DRAM tRFC:
112 * [25:21] DRAM tWR1:
113 * [20:17] DRAM tWRT1:
114 * [16:11] DRAM tDRR:
115 * [10:05] DRAM tRC:
116 * [04:00] DRAM tRAS:
117 * TIME_CFG2
118 * [31:28] DRAM tRCD:
119 * [27:23] DRAM tFAW:
120 * [22:19] DRAM tRTW1:
121 * [18:15] DRAM tCCD:
122 * [14:10] DRAM tRTP:
123 * [09:05] DRAM tRP:
124 * [04:00] DRAM tRPA
125 */
Wolfgang Denk25671c82009-06-14 20:58:48 +0200126#define CONFIG_SYS_MDDRC_SYS_CFG ( (1 << 31) | /* RST_B */ \
127 (1 << 30) | /* CKE */ \
128 (1 << 29) | /* CLK_ON */ \
Martha M Stan054197b2009-09-21 14:07:14 -0400129 (0 << 28) | /* CMD_MODE */ \
Wolfgang Denk25671c82009-06-14 20:58:48 +0200130 (4 << 25) | /* DRAM_ROW_SELECT */ \
131 (3 << 21) | /* DRAM_BANK_SELECT */ \
132 (0 << 18) | /* SELF_REF_EN */ \
133 (0 << 17) | /* 16BIT_MODE */ \
134 (2 << 13) | /* RDLY */ \
135 (0 << 12) | /* HALF_DQS_DLY */ \
136 (1 << 11) | /* QUART_DQS_DLY */ \
137 (2 << 8) | /* WDLY */ \
138 (0 << 7) | /* EARLY_ODT */ \
139 (1 << 6) | /* ON_DIE_TERMINATE */ \
140 (0 << 5) | /* FIFO_OV_CLEAR */ \
141 (0 << 4) | /* FIFO_UV_CLEAR */ \
142 (0 << 1) | /* FIFO_OV_EN */ \
143 (0 << 0) /* FIFO_UV_EN */ \
144 )
145
Martha M Stan054197b2009-09-21 14:07:14 -0400146#define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E
Wolfgang Denk25671c82009-06-14 20:58:48 +0200147#define CONFIG_SYS_MDDRC_TIME_CFG1 0x55D81189
148#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34790863
Wolfgang Denk52568c32009-05-16 10:47:46 +0200149
Martha M Stan054197b2009-09-21 14:07:14 -0400150#define CONFIG_SYS_DDRCMD_NOP 0x01380000
151#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
Wolfgang Denk25671c82009-06-14 20:58:48 +0200152#define CONFIG_SYS_MICRON_EMR ( (1 << 24) | /* CMD_REQ */ \
153 (0 << 22) | /* DRAM_CS */ \
154 (0 << 21) | /* DRAM_RAS */ \
155 (0 << 20) | /* DRAM_CAS */ \
156 (0 << 19) | /* DRAM_WEB */ \
157 (1 << 16) | /* DRAM_BS[2:0] */ \
158 (0 << 15) | /* */ \
159 (0 << 12) | /* A12->out */ \
160 (0 << 11) | /* A11->RDQS */ \
161 (0 << 10) | /* A10->DQS# */ \
162 (0 << 7) | /* OCD program */ \
163 (0 << 6) | /* Rtt1 */ \
164 (0 << 3) | /* posted CAS# */ \
165 (0 << 2) | /* Rtt0 */ \
166 (1 << 1) | /* ODS */ \
167 (0 << 0) /* DLL */ \
168 )
169#define CONFIG_SYS_MICRON_EMR2 0x01020000
170#define CONFIG_SYS_MICRON_EMR3 0x01030000
Martha M Stan054197b2009-09-21 14:07:14 -0400171#define CONFIG_SYS_DDRCMD_RFSH 0x01080000
Wolfgang Denk52568c32009-05-16 10:47:46 +0200172#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
Wolfgang Denk25671c82009-06-14 20:58:48 +0200173#define CONFIG_SYS_MICRON_EMR_OCD ( (1 << 24) | /* CMD_REQ */ \
174 (0 << 22) | /* DRAM_CS */ \
175 (0 << 21) | /* DRAM_RAS */ \
176 (0 << 20) | /* DRAM_CAS */ \
177 (0 << 19) | /* DRAM_WEB */ \
178 (1 << 16) | /* DRAM_BS[2:0] */ \
179 (0 << 15) | /* */ \
180 (0 << 12) | /* A12->out */ \
181 (0 << 11) | /* A11->RDQS */ \
182 (1 << 10) | /* A10->DQS# */ \
183 (7 << 7) | /* OCD program */ \
184 (0 << 6) | /* Rtt1 */ \
185 (0 << 3) | /* posted CAS# */ \
186 (1 << 2) | /* Rtt0 */ \
187 (0 << 1) | /* ODS (Output Drive Strength) */ \
188 (0 << 0) /* DLL */ \
189 )
190
191/*
192 * Backward compatible definitions,
193 * so we do not have to change cpu/mpc512x/fixed_sdram.c
194 */
Martha M Stan054197b2009-09-21 14:07:14 -0400195#define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2)
196#define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3)
197#define CONFIG_SYS_DDRCMD_EN_DLL (CONFIG_SYS_MICRON_EMR)
198#define CONFIG_SYS_DDRCMD_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD)
Wolfgang Denk52568c32009-05-16 10:47:46 +0200199
200/* DDR Priority Manager Configuration */
201#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
202#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
203#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
204#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
205#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
206#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
207#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
208#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
209#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
210#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
211#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
212#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
213#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
214#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
215#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
216#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
217#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
218#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
219#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
220#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
221#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
222#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
223#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
224
225/*
226 * NOR FLASH on the Local Bus
227 */
228#define CONFIG_SYS_FLASH_CFI /* use the CFI code */
229#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
230#define CONFIG_SYS_FLASH_BASE 0xF8000000 /* start of FLASH */
231#define CONFIG_SYS_FLASH_SIZE 0x08000000 /* max flash size */
232
233#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
234#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
235#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
236#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max sectors */
237
238#undef CONFIG_SYS_FLASH_CHECKSUM
239
Wolfgang Denka6d6d462009-06-14 20:58:51 +0200240/*
241 * NAND FLASH support
242 * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
243 */
Wolfgang Denk1f1f82f2009-06-14 20:58:52 +0200244#define CONFIG_CMD_NAND /* enable NAND support */
245#define CONFIG_JFFS2_NAND /* with JFFS2 on it */
246
Wolfgang Denka6d6d462009-06-14 20:58:51 +0200247
248#define CONFIG_NAND_MPC5121_NFC
249#define CONFIG_SYS_NAND_BASE 0x40000000
250
251#define CONFIG_SYS_MAX_NAND_DEVICE 1
252#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
253
Wolfgang Denka6d6d462009-06-14 20:58:51 +0200254/*
255 * Configuration parameters for MPC5121 NAND driver
256 */
257#define CONFIG_FSL_NFC_WIDTH 1
258#define CONFIG_FSL_NFC_WRITE_SIZE 2048
259#define CONFIG_FSL_NFC_SPARE_SIZE 64
260#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
261
Wolfgang Denk52568c32009-05-16 10:47:46 +0200262#define CONFIG_SYS_SRAM_BASE 0x30000000
263#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
264
Wolfgang Denk25671c82009-06-14 20:58:48 +0200265/* Make two SRAM regions contiguous */
266#define CONFIG_SYS_ARIA_SRAM_BASE (CONFIG_SYS_SRAM_BASE + \
267 CONFIG_SYS_SRAM_SIZE)
268#define CONFIG_SYS_ARIA_SRAM_SIZE 0x00100000 /* reserve 1MB-window */
Wolfgang Denk52568c32009-05-16 10:47:46 +0200269
270#define CONFIG_SYS_ARIA_FPGA_BASE (CONFIG_SYS_ARIA_SRAM_BASE + \
271 CONFIG_SYS_ARIA_SRAM_SIZE)
272#define CONFIG_SYS_ARIA_FPGA_SIZE 0x20000 /* 128 KB */
273
274#define CONFIG_SYS_CS0_CFG 0x05059150
275#define CONFIG_SYS_CS2_CFG ( (5 << 24) | \
276 (5 << 16) | \
277 (1 << 15) | \
278 (0 << 14) | \
279 (0 << 13) | \
280 (1 << 12) | \
281 (0 << 10) | \
282 (3 << 8) | /* 32 bit */ \
283 (0 << 7) | \
284 (1 << 6) | \
285 (1 << 4) | \
286 (0 << 3) | \
287 (0 << 2) | \
288 (0 << 1) | \
289 (0 << 0) \
290 )
291#define CONFIG_SYS_CS6_CFG 0x05059150
292
293/* Use alternative CS timing for CS0 and CS2 */
294#define CONFIG_SYS_CS_ALETIMING 0x00000005
295
296/* Use SRAM for initial stack */
297#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE
298#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE
299
300#define CONFIG_SYS_GBL_DATA_SIZE 0x100
301#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
302 CONFIG_SYS_GBL_DATA_SIZE)
303#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
304
305#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
Wolfgang Denka6d6d462009-06-14 20:58:51 +0200306#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
Wolfgang Denk52568c32009-05-16 10:47:46 +0200307
308#ifdef CONFIG_FSL_DIU_FB
309#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024)
310#else
311#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
312#endif
313
314/* FPGA */
315#define CONFIG_ARIA_FPGA 1
316
317/*
318 * Serial Port
319 */
320#define CONFIG_CONS_INDEX 1
321#undef CONFIG_SERIAL_SOFTWARE_FIFO
322
323/*
324 * Serial console configuration
325 */
326#define CONFIG_PSC_CONSOLE 3 /* console on PSC3 */
327#if CONFIG_PSC_CONSOLE != 3
328#error CONFIG_PSC_CONSOLE must be 3
329#endif
330
331#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
332#define CONFIG_SYS_BAUDRATE_TABLE \
333 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
334
335#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
336#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
337#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
338#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
339
340#define CONFIG_CMDLINE_EDITING 1 /* command line history */
341/* Use the HUSH parser */
342#define CONFIG_SYS_HUSH_PARSER
343#ifdef CONFIG_SYS_HUSH_PARSER
344#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
345#endif
346
347/*
348 * PCI
349 */
350#ifdef CONFIG_PCI
351
352#define CONFIG_SYS_PCI_MEM_BASE 0xA0000000
353#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
354#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
355#define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + \
356 CONFIG_SYS_PCI_MEM_SIZE)
357#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
358#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
359#define CONFIG_SYS_PCI_IO_BASE 0x00000000
360#define CONFIG_SYS_PCI_IO_PHYS 0x84000000
361#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */
362
363#define CONFIG_PCI_PNP /* do pci plug-and-play */
364
365#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
366
367#endif
368
369/* I2C */
370#define CONFIG_HARD_I2C /* I2C with hardware support */
371#undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */
372#define CONFIG_I2C_MULTI_BUS
Wolfgang Denk52568c32009-05-16 10:47:46 +0200373
374/* I2C speed and slave address */
375#define CONFIG_SYS_I2C_SPEED 100000
376#define CONFIG_SYS_I2C_SLAVE 0x7F
377#if 0
378#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
379#endif
380
381/*
382 * IIM - IC Identification Module
383 */
384#undef CONFIG_IIM
385
386/*
387 * EEPROM configuration for Atmel AT24C32A-10TQ-2.7:
388 * 16-bit addresses, 10ms write delay, 32-Byte Page Write Mode
389 */
390#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
391#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
392#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
393#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
394
395/*
396 * Ethernet configuration
397 */
398#define CONFIG_MPC512x_FEC 1
399#define CONFIG_NET_MULTI
400#define CONFIG_PHY_ADDR 0x17
401#define CONFIG_MII 1 /* MII PHY management */
402#define CONFIG_FEC_AN_TIMEOUT 1
403#define CONFIG_HAS_ETH0
404
405/*
406 * Environment
407 */
408#define CONFIG_ENV_IS_IN_FLASH 1
409/* This has to be a multiple of the flash sector size */
410#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
411 CONFIG_SYS_MONITOR_LEN)
412#define CONFIG_ENV_SIZE 0x2000
413#define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (256K) */
414
415/* Address and size of Redundant Environment Sector */
416#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
417 CONFIG_ENV_SECT_SIZE)
418#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
419
420#define CONFIG_LOADS_ECHO 1
421#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
422
423#include <config_cmd_default.h>
424
425#define CONFIG_CMD_ASKENV
426#define CONFIG_CMD_DHCP
427#define CONFIG_CMD_EEPROM
428#undef CONFIG_CMD_FUSE
429#define CONFIG_CMD_I2C
430#undef CONFIG_CMD_IDE
Wolfgang Denk1f1f82f2009-06-14 20:58:52 +0200431#define CONFIG_CMD_JFFS2
Wolfgang Denk52568c32009-05-16 10:47:46 +0200432#define CONFIG_CMD_MII
433#define CONFIG_CMD_NFS
434#define CONFIG_CMD_PING
435#define CONFIG_CMD_REGINFO
436
437#if defined(CONFIG_PCI)
438#define CONFIG_CMD_PCI
439#endif
440
Wolfgang Denk1f1f82f2009-06-14 20:58:52 +0200441#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2)
Wolfgang Denk52568c32009-05-16 10:47:46 +0200442#define CONFIG_DOS_PARTITION
443#define CONFIG_MAC_PARTITION
444#define CONFIG_ISO_PARTITION
445#endif /* defined(CONFIG_CMD_IDE) */
446
447/*
Wolfgang Denk1f1f82f2009-06-14 20:58:52 +0200448 * Dynamic MTD partition support
449 */
450#define CONFIG_CMD_MTDPARTS
451#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
452#define CONFIG_FLASH_CFI_MTD
453#define MTDIDS_DEFAULT "nor0=f8000000.flash,nand0=mpc5121.nand"
454
455/*
456 * NOR flash layout:
457 *
458 * F8000000 - FEAFFFFF 107 MiB User Data
459 * FEB00000 - FFAFFFFF 16 MiB Root File System
460 * FFB00000 - FFFEFFFF 4 MiB Linux Kernel
461 * FFF00000 - FFFBFFFF 768 KiB U-Boot (up to 512 KiB) and 2 x * env
462 * FFFC0000 - FFFFFFFF 256 KiB Device Tree
463 *
464 * NAND flash layout: one big partition
465 */
466#define MTDPARTS_DEFAULT "mtdparts=f8000000.flash:107m(user)," \
467 "16m(rootfs)," \
468 "4m(kernel)," \
469 "768k(u-boot)," \
470 "256k(dtb);" \
471 "mpc5121.nand:-(data)"
472
473/*
Wolfgang Denk52568c32009-05-16 10:47:46 +0200474 * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
475 * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE
476 * is set to 0xFFFF, watchdog timeouts after about 64s. For details
477 * refer to chapter 36 of the MPC5121e Reference Manual.
478 */
479/* #define CONFIG_WATCHDOG */ /* enable watchdog */
480#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
481
482 /*
483 * Miscellaneous configurable options
484 */
485#define CONFIG_SYS_LONGHELP /* undef to save memory */
486#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
487#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
488
489#ifdef CONFIG_CMD_KGDB
490# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
491#else
492# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
493#endif
494
495/* Print Buffer Size */
496#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
497 sizeof(CONFIG_SYS_PROMPT) + 16)
498/* max number of command args */
499#define CONFIG_SYS_MAXARGS 32
500/* Boot Argument Buffer Size */
501#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
502
503#define CONFIG_SYS_HZ 1000
504
505/*
506 * For booting Linux, the board info and command line data
507 * have to be in the first 8 MB of memory, since this is
508 * the maximum mapped by the Linux kernel during initialization.
509 */
510#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
511
512/* Cache Configuration */
513#define CONFIG_SYS_DCACHE_SIZE 32768
514#define CONFIG_SYS_CACHELINE_SIZE 32
515#ifdef CONFIG_CMD_KGDB
516#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of 32 */
517#endif
518
519#define CONFIG_SYS_HID0_INIT 0x000000000
520#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
521 HID0_ICE)
522#define CONFIG_SYS_HID2 HID2_HBE
523
524#define CONFIG_HIGH_BATS 1 /* High BATs supported */
525
526/*
527 * Internal Definitions
528 *
529 * Boot Flags
530 */
531#define BOOTFLAG_COLD 0x01
532#define BOOTFLAG_WARM 0x02
533
534#ifdef CONFIG_CMD_KGDB
535#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
536#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
537#endif
538
539/*
540 * Environment Configuration
541 */
542#define CONFIG_ENV_OVERWRITE
543#define CONFIG_TIMESTAMP
544
545#define CONFIG_HOSTNAME aria
546#define CONFIG_BOOTFILE aria/uImage
547#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx
548
549#define CONFIG_LOADADDR 400000 /* default load addr */
550
551#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
552#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
553
554#define CONFIG_BAUDRATE 115200
555
556#define CONFIG_PREBOOT "echo;" \
557 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
558 "echo"
559
560#define CONFIG_EXTRA_ENV_SETTINGS \
561 "u-boot_addr_r=200000\0" \
562 "kernel_addr_r=600000\0" \
563 "fdt_addr_r=880000\0" \
564 "ramdisk_addr_r=900000\0" \
565 "u-boot_addr=FFF00000\0" \
Wolfgang Denk1f1f82f2009-06-14 20:58:52 +0200566 "kernel_addr=FFB00000\0" \
567 "fdt_addr=FFFC0000\0" \
568 "ramdisk_addr=FEB00000\0" \
Wolfgang Denk52568c32009-05-16 10:47:46 +0200569 "ramdiskfile=aria/uRamdisk\0" \
570 "u-boot=aria/u-boot.bin\0" \
571 "fdtfile=aria/aria.dtb\0" \
572 "netdev=eth0\0" \
573 "consdev=ttyPSC0\0" \
574 "nfsargs=setenv bootargs root=/dev/nfs rw " \
575 "nfsroot=${serverip}:${rootpath}\0" \
576 "ramargs=setenv bootargs root=/dev/ram rw\0" \
577 "addip=setenv bootargs ${bootargs} " \
578 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
579 ":${hostname}:${netdev}:off panic=1\0" \
580 "addtty=setenv bootargs ${bootargs} " \
581 "console=${consdev},${baudrate}\0" \
582 "flash_nfs=run nfsargs addip addtty;" \
583 "bootm ${kernel_addr} - ${fdt_addr}\0" \
584 "flash_self=run ramargs addip addtty;" \
585 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
586 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
587 "tftp ${fdt_addr_r} ${fdtfile};" \
588 "run nfsargs addip addtty;" \
589 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
590 "net_self=tftp ${kernel_addr_r} ${bootfile};" \
591 "tftp ${ramdisk_addr_r} ${ramdiskfile};" \
592 "tftp ${fdt_addr_r} ${fdtfile};" \
593 "run ramargs addip addtty;" \
594 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
595 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
596 "update=protect off ${u-boot_addr} +${filesize};" \
597 "era ${u-boot_addr} +${filesize};" \
598 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
599 "upd=run load update\0" \
600 ""
601
602#define CONFIG_BOOTCOMMAND "run flash_self"
603
604#define CONFIG_OF_LIBFDT 1
605#define CONFIG_OF_BOARD_SETUP 1
606#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
607
608#define OF_CPU "PowerPC,5121@0"
609#define OF_SOC_COMPAT "fsl,mpc5121-immr"
610#define OF_TBCLK (bd->bi_busfreq / 4)
611#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
612
613/*-----------------------------------------------------------------------
614 * IDE/ATA stuff
615 *-----------------------------------------------------------------------
616 */
617
618#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
619#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
620#undef CONFIG_IDE_LED /* LED for IDE not supported */
621
622#define CONFIG_IDE_RESET /* reset for IDE supported */
623#define CONFIG_IDE_PREINIT
624
625#define CONFIG_SYS_IDE_MAXBUS 1 /* 1 IDE bus */
626#define CONFIG_SYS_IDE_MAXDEVICE 2 /* 1 drive per IDE bus */
627
628#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
629#define CONFIG_SYS_ATA_BASE_ADDR get_pata_base()
630
631/* Offset for data I/O RefMan MPC5121EE Table 28-10 */
632#define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0)
633
634/* Offset for normal register accesses */
635#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
636
637/* Offset for alternate registers RefMan MPC5121EE Table 28-23 */
638#define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8)
639
640/* Interval between registers */
641#define CONFIG_SYS_ATA_STRIDE 4
642
643#define ATA_BASE_ADDR get_pata_base()
644
645/*
646 * Control register bit definitions
647 */
648#define FSL_ATA_CTRL_FIFO_RST_B 0x80000000
649#define FSL_ATA_CTRL_ATA_RST_B 0x40000000
650#define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000
651#define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000
652#define FSL_ATA_CTRL_DMA_PENDING 0x08000000
653#define FSL_ATA_CTRL_DMA_ULTRA 0x04000000
654#define FSL_ATA_CTRL_DMA_WRITE 0x02000000
655#define FSL_ATA_CTRL_IORDY_EN 0x01000000
656
657#endif /* __CONFIG_H */