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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
gaurav ranaa2e225e2015-02-27 09:43:49 +05302/*
3 * Copyright 2015 Freescale Semiconductor, Inc.
gaurav ranaa2e225e2015-02-27 09:43:49 +05304 */
5
6#ifndef _FSL_SFP_SNVS_
7#define _FSL_SFP_SNVS_
8
9#include <common.h>
10#include <config.h>
11#include <asm/io.h>
12
13#ifdef CONFIG_SYS_FSL_SRK_LE
14#define srk_in32(a) in_le32(a)
15#else
16#define srk_in32(a) in_be32(a)
17#endif
18
19#ifdef CONFIG_SYS_FSL_SFP_LE
20#define sfp_in32(a) in_le32(a)
21#define sfp_out32(a, v) out_le32(a, v)
22#define sfp_in16(a) in_le16(a)
23#elif defined(CONFIG_SYS_FSL_SFP_BE)
24#define sfp_in32(a) in_be32(a)
25#define sfp_out32(a, v) out_be32(a, v)
26#define sfp_in16(a) in_be16(a)
27#else
28#error Neither CONFIG_SYS_FSL_SFP_LE nor CONFIG_SYS_FSL_SFP_BE is defined
29#endif
30
31/* Number of SRKH registers */
32#define NUM_SRKH_REGS 8
33
Saksham Jain38081902016-03-23 16:24:32 +053034#if defined(CONFIG_SYS_FSL_SFP_VER_3_2) || \
35 defined(CONFIG_SYS_FSL_SFP_VER_3_4)
gaurav ranaa2e225e2015-02-27 09:43:49 +053036struct ccsr_sfp_regs {
37 u32 ospr; /* 0x200 */
38 u32 ospr1; /* 0x204 */
39 u32 reserved1[4];
40 u32 fswpr; /* 0x218 FSL Section Write Protect */
41 u32 fsl_uid; /* 0x21c FSL UID 0 */
42 u32 fsl_uid_1; /* 0x220 FSL UID 0 */
43 u32 reserved2[12];
44 u32 srk_hash[8]; /* 0x254 Super Root Key Hash */
45 u32 oem_uid; /* 0x274 OEM UID 0*/
46 u32 oem_uid_1; /* 0x278 OEM UID 1*/
47 u32 oem_uid_2; /* 0x27c OEM UID 2*/
48 u32 oem_uid_3; /* 0x280 OEM UID 3*/
49 u32 oem_uid_4; /* 0x284 OEM UID 4*/
50 u32 reserved3[8];
51};
52#elif defined(CONFIG_SYS_FSL_SFP_VER_3_0)
53struct ccsr_sfp_regs {
54 u32 ospr; /* 0x200 */
55 u32 reserved0[14];
56 u32 srk_hash[NUM_SRKH_REGS]; /* 0x23c Super Root Key Hash */
57 u32 oem_uid; /* 0x9c OEM Unique ID */
58 u8 reserved2[0x04];
59 u32 ovpr; /* 0xA4 Intent To Secure */
60 u8 reserved4[0x08];
61 u32 fsl_uid; /* 0xB0 FSL Unique ID */
62 u8 reserved5[0x04];
63 u32 fsl_spfr0; /* Scratch Pad Fuse Register 0 */
64 u32 fsl_spfr1; /* Scratch Pad Fuse Register 1 */
65
66};
67#else
68struct ccsr_sfp_regs {
69 u8 reserved0[0x40];
70 u32 ospr; /* 0x40 OEM Security Policy Register */
71 u8 reserved2[0x38];
72 u32 srk_hash[8]; /* 0x7c Super Root Key Hash */
73 u32 oem_uid; /* 0x9c OEM Unique ID */
74 u8 reserved4[0x4];
75 u32 ovpr; /* 0xA4 OEM Validation Policy Register */
76 u8 reserved8[0x8];
77 u32 fsl_uid; /* 0xB0 FSL Unique ID */
78};
79#endif
Sumit Gargabd9c1b2016-09-07 12:17:34 -040080
gaurav ranaa2e225e2015-02-27 09:43:49 +053081#define ITS_MASK 0x00000004
82#define ITS_BIT 2
Sumit Gargabd9c1b2016-09-07 12:17:34 -040083
84#if defined(CONFIG_SYS_FSL_SFP_VER_3_4)
85#define OSPR_KEY_REVOC_SHIFT 9
86#define OSPR_KEY_REVOC_MASK 0x0000fe00
87#else
88#define OSPR_KEY_REVOC_SHIFT 13
89#define OSPR_KEY_REVOC_MASK 0x0000e000
90#endif /* CONFIG_SYS_FSL_SFP_VER_3_4 */
gaurav ranaa2e225e2015-02-27 09:43:49 +053091
92#endif