arch/arm/dts/meson-g12a.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
 */

#include "meson-g12-common.dtsi"
#include <dt-bindings/power/meson-g12a-power.h>

/ {
	compatible = "amlogic,g12a";

	cpus {
		#address-cells = <0x2>;
		#size-cells = <0x0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <&l2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x1>;
			enable-method = "psci";
			next-level-cache = <&l2>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x2>;
			enable-method = "psci";
			next-level-cache = <&l2>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x3>;
			enable-method = "psci";
			next-level-cache = <&l2>;
		};

		l2: l2-cache0 {
			compatible = "cache";
		};
	};

	cpu_opp_table: opp-table {
		compatible = "operating-points-v2";
		opp-shared;

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
			opp-microvolt = <731000>;
		};

		opp-250000000 {
			opp-hz = /bits/ 64 <250000000>;
			opp-microvolt = <731000>;
		};

		opp-500000000 {
			opp-hz = /bits/ 64 <500000000>;
			opp-microvolt = <731000>;
		};

		opp-667000000 {
			opp-hz = /bits/ 64 <666666666>;
			opp-microvolt = <731000>;
		};

		opp-1000000000 {
			opp-hz = /bits/ 64 <1000000000>;
			opp-microvolt = <731000>;
		};

		opp-1200000000 {
			opp-hz = /bits/ 64 <1200000000>;
			opp-microvolt = <731000>;
		};

		opp-1398000000 {
			opp-hz = /bits/ 64 <1398000000>;
			opp-microvolt = <761000>;
		};

		opp-1512000000 {
			opp-hz = /bits/ 64 <1512000000>;
			opp-microvolt = <791000>;
		};

		opp-1608000000 {
			opp-hz = /bits/ 64 <1608000000>;
			opp-microvolt = <831000>;
		};

		opp-1704000000 {
			opp-hz = /bits/ 64 <1704000000>;
			opp-microvolt = <861000>;
		};

		opp-1800000000 {
			opp-hz = /bits/ 64 <1800000000>;
			opp-microvolt = <981000>;
		};
	};
};

&ethmac {
	power-domains = <&pwrc PWRC_G12A_ETH_ID>;
};

&vpu {
	power-domains = <&pwrc PWRC_G12A_VPU_ID>;
};

&sd_emmc_a {
	amlogic,dram-access-quirk;
};