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wdenkd4ca31c2004-01-02 14:00:00 +00001/*
Wolfgang Denk23c5d252014-10-24 15:31:26 +02002 * (C) Copyright 2000-2014
wdenkd4ca31c2004-01-02 14:00:00 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkd4ca31c2004-01-02 14:00:00 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_MPC866 1 /* This is a MPC866 CPU */
21#define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */
Wolfgang Denk23c5d252014-10-24 15:31:26 +020022#define CONFIG_DISPLAY_BOARDINFO
wdenkd4ca31c2004-01-02 14:00:00 +000023
Wolfgang Denk2ae18242010-10-06 09:05:45 +020024#define CONFIG_SYS_TEXT_BASE 0x40000000
25
wdenk66ca92a2004-09-28 17:59:53 +000026#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020027#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
28#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
wdenk66ca92a2004-09-28 17:59:53 +000029#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */
wdenkc178d3d2004-01-24 20:25:54 +000030 /* (it will be used if there is no */
31 /* 'cpuclk' variable with valid value) */
wdenkd4ca31c2004-01-02 14:00:00 +000032
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020033#undef CONFIG_SYS_MEASURE_CPUCLK /* Measure real cpu clock */
wdenk75d1ea72004-01-31 20:06:54 +000034 /* (function measure_gclk() */
35 /* will be called) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020036#ifdef CONFIG_SYS_MEASURE_CPUCLK
37#define CONFIG_SYS_8XX_XIN 10000000 /* measure_gclk() needs this */
wdenk75d1ea72004-01-31 20:06:54 +000038#endif
39
wdenkc178d3d2004-01-24 20:25:54 +000040#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denk3cb7a482009-07-28 22:13:52 +020041#define CONFIG_SYS_SMC_RXBUFLEN 128
42#define CONFIG_SYS_MAXIDLE 10
wdenkd4ca31c2004-01-02 14:00:00 +000043#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
44
wdenkc178d3d2004-01-24 20:25:54 +000045#define CONFIG_BOOTCOUNT_LIMIT
wdenkd4ca31c2004-01-02 14:00:00 +000046
47#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
48
49#define CONFIG_BOARD_TYPES 1 /* support board types */
50
wdenkc178d3d2004-01-24 20:25:54 +000051#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010052 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenkd4ca31c2004-01-02 14:00:00 +000053 "echo"
54
55#undef CONFIG_BOOTARGS
56
wdenkc178d3d2004-01-24 20:25:54 +000057#define CONFIG_EXTRA_ENV_SETTINGS \
wdenkd4ca31c2004-01-02 14:00:00 +000058 "netdev=eth0\0" \
59 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010060 "nfsroot=${serverip}:${rootpath}\0" \
wdenkd4ca31c2004-01-02 14:00:00 +000061 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010062 "addip=setenv bootargs ${bootargs} " \
63 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
64 ":${hostname}:${netdev}:off panic=1\0" \
wdenkd4ca31c2004-01-02 14:00:00 +000065 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010066 "bootm ${kernel_addr}\0" \
wdenkd4ca31c2004-01-02 14:00:00 +000067 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010068 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
69 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenkd4ca31c2004-01-02 14:00:00 +000070 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020071 "hostname=TQM866M\0" \
72 "bootfile=TQM866M/uImage\0" \
Martin Krause9ef57bb2007-09-26 17:55:55 +020073 "fdt_addr=400C0000\0" \
74 "kernel_addr=40100000\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020075 "ramdisk_addr=40280000\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020076 "u-boot=TQM866M/u-image.bin\0" \
Martin Krause9ef57bb2007-09-26 17:55:55 +020077 "load=tftp 200000 ${u-boot}\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020078 "update=prot off 40000000 +${filesize};" \
79 "era 40000000 +${filesize};" \
Martin Krause9ef57bb2007-09-26 17:55:55 +020080 "cp.b 200000 40000000 ${filesize};" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020081 "sete filesize;save\0" \
wdenkd4ca31c2004-01-02 14:00:00 +000082 ""
83#define CONFIG_BOOTCOMMAND "run flash_self"
84
85#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkd4ca31c2004-01-02 14:00:00 +000087
88#undef CONFIG_WATCHDOG /* watchdog disabled */
89
wdenkc178d3d2004-01-24 20:25:54 +000090#define CONFIG_STATUS_LED 1 /* Status LED enabled */
wdenkd4ca31c2004-01-02 14:00:00 +000091
92#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
93
94/* enable I2C and select the hardware/software driver */
Heiko Schocherea818db2013-01-29 08:53:15 +010095#define CONFIG_SYS_I2C
96#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
97#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
98#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
wdenkd4ca31c2004-01-02 14:00:00 +000099
wdenkd4ca31c2004-01-02 14:00:00 +0000100/*
101 * Software (bit-bang) I2C driver configuration
102 */
103#define PB_SCL 0x00000020 /* PB 26 */
104#define PB_SDA 0x00000010 /* PB 27 */
105
106#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
107#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
108#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
109#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
110#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
wdenkc178d3d2004-01-24 20:25:54 +0000111 else immr->im_cpm.cp_pbdat &= ~PB_SDA
wdenkd4ca31c2004-01-02 14:00:00 +0000112#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
wdenkc178d3d2004-01-24 20:25:54 +0000113 else immr->im_cpm.cp_pbdat &= ~PB_SCL
wdenkd4ca31c2004-01-02 14:00:00 +0000114#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
wdenkd4ca31c2004-01-02 14:00:00 +0000115
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */
117#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
118#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
119#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenkd4ca31c2004-01-02 14:00:00 +0000120
Jon Loeliger37d4bb72007-07-09 21:38:02 -0500121/*
122 * BOOTP options
123 */
124#define CONFIG_BOOTP_SUBNETMASK
125#define CONFIG_BOOTP_GATEWAY
126#define CONFIG_BOOTP_HOSTNAME
127#define CONFIG_BOOTP_BOOTPATH
128#define CONFIG_BOOTP_BOOTFILESIZE
129
wdenkd4ca31c2004-01-02 14:00:00 +0000130
131#define CONFIG_MAC_PARTITION
132#define CONFIG_DOS_PARTITION
133
wdenka6cccae2004-02-06 21:48:22 +0000134#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
135
136#define CONFIG_TIMESTAMP /* but print image timestmps */
wdenkd4ca31c2004-01-02 14:00:00 +0000137
wdenkd4ca31c2004-01-02 14:00:00 +0000138
Jon Loeliger26946902007-07-04 22:30:50 -0500139/*
140 * Command line configuration.
141 */
Jon Loeliger26946902007-07-04 22:30:50 -0500142#define CONFIG_CMD_ASKENV
143#define CONFIG_CMD_DHCP
144#define CONFIG_CMD_EEPROM
Wolfgang Denk9a63b7f2009-02-21 21:51:21 +0100145#define CONFIG_CMD_EXT2
Jon Loeliger26946902007-07-04 22:30:50 -0500146#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200147#define CONFIG_CMD_JFFS2
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200148#define CONFIG_CMD_SNTP
149
150
151#define CONFIG_NETCONSOLE
Jon Loeliger26946902007-07-04 22:30:50 -0500152
wdenkd4ca31c2004-01-02 14:00:00 +0000153
154/*
155 * Miscellaneous configurable options
156 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenkd4ca31c2004-01-02 14:00:00 +0000158
Wolfgang Denk2751a952006-10-28 02:29:14 +0200159#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
wdenkd4ca31c2004-01-02 14:00:00 +0000161
Jon Loeliger26946902007-07-04 22:30:50 -0500162#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkd4ca31c2004-01-02 14:00:00 +0000164#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkd4ca31c2004-01-02 14:00:00 +0000166#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
168#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
169#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkd4ca31c2004-01-02 14:00:00 +0000170
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
172#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkd4ca31c2004-01-02 14:00:00 +0000173
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkd4ca31c2004-01-02 14:00:00 +0000175
wdenkd4ca31c2004-01-02 14:00:00 +0000176/*
177 * Low Level Configuration Settings
178 * (address mappings, register initial values, etc.)
179 * You should know what you are doing if you make changes here.
180 */
181/*-----------------------------------------------------------------------
182 * Internal Memory Mapped Register
183 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_IMMR 0xFFF00000
wdenkd4ca31c2004-01-02 14:00:00 +0000185
186/*-----------------------------------------------------------------------
187 * Definitions for initial stack pointer and data area (in DPRAM)
188 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200190#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200191#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkd4ca31c2004-01-02 14:00:00 +0000193
194/*-----------------------------------------------------------------------
195 * Start addresses for the final memory configuration
196 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkd4ca31c2004-01-02 14:00:00 +0000198 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_SDRAM_BASE 0x00000000
200#define CONFIG_SYS_FLASH_BASE 0x40000000
201#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
202#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
203#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
wdenkd4ca31c2004-01-02 14:00:00 +0000204
205/*
206 * For booting Linux, the board info and command line data
207 * have to be in the first 8 MB of memory, since this is
208 * the maximum mapped by the Linux kernel during initialization.
209 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkd4ca31c2004-01-02 14:00:00 +0000211
212/*-----------------------------------------------------------------------
213 * FLASH organization
214 */
Martin Krausee318d9e2007-09-27 11:10:08 +0200215/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200217#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
219#define CONFIG_SYS_FLASH_EMPTY_INFO
220#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
221#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
222#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkd4ca31c2004-01-02 14:00:00 +0000223
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200224#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200225#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
226#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
227#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
wdenkd4ca31c2004-01-02 14:00:00 +0000228
229/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200230#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
231#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenkd4ca31c2004-01-02 14:00:00 +0000232
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200234
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200235#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
236
wdenkd4ca31c2004-01-02 14:00:00 +0000237/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200238 * Dynamic MTD partition support
239 */
Stefan Roese68d7d652009-03-19 13:30:36 +0100240#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200241#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
242#define CONFIG_FLASH_CFI_MTD
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200243#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
244
245#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
246 "128k(dtb)," \
247 "1920k(kernel)," \
248 "5632(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200249 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200250
251/*-----------------------------------------------------------------------
wdenkd4ca31c2004-01-02 14:00:00 +0000252 * Hardware Information Block
253 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
255#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
256#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenkd4ca31c2004-01-02 14:00:00 +0000257
258/*-----------------------------------------------------------------------
259 * Cache Configuration
260 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500262#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkd4ca31c2004-01-02 14:00:00 +0000264#endif
265
266/*-----------------------------------------------------------------------
267 * SYPCR - System Protection Control 11-9
268 * SYPCR can only be written once after reset!
269 *-----------------------------------------------------------------------
270 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
271 */
272#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkd4ca31c2004-01-02 14:00:00 +0000274 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
275#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenkd4ca31c2004-01-02 14:00:00 +0000277#endif
278
279/*-----------------------------------------------------------------------
280 * SIUMCR - SIU Module Configuration 11-6
281 *-----------------------------------------------------------------------
282 * PCMCIA config., multi-function pin tri-state
283 */
wdenkc178d3d2004-01-24 20:25:54 +0000284#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkd4ca31c2004-01-02 14:00:00 +0000286#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkd4ca31c2004-01-02 14:00:00 +0000288#endif /* CONFIG_CAN_DRIVER */
289
290/*-----------------------------------------------------------------------
291 * TBSCR - Time Base Status and Control 11-26
292 *-----------------------------------------------------------------------
293 * Clear Reference Interrupt Status, Timebase freezing enabled
294 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkd4ca31c2004-01-02 14:00:00 +0000296
297/*-----------------------------------------------------------------------
wdenkd4ca31c2004-01-02 14:00:00 +0000298 * PISCR - Periodic Interrupt Status and Control 11-31
299 *-----------------------------------------------------------------------
300 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
301 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkd4ca31c2004-01-02 14:00:00 +0000303
304/*-----------------------------------------------------------------------
wdenkd4ca31c2004-01-02 14:00:00 +0000305 * SCCR - System Clock and reset Control Register 15-27
306 *-----------------------------------------------------------------------
307 * Set clock output, timebase and RTC source and divider,
308 * power management and some other internal clocks
309 */
310#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkd4ca31c2004-01-02 14:00:00 +0000312 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
313 SCCR_DFALCD00)
wdenkd4ca31c2004-01-02 14:00:00 +0000314
315/*-----------------------------------------------------------------------
316 * PCMCIA stuff
317 *-----------------------------------------------------------------------
318 *
319 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
321#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
322#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
323#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
324#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
325#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
326#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
327#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenkd4ca31c2004-01-02 14:00:00 +0000328
329/*-----------------------------------------------------------------------
330 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
331 *-----------------------------------------------------------------------
332 */
333
Pavel Herrmann8d1165e11a2012-10-09 07:01:56 +0000334#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
wdenkc178d3d2004-01-24 20:25:54 +0000335#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
wdenkd4ca31c2004-01-02 14:00:00 +0000336
wdenkc178d3d2004-01-24 20:25:54 +0000337#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
338#undef CONFIG_IDE_LED /* LED for ide not supported */
wdenkd4ca31c2004-01-02 14:00:00 +0000339#undef CONFIG_IDE_RESET /* reset for ide not supported */
340
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
342#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenkd4ca31c2004-01-02 14:00:00 +0000343
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkd4ca31c2004-01-02 14:00:00 +0000345
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenkd4ca31c2004-01-02 14:00:00 +0000347
348/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkd4ca31c2004-01-02 14:00:00 +0000350
351/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkd4ca31c2004-01-02 14:00:00 +0000353
354/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkd4ca31c2004-01-02 14:00:00 +0000356
357/*-----------------------------------------------------------------------
358 *
359 *-----------------------------------------------------------------------
360 *
361 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_DER 0
wdenkd4ca31c2004-01-02 14:00:00 +0000363
364/*
365 * Init Memory Controller:
366 *
367 * BR0/1 and OR0/1 (FLASH)
368 */
369
370#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
371#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
372
373/* used to re-map FLASH both when starting from SRAM or FLASH:
374 * restrict access enough to keep SRAM working (if any)
375 * but not too much to meddle with FLASH accesses
376 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
378#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenkd4ca31c2004-01-02 14:00:00 +0000379
380/*
wdenkc178d3d2004-01-24 20:25:54 +0000381 * FLASH timing: Default value of OR0 after reset
wdenkd4ca31c2004-01-02 14:00:00 +0000382 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
wdenkc178d3d2004-01-24 20:25:54 +0000384 OR_SCY_15_CLK | OR_TRLX)
wdenkd4ca31c2004-01-02 14:00:00 +0000385
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
387#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
388#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenkd4ca31c2004-01-02 14:00:00 +0000389
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
391#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
392#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenkd4ca31c2004-01-02 14:00:00 +0000393
394/*
395 * BR2/3 and OR2/3 (SDRAM)
396 *
397 */
398#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
399#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
wdenkc178d3d2004-01-24 20:25:54 +0000400#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
wdenkd4ca31c2004-01-02 14:00:00 +0000401
402/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenkd4ca31c2004-01-02 14:00:00 +0000404
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200405#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
406#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkd4ca31c2004-01-02 14:00:00 +0000407
wdenkc178d3d2004-01-24 20:25:54 +0000408#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200409#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
410#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkd4ca31c2004-01-02 14:00:00 +0000411#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200412#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
413#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
414#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
415#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenkd4ca31c2004-01-02 14:00:00 +0000416 BR_PS_8 | BR_MS_UPMB | BR_V )
417#endif /* CONFIG_CAN_DRIVER */
418
419/*
wdenkc178d3d2004-01-24 20:25:54 +0000420 * 4096 Rows from SDRAM example configuration
421 * 1000 factor s -> ms
422 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
423 * 4 Number of refresh cycles per period
424 * 64 Refresh cycle in ms per number of rows
wdenkd4ca31c2004-01-02 14:00:00 +0000425 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200426#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
wdenkc178d3d2004-01-24 20:25:54 +0000427
428/*
Martin Kraused43e4892007-09-27 14:54:36 +0200429 * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
430 *
431 * CPUclock(MHz) * 31.2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200432 * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0
Martin Kraused43e4892007-09-27 14:54:36 +0200433 * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
434 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435 * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us
436 * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us
437 * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us
438 * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us
Martin Kraused43e4892007-09-27 14:54:36 +0200439 *
440 * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
441 * be met also in the default configuration, i.e. if environment variable
442 * 'cpuclk' is not set.
wdenkc178d3d2004-01-24 20:25:54 +0000443 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200444#define CONFIG_SYS_MAMR_PTA 97
wdenkd4ca31c2004-01-02 14:00:00 +0000445
446/*
Martin Kraused43e4892007-09-27 14:54:36 +0200447 * Memory Periodic Timer Prescaler Register (MPTPR) values.
wdenkd4ca31c2004-01-02 14:00:00 +0000448 */
Martin Kraused43e4892007-09-27 14:54:36 +0200449/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200450#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16
Martin Kraused43e4892007-09-27 14:54:36 +0200451/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200452#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8
wdenkd4ca31c2004-01-02 14:00:00 +0000453
454/*
455 * MAMR settings for SDRAM
456 */
457
458/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200459#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkd4ca31c2004-01-02 14:00:00 +0000460 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
461 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
462/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200463#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkd4ca31c2004-01-02 14:00:00 +0000464 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
465 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
wdenkc178d3d2004-01-24 20:25:54 +0000466/* 10 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200467#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkc178d3d2004-01-24 20:25:54 +0000468 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
469 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
wdenkd4ca31c2004-01-02 14:00:00 +0000470
wdenkd4ca31c2004-01-02 14:00:00 +0000471#define CONFIG_SCC1_ENET
472#define CONFIG_FEC_ENET
Heiko Schocher48690d82010-07-20 17:45:02 +0200473#define CONFIG_ETHPRIME "SCC"
wdenkd4ca31c2004-01-02 14:00:00 +0000474
Heiko Schocher7026ead2010-02-09 15:50:27 +0100475/* pass open firmware flat tree */
476#define CONFIG_OF_LIBFDT 1
477#define CONFIG_OF_BOARD_SETUP 1
478#define CONFIG_HWCONFIG 1
479
wdenkd4ca31c2004-01-02 14:00:00 +0000480#endif /* __CONFIG_H */