blob: c979049b5ba40ecf876c0a67d4350a33bf31449f [file] [log] [blame]
Simon Glass7b7ad5c2016-01-21 19:45:05 -07001/*
2 * Copyright (c) 2015 Google, Inc
3 * Copyright 2014 Rockchip Inc.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <clk.h>
10#include <display.h>
11#include <dm.h>
12#include <edid.h>
13#include <regmap.h>
14#include <syscon.h>
15#include <video.h>
16#include <asm/gpio.h>
17#include <asm/hardware.h>
18#include <asm/io.h>
19#include <asm/arch/clock.h>
Simon Glass7b7ad5c2016-01-21 19:45:05 -070020#include <asm/arch/edp_rk3288.h>
Simon Glass7b7ad5c2016-01-21 19:45:05 -070021#include <asm/arch/vop_rk3288.h>
22#include <dm/device-internal.h>
23#include <dm/uclass-internal.h>
Simon Glass7b7ad5c2016-01-21 19:45:05 -070024#include <power/regulator.h>
Philipp Tomsichd46d4042017-05-31 17:59:30 +020025#include "rk_vop.h"
Simon Glass7b7ad5c2016-01-21 19:45:05 -070026
27DECLARE_GLOBAL_DATA_PTR;
28
Philipp Tomsichd46d4042017-05-31 17:59:30 +020029enum vop_pol {
30 HSYNC_POSITIVE = 0,
31 VSYNC_POSITIVE = 1,
32 DEN_NEGATIVE = 2,
33 DCLK_INVERT = 3
Simon Glass7b7ad5c2016-01-21 19:45:05 -070034};
35
Philipp Tomsichd46d4042017-05-31 17:59:30 +020036static void rkvop_enable(struct rk3288_vop *regs, ulong fbbase,
37 int fb_bits_per_pixel,
38 const struct display_timing *edid)
Simon Glass7b7ad5c2016-01-21 19:45:05 -070039{
40 u32 lb_mode;
41 u32 rgb_mode;
42 u32 hactive = edid->hactive.typ;
43 u32 vactive = edid->vactive.typ;
44
45 writel(V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1),
46 &regs->win0_act_info);
47
48 writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) |
49 V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ),
50 &regs->win0_dsp_st);
51
52 writel(V_DSP_WIDTH(hactive - 1) |
53 V_DSP_HEIGHT(vactive - 1),
54 &regs->win0_dsp_info);
55
56 clrsetbits_le32(&regs->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR,
57 V_WIN0_KEY_EN(0) | V_WIN0_KEY_COLOR(0));
58
59 switch (fb_bits_per_pixel) {
60 case 16:
61 rgb_mode = RGB565;
62 writel(V_RGB565_VIRWIDTH(hactive), &regs->win0_vir);
63 break;
64 case 24:
65 rgb_mode = RGB888;
66 writel(V_RGB888_VIRWIDTH(hactive), &regs->win0_vir);
67 break;
68 case 32:
69 default:
70 rgb_mode = ARGB8888;
71 writel(V_ARGB888_VIRWIDTH(hactive), &regs->win0_vir);
72 break;
73 }
74
75 if (hactive > 2560)
76 lb_mode = LB_RGB_3840X2;
77 else if (hactive > 1920)
78 lb_mode = LB_RGB_2560X4;
79 else if (hactive > 1280)
80 lb_mode = LB_RGB_1920X5;
81 else
82 lb_mode = LB_RGB_1280X8;
83
84 clrsetbits_le32(&regs->win0_ctrl0,
85 M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN,
86 V_WIN0_LB_MODE(lb_mode) | V_WIN0_DATA_FMT(rgb_mode) |
87 V_WIN0_EN(1));
88
89 writel(fbbase, &regs->win0_yrgb_mst);
90 writel(0x01, &regs->reg_cfg_done); /* enable reg config */
91}
92
Philipp Tomsichd46d4042017-05-31 17:59:30 +020093static void rkvop_set_pin_polarity(struct udevice *dev,
94 enum vop_modes mode, u32 polarity)
Simon Glass7b7ad5c2016-01-21 19:45:05 -070095{
Philipp Tomsichd46d4042017-05-31 17:59:30 +020096 struct rkvop_driverdata *ops =
97 (struct rkvop_driverdata *)dev_get_driver_data(dev);
98
99 if (ops->set_pin_polarity)
100 ops->set_pin_polarity(dev, mode, polarity);
101}
102
103static void rkvop_enable_output(struct udevice *dev, enum vop_modes mode)
104{
105 struct rk_vop_priv *priv = dev_get_priv(dev);
106 struct rk3288_vop *regs = priv->regs;
107
Simon Glass6b5a09a2017-05-31 17:57:29 -0600108 /* remove from standby */
109 clrbits_le32(&regs->sys_ctrl, V_STANDBY_EN(1));
110
Philipp Tomsichd46d4042017-05-31 17:59:30 +0200111 switch (mode) {
112 case VOP_MODE_HDMI:
113 clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
114 V_HDMI_OUT_EN(1));
115 break;
116
117 case VOP_MODE_EDP:
118 clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
119 V_EDP_OUT_EN(1));
120 break;
121
122 case VOP_MODE_LVDS:
123 clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
124 V_RGB_OUT_EN(1));
125 break;
126
127 case VOP_MODE_MIPI:
128 clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
129 V_MIPI_OUT_EN(1));
130 break;
131
132 default:
133 debug("%s: unsupported output mode %x\n", __func__, mode);
134 }
135}
136
137static void rkvop_mode_set(struct udevice *dev,
138 const struct display_timing *edid,
139 enum vop_modes mode)
140{
141 struct rk_vop_priv *priv = dev_get_priv(dev);
142 struct rk3288_vop *regs = priv->regs;
143 struct rkvop_driverdata *data =
144 (struct rkvop_driverdata *)dev_get_driver_data(dev);
145
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700146 u32 hactive = edid->hactive.typ;
147 u32 vactive = edid->vactive.typ;
148 u32 hsync_len = edid->hsync_len.typ;
149 u32 hback_porch = edid->hback_porch.typ;
150 u32 vsync_len = edid->vsync_len.typ;
151 u32 vback_porch = edid->vback_porch.typ;
152 u32 hfront_porch = edid->hfront_porch.typ;
153 u32 vfront_porch = edid->vfront_porch.typ;
Jacob Chen85307832016-03-14 11:20:18 +0800154 int mode_flags;
Philipp Tomsichd46d4042017-05-31 17:59:30 +0200155 u32 pin_polarity;
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700156
Philipp Tomsichd46d4042017-05-31 17:59:30 +0200157 pin_polarity = BIT(DCLK_INVERT);
158 if (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH)
159 pin_polarity |= BIT(HSYNC_POSITIVE);
160 if (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH)
161 pin_polarity |= BIT(VSYNC_POSITIVE);
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700162
Philipp Tomsichd46d4042017-05-31 17:59:30 +0200163 rkvop_set_pin_polarity(dev, mode, pin_polarity);
164 rkvop_enable_output(dev, mode);
Jacob Chen85307832016-03-14 11:20:18 +0800165
Philipp Tomsichd46d4042017-05-31 17:59:30 +0200166 mode_flags = 0; /* RGB888 */
167 if ((data->features & VOP_FEATURE_OUTPUT_10BIT) &&
168 (mode == VOP_MODE_HDMI || mode == VOP_MODE_EDP))
169 mode_flags = 15; /* RGBaaa */
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700170
Philipp Tomsichd46d4042017-05-31 17:59:30 +0200171 clrsetbits_le32(&regs->dsp_ctrl0, M_DSP_OUT_MODE,
172 V_DSP_OUT_MODE(mode_flags));
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700173
174 writel(V_HSYNC(hsync_len) |
175 V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch),
176 &regs->dsp_htotal_hs_end);
177
178 writel(V_HEAP(hsync_len + hback_porch + hactive) |
179 V_HASP(hsync_len + hback_porch),
180 &regs->dsp_hact_st_end);
181
182 writel(V_VSYNC(vsync_len) |
183 V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch),
184 &regs->dsp_vtotal_vs_end);
185
186 writel(V_VAEP(vsync_len + vback_porch + vactive)|
187 V_VASP(vsync_len + vback_porch),
188 &regs->dsp_vact_st_end);
189
190 writel(V_HEAP(hsync_len + hback_porch + hactive) |
191 V_HASP(hsync_len + hback_porch),
192 &regs->post_dsp_hact_info);
193
194 writel(V_VAEP(vsync_len + vback_porch + vactive)|
195 V_VASP(vsync_len + vback_porch),
196 &regs->post_dsp_vact_info);
197
198 writel(0x01, &regs->reg_cfg_done); /* enable reg config */
199}
200
201/**
202 * rk_display_init() - Try to enable the given display device
203 *
204 * This function performs many steps:
205 * - Finds the display device being referenced by @ep_node
206 * - Puts the VOP's ID into its uclass platform data
207 * - Probes the device to set it up
208 * - Reads the EDID timing information
209 * - Sets up the VOP clocks, etc. for the selected pixel clock and display mode
210 * - Enables the display (the display device handles this and will do different
211 * things depending on the display type)
212 * - Tells the uclass about the display resolution so that the console will
213 * appear correctly
214 *
215 * @dev: VOP device that we want to connect to the display
216 * @fbbase: Frame buffer address
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700217 * @ep_node: Device tree node to process - this is the offset of an endpoint
218 * node within the VOP's 'port' list.
219 * @return 0 if OK, -ve if something went wrong
220 */
Philipp Tomsichd46d4042017-05-31 17:59:30 +0200221static int rk_display_init(struct udevice *dev, ulong fbbase, int ep_node)
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700222{
223 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
224 const void *blob = gd->fdt_blob;
225 struct rk_vop_priv *priv = dev_get_priv(dev);
226 int vop_id, remote_vop_id;
227 struct rk3288_vop *regs = priv->regs;
228 struct display_timing timing;
229 struct udevice *disp;
230 int ret, remote, i, offset;
231 struct display_plat *disp_uc_plat;
Stephen Warren135aa952016-06-17 09:44:00 -0600232 struct clk clk;
Eric Gao8aed0d72017-05-02 18:23:53 +0800233 enum video_log2_bpp l2bpp;
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700234
235 vop_id = fdtdec_get_int(blob, ep_node, "reg", -1);
236 debug("vop_id=%d\n", vop_id);
237 remote = fdtdec_lookup_phandle(blob, ep_node, "remote-endpoint");
238 if (remote < 0)
239 return -EINVAL;
240 remote_vop_id = fdtdec_get_int(blob, remote, "reg", -1);
241 debug("remote vop_id=%d\n", remote_vop_id);
242
243 for (i = 0, offset = remote; i < 3 && offset > 0; i++)
244 offset = fdt_parent_offset(blob, offset);
245 if (offset < 0) {
246 debug("%s: Invalid remote-endpoint position\n", dev->name);
247 return -EINVAL;
248 }
249
250 ret = uclass_find_device_by_of_offset(UCLASS_DISPLAY, offset, &disp);
251 if (ret) {
252 debug("%s: device '%s' display not found (ret=%d)\n", __func__,
253 dev->name, ret);
254 return ret;
255 }
256
257 disp_uc_plat = dev_get_uclass_platdata(disp);
258 debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
Simon Glass987a4042016-11-13 14:22:08 -0700259 if (display_in_use(disp)) {
260 debug(" - device in use\n");
261 return -EBUSY;
262 }
263
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700264 disp_uc_plat->source_id = remote_vop_id;
265 disp_uc_plat->src_dev = dev;
266
267 ret = device_probe(disp);
268 if (ret) {
269 debug("%s: device '%s' display won't probe (ret=%d)\n",
270 __func__, dev->name, ret);
271 return ret;
272 }
273
274 ret = display_read_timing(disp, &timing);
275 if (ret) {
276 debug("%s: Failed to read timings\n", __func__);
277 return ret;
278 }
279
Simon Glass9ed68262016-11-13 14:21:56 -0700280 ret = clk_get_by_index(dev, 1, &clk);
Stephen Warren135aa952016-06-17 09:44:00 -0600281 if (!ret)
282 ret = clk_set_rate(&clk, timing.pixelclock.typ);
Eric Gaoe07e5bd2017-05-02 18:23:51 +0800283 if (IS_ERR_VALUE(ret)) {
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700284 debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret);
285 return ret;
286 }
287
Eric Gao8aed0d72017-05-02 18:23:53 +0800288 /* Set bitwidth for vop display according to vop mode */
289 switch (vop_id) {
290 case VOP_MODE_EDP:
Eric Gao8aed0d72017-05-02 18:23:53 +0800291 case VOP_MODE_LVDS:
292 l2bpp = VIDEO_BPP16;
293 break;
Philipp Tomsichd46d4042017-05-31 17:59:30 +0200294 case VOP_MODE_HDMI:
Eric Gao8aed0d72017-05-02 18:23:53 +0800295 case VOP_MODE_MIPI:
296 l2bpp = VIDEO_BPP32;
297 break;
298 default:
299 l2bpp = VIDEO_BPP16;
300 }
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700301
Philipp Tomsichd46d4042017-05-31 17:59:30 +0200302 rkvop_mode_set(dev, &timing, vop_id);
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700303 rkvop_enable(regs, fbbase, 1 << l2bpp, &timing);
304
305 ret = display_enable(disp, 1 << l2bpp, &timing);
306 if (ret)
307 return ret;
308
309 uc_priv->xsize = timing.hactive.typ;
310 uc_priv->ysize = timing.vactive.typ;
311 uc_priv->bpix = l2bpp;
312 debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);
313
314 return 0;
315}
316
Philipp Tomsichd46d4042017-05-31 17:59:30 +0200317void rk_vop_probe_regulators(struct udevice *dev,
318 const char * const *names, int cnt)
319{
320 int i, ret;
321 const char *name;
322 struct udevice *reg;
323
324 for (i = 0; i < cnt; ++i) {
325 name = names[i];
326 debug("%s: probing regulator '%s'\n", dev->name, name);
327
328 ret = regulator_autoset_by_name(name, &reg);
329 if (!ret)
330 ret = regulator_set_enable(reg, true);
331 }
332}
333
334int rk_vop_probe(struct udevice *dev)
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700335{
336 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
337 const void *blob = gd->fdt_blob;
338 struct rk_vop_priv *priv = dev_get_priv(dev);
Philipp Tomsichd46d4042017-05-31 17:59:30 +0200339 int ret = 0;
340 int port, node;
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700341
342 /* Before relocation we don't need to do anything */
343 if (!(gd->flags & GD_FLG_RELOC))
344 return 0;
345
Simon Glassa821c4a2017-05-17 17:18:05 -0600346 priv->regs = (struct rk3288_vop *)devfdt_get_addr(dev);
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700347
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700348 /*
349 * Try all the ports until we find one that works. In practice this
350 * tries EDP first if available, then HDMI.
Simon Glass987a4042016-11-13 14:22:08 -0700351 *
352 * Note that rockchip_vop_set_clk() always uses NPLL as the source
353 * clock so it is currently not possible to use more than one display
354 * device simultaneously.
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700355 */
Simon Glasse160f7d2017-01-17 16:52:55 -0700356 port = fdt_subnode_offset(blob, dev_of_offset(dev), "port");
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700357 if (port < 0)
358 return -EINVAL;
359 for (node = fdt_first_subnode(blob, port);
360 node > 0;
361 node = fdt_next_subnode(blob, node)) {
Eric Gao8aed0d72017-05-02 18:23:53 +0800362 ret = rk_display_init(dev, plat->base, node);
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700363 if (ret)
364 debug("Device failed: ret=%d\n", ret);
365 if (!ret)
366 break;
367 }
Simon Glassb55e04a2016-05-14 14:03:01 -0600368 video_set_flush_dcache(dev, 1);
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700369
370 return ret;
371}
372
Philipp Tomsichd46d4042017-05-31 17:59:30 +0200373int rk_vop_bind(struct udevice *dev)
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700374{
375 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
376
Philipp Tomsich89b2b612017-05-31 17:59:29 +0200377 plat->size = 4 * (CONFIG_VIDEO_ROCKCHIP_MAX_XRES *
378 CONFIG_VIDEO_ROCKCHIP_MAX_YRES);
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700379
380 return 0;
381}