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Wojtek Skulski3bbed7f2010-09-27 18:21:59 -04001/* U-boot for BlackVME. (C) Wojtek Skulski 2010.
2 * The board includes ADSP-BF561 rev. 0.5,
3 * 32-bit SDRAM (2 * MT48LC16M16A2TG or MT48LC32M16A2TG),
4 * Gigabit Ether AX88180 (ASIX) + 88E1111 rev. B2 (Marvell),
5 * SPI boot flash on PF2 (M25P64 8MB, or M25P128 16 MB),
6 * FPGA boot flash on PF3 (M25P64 8MB, or M25P128 16 MB),
7 * Spartan6-LX150 (memory-mapped; both PPIs also connected).
8 * See http://www.skutek.com
9 */
10
11#ifndef __CONFIG_BLACKVME_H__
12#define __CONFIG_BLACKVME_H__
13
14#include <asm/config-pre.h>
15
16/* Debugging: Set these options if you're having problems
17 * #define CONFIG_DEBUG_EARLY_SERIAL
18 * #define DEBUG
19 * #define CONFIG_DEBUG_DUMP
20 * #define CONFIG_DEBUG_DUMP_SYMS
21 * CONFIG_PANIC_HANG means that the board will not auto-reboot
22 */
23#define CONFIG_PANIC_HANG 0
24
25/* CPU Options */
Mike Frysingerfbcf8e82010-12-23 14:58:37 -050026#define CONFIG_BFIN_CPU bf561-0.5
27#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
Wojtek Skulski3bbed7f2010-09-27 18:21:59 -040028
29/*
30 * CLOCK SETTINGS CAVEAT
31 * You CANNOT just change the clock settings, esp. the SCLK.
32 * The SDRAM timing, SPI baud, and the serial UART baud
33 * use SCLK frequency to set their own frequencies. Therefore,
34 * if you change the SCLK_DIV, you may also have to adjust
35 * SDRAM refresh and other timings.
36 * --------------------------------------------------------------
37 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
38 * 25 * 8 / 1 = 200 MHz
39 * 25 * 16 / 1 = 400 MHz
40 * 25 * 24 / 1 = 600 MHz
41 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
42 * 25 * 8 / 2 = 100 MHz
43 * 25 * 24 / 6 = 100 MHz
44 * 25 * 24 / 5 = 120 MHz
45 * 25 * 16 / 3 = 133 MHz
46 * 25 MHz because the oscillator also feeds the ether chip.
47 * CONFIG_CLKIN_HZ is 25 MHz written in Hz
48 * CLKIN_HALF controls the DF bit in PLL_CTL
49 * 0 = CLKIN 1 = CLKIN / 2
50 * PLL_BYPASS controls the BYPASS bit in PLL_CTL
51 * 0 = do not bypass 1 = bypass PLL
52 * VCO_MULT = MSEL (multiplier) in PLL_CTL
53 * Values can range from 0-63 (where 0 means 64)
54 * CCLK_DIV = core clock divider (1, 2, 4, or 8 ONLY)
55 * SCLK_DIV = system clock divider, 1 to 15
56 */
57#define CONFIG_CLKIN_HZ 25000000
58#define CONFIG_CLKIN_HALF 0
59#define CONFIG_PLL_BYPASS 0
60#define CONFIG_VCO_MULT 8
61#define CONFIG_CCLK_DIV 1
62#define CONFIG_SCLK_DIV 2
63
64/*
65 * Ether chip in async memory space AMS3, same as BF561-EZ-KIT.
66 * Used in 32-bit mode. 16-bit mode not supported.
67 * http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:ax88180
68 */
69/*
70 * Network settings using a dedicated 2nd ether card in PC
71 * Windows will automatically acquire IP of that card
72 * Then use the dedicated card IP + 1 for the board
73 * http://docs.blackfin.uclinux.org/doku.php?id=setting_up_the_network
74 */
Wojtek Skulski3bbed7f2010-09-27 18:21:59 -040075#define CONFIG_DRIVER_AX88180 1
76#define AX88180_BASE 0x2c000000
77#define CONFIG_CMD_MII /* enable probing PHY */
78
Mike Frysinger31a4f1e2011-10-02 10:01:28 +000079#define CONFIG_HOSTNAME blackvme /* Bfin board */
80#define CONFIG_IPADDR 169.254.144.145 /* Bfin board */
81#define CONFIG_GATEWAYIP 169.254.144.144 /* dedic card */
82#define CONFIG_SERVERIP 169.254.144.144 /* tftp server */
83#define CONFIG_NETMASK 255.255.255.0
Joe Hershberger8b3637c2011-10-13 13:03:47 +000084#define CONFIG_ROOTPATH "/export/uClinux-dist/romfs" /*NFS*/
Mike Frysinger31a4f1e2011-10-02 10:01:28 +000085#define CFG_AUTOLOAD "no"
86#define CONFIG_CMD_DHCP
87#define CONFIG_CMD_PING
Wojtek Skulski3bbed7f2010-09-27 18:21:59 -040088
89/*
90 * SDRAM settings & memory map
91 */
92
93#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */
94#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */
95/*
96 * SDRAM reference page
97 * http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
98 * NOTE: BlackVME populates only SDRAM bank 0
99 */
100/* CONFIG_EBIU_SDBCTL_VAL bank ctrl may be needed in future */
101#define CONFIG_EBIU_SDGCTL_VAL 0x91114d /* global control */
102#define CONFIG_EBIU_SDRRC_VAL 0x306 /* refresh rate */
103
104/* Async memory global settings. (ASRAM, not SDRAM)
105 * HRM page 16-10. Global ASRAM control = 0x3F. Six lower bits = 1
106 * CLKOUT enabled, all async banks enabled, core has priority
107 * bank 0&1 16 bit (FPGA)
108 * bank 2&3 32 bit (ether and USB chips)
109 */
110#define CONFIG_EBIU_AMGCTL_VAL 0x3F /* ASRAM setup */
111
112/* Async mem timing: BF561 HRM page 16-12 and 16-15.
113 * Default values 0xFFC2 FFC2 are the slowest supported.
114 * Example settings of CONFIG_EBIU_AMBCTL1_VAL
115 * 1. EZ-KIT settings: 0xFFC2 7BB0
116 * 2. Bank 3 good timing for AX88180 @ 125MHz = 0x8850 xxxx
117 * See the following page:
118 * http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:ax88180
119 * 3. Bank 3 timing for AX88180 @ SCLK = 100 MHz:
120 * AX88180 WEN = 5 clocks REN 6 clocks @ SCLK = 100 MHz
121 * One extra clock needed because AX88180 is asynchronous to CPU.
122 */
Wolfgang Denk071bc922010-10-27 22:48:30 +0200123 /* bank 1 0 */
Wojtek Skulski3bbed7f2010-09-27 18:21:59 -0400124#define CONFIG_EBIU_AMBCTL0_VAL 0xFFC2FFC2
Wolfgang Denk071bc922010-10-27 22:48:30 +0200125 /* bank 3 2 */
Wojtek Skulski3bbed7f2010-09-27 18:21:59 -0400126#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC2FFC2
127
128/* memory layout */
129
130#define CONFIG_SYS_MONITOR_LEN (256 << 10)
131#define CONFIG_SYS_MALLOC_LEN (384 << 10)
132
133/*
134 * Serial SPI Flash
135 * For the M25P64 SCK should be kept < 15 MHz
136 */
137#define CONFIG_BFIN_SPI
138#define CONFIG_ENV_IS_IN_SPI_FLASH
139#define CONFIG_ENV_OFFSET 0x40000
140#define CONFIG_ENV_SIZE 0x2000
141#define CONFIG_ENV_SECT_SIZE 0x40000
142
143#define CONFIG_ENV_SPI_MAX_HZ 15000000
144#define CONFIG_SF_DEFAULT_SPEED 15000000
Wojtek Skulski3bbed7f2010-09-27 18:21:59 -0400145#define CONFIG_SPI_FLASH_STMICRO
146
147/*
148 * Interactive command settings
149 */
150
151#define CONFIG_SYS_LONGHELP 1
152#define CONFIG_CMDLINE_EDITING 1
153#define CONFIG_AUTO_COMPLETE 1
154
Wojtek Skulski3bbed7f2010-09-27 18:21:59 -0400155#define CONFIG_CMD_BOOTLDR
156#define CONFIG_CMD_CACHE
157#define CONFIG_CMD_CPLBINFO
158#define CONFIG_CMD_SF
Wojtek Skulski3bbed7f2010-09-27 18:21:59 -0400159
160/*
161 * Default: boot from SPI flash.
162 * "sfboot" is a composite command defined in extra settings
163 */
164#define CONFIG_BOOTDELAY 5
165#define CONFIG_BOOTCOMMAND "run sfboot"
166
167/*
168 * Console settings
169 */
170#define CONFIG_BAUDRATE 57600
171#define CONFIG_LOADS_ECHO 1
172#define CONFIG_UART_CONSOLE 0
Sonic Zhang7b27a682013-12-09 12:19:38 +0800173#define CONFIG_BFIN_SERIAL
Wojtek Skulski3bbed7f2010-09-27 18:21:59 -0400174
175/*
176 * U-Boot environment variables. Use "printenv" to examine.
177 * http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot:env
178 */
179#define CONFIG_BOOTARGS \
180 "root=/dev/mtdblock0 rw " \
Marek Vasut5368c552012-09-23 17:41:24 +0200181 "clkin_hz=" __stringify(CONFIG_CLKIN_HZ) " " \
Wojtek Skulski3bbed7f2010-09-27 18:21:59 -0400182 "earlyprintk=serial,uart0," \
Marek Vasut5368c552012-09-23 17:41:24 +0200183 __stringify(CONFIG_BAUDRATE) " " \
184 "console=ttyBF0," __stringify(CONFIG_BAUDRATE) " "
Wojtek Skulski3bbed7f2010-09-27 18:21:59 -0400185
186/* Convenience env variables & commands.
187 * Reserve kernstart = 0x20000 = 128 kB for U-Boot.
188 * Reserve kernarea = 0x500000 = 5 MB for kernel (reasonable size).
189 * U-Boot image is saved at flash offset=0.
190 * Kernel image is saved at flash offset=$kernstart.
191 * Instructions. Ksave takes about a minute to complete.
192 * 1. Update U-Boot: run uget; run usave
193 * 2. Update kernel: run kget; run ksave
194 * After updating U-Boot also update the kernel per above instructions
195 * to make the saved environment consistent with the flash.
196 */
197#define CONFIG_EXTRA_ENV_SETTINGS \
198 "kernstart=0x20000\0" \
199 "kernarea=0x500000\0" \
200 "uget=tftp u-boot.ldr\0" \
201 "kget=tftp uImage\0" \
202 "usave=sf probe 2; " \
203 "sf erase 0 $(kernstart); " \
204 "sf write $(fileaddr) 0 $(filesize)\0" \
205 "ksave=sf probe 2; " \
206 "saveenv; " \
207 "echo Now patiently wait for the prompt...; " \
208 "sf erase $(kernstart) $(kernarea); " \
209 "sf write $(fileaddr) $(kernstart) $(filesize)\0" \
210 "sfboot=sf probe 2; " \
211 "sf read $(loadaddr) $(kernstart) $(filesize); " \
212 "run addip; bootm\0" \
213 "addip=setenv bootargs $(bootargs) " \
214 "ip=$(ipaddr):$(serverip):$(gatewayip):" \
215 "$(netmask):$(hostname):eth0:off\0"
216
217/*
218 * Soft I2C settings (BF561 does not have hard I2C)
219 * PF12,13 on SPI connector 0.
220 */
Heiko Schocherea818db2013-01-29 08:53:15 +0100221#ifdef CONFIG_SYS_I2C_SOFT
Wojtek Skulski3bbed7f2010-09-27 18:21:59 -0400222# define CONFIG_CMD_I2C
223# define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF12
224# define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF13
225# define CONFIG_SYS_I2C_SPEED 50000
226# define CONFIG_SYS_I2C_SLAVE 0xFE
227#endif
228
229/*
230 * No Parallel Flash on this board
231 */
232#define CONFIG_SYS_NO_FLASH
Wojtek Skulski3bbed7f2010-09-27 18:21:59 -0400233#undef CONFIG_CMD_JFFS2
Wojtek Skulski3bbed7f2010-09-27 18:21:59 -0400234
235#endif