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Dirk Eibach255ef4d2011-10-20 11:12:55 +02001/*
2 * (C) Copyright 2011
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
5 * based on kilauea.h
6 * by Stefan Roese, DENX Software Engineering, sr@denx.de.
7 * and Grant Erickson <gerickson@nuovations.com>
8 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02009 * SPDX-License-Identifier: GPL-2.0+
Dirk Eibach255ef4d2011-10-20 11:12:55 +020010 */
11
12/************************************************************************
13 * io64.h - configuration for Guntermann & Drunck Io64 (405EX)
14 ***********************************************************************/
15
16#ifndef __CONFIG_H
17#define __CONFIG_H
18
19/*-----------------------------------------------------------------------
20 * High Level Configuration Options
21 *----------------------------------------------------------------------*/
22#define CONFIG_IO64 1 /* Board is Io64 */
Dirk Eibach255ef4d2011-10-20 11:12:55 +020023#define CONFIG_405EX 1 /* Specifc 405EX support*/
24#define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */
25
26#ifndef CONFIG_SYS_TEXT_BASE
27#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
28#endif
29
30/*
31 * CHIP_21 errata
32 */
33#define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
34
35/*
36 * Include common defines/options for all AMCC eval boards
37 */
38#define CONFIG_HOSTNAME io64
Dirk Eibach996d88d2012-04-26 03:54:25 +000039#define CONFIG_IDENT_STRING " io64 0.02"
Dirk Eibach255ef4d2011-10-20 11:12:55 +020040#include "amcc-common.h"
41
42#define CONFIG_BOARD_EARLY_INIT_F
43#define CONFIG_BOARD_EARLY_INIT_R
44#define CONFIG_MISC_INIT_R
45#define CONFIG_LAST_STAGE_INIT
46
47#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
Dirk Eibach255ef4d2011-10-20 11:12:55 +020048
49/* new uImage format support */
50#define CONFIG_FIT
51#define CONFIG_FIT_VERBOSE
52
53/*-----------------------------------------------------------------------
54 * Base addresses -- Note these are effective addresses where the
55 * actual resources get mapped (not physical addresses)
56 *----------------------------------------------------------------------*/
57#define CONFIG_SYS_FLASH_BASE 0xFC000000
58#define CONFIG_SYS_NVRAM_BASE 0xF0000000
59#define CONFIG_SYS_FPGA0_BASE 0xF0100000
60#define CONFIG_SYS_FPGA1_BASE 0xF0108000
61#define CONFIG_SYS_LATCH_BASE 0xF0200000
62
63/*-----------------------------------------------------------------------
64 * Initial RAM & Stack Pointer Configuration Options
65 *
66 * There are traditionally three options for the primordial
67 * (i.e. initial) stack usage on the 405-series:
68 *
69 * 1) On-chip Memory (OCM) (i.e. SRAM)
70 * 2) Data cache
71 * 3) SDRAM
72 *
73 * For the 405EX(r), there is no OCM, so we are left with (2) or (3)
74 * the latter of which is less than desireable since it requires
75 * setting up the SDRAM and ECC in assembly code.
76 *
77 * To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
78 * select on the External Bus Controller (EBC) and then select a
79 * value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
80 * physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
81 * select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
82 * physical SDRAM to use (3).
83 *-----------------------------------------------------------------------*/
84
85#define CONFIG_SYS_INIT_DCACHE_CS 4
86
87#if defined(CONFIG_SYS_INIT_DCACHE_CS)
88#define CONFIG_SYS_INIT_RAM_ADDR \
89 (CONFIG_SYS_SDRAM_BASE + (1 << 30)) /* 1 GiB */
90#else
91#define CONFIG_SYS_INIT_RAM_ADDR \
92 (CONFIG_SYS_SDRAM_BASE + (32 << 20)) /* 32 MiB */
93#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
94
95#define CONFIG_SYS_INIT_RAM_SIZE \
96 (4 << 10) /* 4 KiB */
97#define CONFIG_SYS_GBL_DATA_OFFSET \
98 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
99
100/*
101 * If the data cache is being used for the primordial stack and global
102 * data area, the POST word must be placed somewhere else. The General
103 * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
104 * its compare and mask register contents across reset, so it is used
105 * for the POST word.
106 */
107
108#if defined(CONFIG_SYS_INIT_DCACHE_CS)
109# define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
110# define CONFIG_SYS_POST_WORD_ADDR \
111 (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
112#else
113# define CONFIG_SYS_INIT_EXTRA_SIZE 16
114# define CONFIG_SYS_INIT_SP_OFFSET \
115 (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
116# define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_INIT_RAM_ADDR
117#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
118
119/*-----------------------------------------------------------------------
120 * Serial Port
121 *----------------------------------------------------------------------*/
122#define CONFIG_CONS_INDEX 1 /* Use UART0 */
123#define CONFIG_SYS_BASE_BAUD 691200
124
125/*-----------------------------------------------------------------------
126 * Environment
127 *----------------------------------------------------------------------*/
128#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
129
130/*-----------------------------------------------------------------------
131 * FLASH related
132 *----------------------------------------------------------------------*/
133#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
134#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
135
136#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
137#define CONFIG_SYS_MAX_FLASH_BANKS 1
138#define CONFIG_SYS_MAX_FLASH_SECT 512
139
140#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
141#define CONFIG_SYS_FLASH_WRITE_TOUT 500
142
143#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
144#define CONFIG_SYS_FLASH_EMPTY_INFO
145
146#ifdef CONFIG_ENV_IS_IN_FLASH
147#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
148#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
149#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
150
151/* Address and size of Redundant Environment Sector */
152#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
153#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
154#endif /* CONFIG_ENV_IS_IN_FLASH */
155
156/* Gbit PHYs */
157#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
158#define CONFIG_BITBANGMII_MULTI
159
160#define CONFIG_SYS_MDIO_PIN (0x80000000 >> 12) /* MDIO is GPIO12 */
161#define CONFIG_SYS_MDC_PIN (0x80000000 >> 13) /* MDC is GPIO13 */
162
163#define CONFIG_SYS_GBIT_MII_BUSNAME "io_miiphy0"
164
165#define CONFIG_SYS_MDIO1_PIN (0x80000000 >> 2) /* MDIO is GPIO2 */
166#define CONFIG_SYS_MDC1_PIN (0x80000000 >> 3) /* MDC is GPIO3 */
167
168#define CONFIG_SYS_GBIT_MII1_BUSNAME "io_miiphy1"
169
170/*-----------------------------------------------------------------------
171 * DDR SDRAM
172 *----------------------------------------------------------------------*/
173#define CONFIG_SYS_MBYTES_SDRAM (128) /* 128MB */
174
175/*
176 * CONFIG_PPC4xx_DDR_AUTOCALIBRATION
177 *
178 * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx
179 * SDRAM Controller DDR autocalibration values and takes a lot longer
180 * to run than Method_B.
181 * (See the Method_A and Method_B algorithm discription in the file:
182 * arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
183 * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
184 *
185 * DDR Autocalibration Method_B is the default.
186 */
187#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION
188#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION
189#undef CONFIG_PPC4xx_DDR_METHOD_A
190
191#define CONFIG_SYS_SDRAM0_MB0CF_BASE ((0 << 20) + CONFIG_SYS_SDRAM_BASE)
192
193/* DDR1/2 SDRAM Device Control Register Data Values */
194#define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3) | \
195 SDRAM_RXBAS_SDSZ_128MB | \
196 SDRAM_RXBAS_SDAM_MODE2 | \
197 SDRAM_RXBAS_SDBE_ENABLE)
198#define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
199#define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
200#define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
201#define CONFIG_SYS_SDRAM0_MCOPT1 (SDRAM_MCOPT1_PMU_OPEN | \
202 SDRAM_MCOPT1_4_BANKS | \
203 SDRAM_MCOPT1_DDR2_TYPE | \
204 SDRAM_MCOPT1_QDEP | \
205 SDRAM_MCOPT1_DCOO_DISABLED)
206#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
207#define CONFIG_SYS_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \
208 SDRAM_MODT_EB0R_ENABLE)
209#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
210#define CONFIG_SYS_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \
211 SDRAM_CODT_CKLZ_36OHM | \
212 SDRAM_CODT_DQS_1_8_V_DDR2 | \
213 SDRAM_CODT_IO_NMODE)
214#define CONFIG_SYS_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560)
215#define CONFIG_SYS_SDRAM0_INITPLR0 (SDRAM_INITPLR_ENABLE | \
216 SDRAM_INITPLR_IMWT_ENCODE(80) | \
217 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
218#define CONFIG_SYS_SDRAM0_INITPLR1 (SDRAM_INITPLR_ENABLE | \
219 SDRAM_INITPLR_IMWT_ENCODE(3) | \
220 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
221 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
222 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
223#define CONFIG_SYS_SDRAM0_INITPLR2 (SDRAM_INITPLR_ENABLE | \
224 SDRAM_INITPLR_IMWT_ENCODE(2) | \
225 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
226 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \
227 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
228#define CONFIG_SYS_SDRAM0_INITPLR3 (SDRAM_INITPLR_ENABLE | \
229 SDRAM_INITPLR_IMWT_ENCODE(2) | \
230 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
231 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \
232 SDRAM_INITPLR_IMA_ENCODE(0))
233#define CONFIG_SYS_SDRAM0_INITPLR4 (SDRAM_INITPLR_ENABLE | \
234 SDRAM_INITPLR_IMWT_ENCODE(2) | \
235 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
236 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
237 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
238 JEDEC_MA_EMR_RTT_75OHM))
239#define CONFIG_SYS_SDRAM0_INITPLR5 (SDRAM_INITPLR_ENABLE | \
240 SDRAM_INITPLR_IMWT_ENCODE(2) | \
241 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
242 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
243 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
244 JEDEC_MA_MR_CL_DDR2_5_0_CLK | \
245 JEDEC_MA_MR_BLEN_4 | \
246 JEDEC_MA_MR_DLL_RESET))
247#define CONFIG_SYS_SDRAM0_INITPLR6 (SDRAM_INITPLR_ENABLE | \
248 SDRAM_INITPLR_IMWT_ENCODE(3) | \
249 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
250 SDRAM_INITPLR_IBA_ENCODE(0x0) | \
251 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
252#define CONFIG_SYS_SDRAM0_INITPLR7 (SDRAM_INITPLR_ENABLE | \
253 SDRAM_INITPLR_IMWT_ENCODE(26) | \
254 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
255#define CONFIG_SYS_SDRAM0_INITPLR8 (SDRAM_INITPLR_ENABLE | \
256 SDRAM_INITPLR_IMWT_ENCODE(26) | \
257 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
258#define CONFIG_SYS_SDRAM0_INITPLR9 (SDRAM_INITPLR_ENABLE | \
259 SDRAM_INITPLR_IMWT_ENCODE(26) | \
260 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
261#define CONFIG_SYS_SDRAM0_INITPLR10 (SDRAM_INITPLR_ENABLE | \
262 SDRAM_INITPLR_IMWT_ENCODE(26) | \
263 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
264#define CONFIG_SYS_SDRAM0_INITPLR11 (SDRAM_INITPLR_ENABLE | \
265 SDRAM_INITPLR_IMWT_ENCODE(2) | \
266 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
267 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
268 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
269 JEDEC_MA_MR_CL_DDR2_5_0_CLK | \
270 JEDEC_MA_MR_BLEN_4))
271#define CONFIG_SYS_SDRAM0_INITPLR12 (SDRAM_INITPLR_ENABLE | \
272 SDRAM_INITPLR_IMWT_ENCODE(2) | \
273 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
274 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
275 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
276 JEDEC_MA_EMR_RDQS_DISABLE | \
277 JEDEC_MA_EMR_DQS_DISABLE | \
278 JEDEC_MA_EMR_RTT_DISABLED | \
279 JEDEC_MA_EMR_ODS_NORMAL))
280#define CONFIG_SYS_SDRAM0_INITPLR13 (SDRAM_INITPLR_ENABLE | \
281 SDRAM_INITPLR_IMWT_ENCODE(2) | \
282 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
283 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
284 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
285 JEDEC_MA_EMR_RDQS_DISABLE | \
286 JEDEC_MA_EMR_DQS_DISABLE | \
287 JEDEC_MA_EMR_RTT_DISABLED | \
288 JEDEC_MA_EMR_ODS_NORMAL))
289#define CONFIG_SYS_SDRAM0_INITPLR14 (SDRAM_INITPLR_DISABLE)
290#define CONFIG_SYS_SDRAM0_INITPLR15 (SDRAM_INITPLR_DISABLE)
291#define CONFIG_SYS_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \
292 SDRAM_RQDC_RQFD_ENCODE(56))
293#define CONFIG_SYS_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(521)
294#define CONFIG_SYS_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2)
295#define CONFIG_SYS_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \
296 SDRAM_DLCR_DLCS_CONT_DONE | \
297 SDRAM_DLCR_DLCV_ENCODE(165))
298#define CONFIG_SYS_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV)
299#define CONFIG_SYS_SDRAM0_WRDTR 0x00000000
300#define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \
301 SDRAM_SDTR1_RTW_2_CLK | \
302 SDRAM_SDTR1_WTWO_1_CLK | \
303 SDRAM_SDTR1_RTRO_1_CLK)
304#define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \
305 SDRAM_SDTR2_WTR_2_CLK | \
306 SDRAM_SDTR2_XSNR_32_CLK | \
307 SDRAM_SDTR2_WPC_4_CLK | \
308 SDRAM_SDTR2_RPC_2_CLK | \
309 SDRAM_SDTR2_RP_3_CLK | \
310 SDRAM_SDTR2_RRD_2_CLK)
311#define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(9) | \
312 SDRAM_SDTR3_RC_ENCODE(12) | \
313 SDRAM_SDTR3_XCS | \
314 SDRAM_SDTR3_RFC_ENCODE(21))
315#define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \
316 SDRAM_MMODE_DCL_DDR2_5_0_CLK | \
317 SDRAM_MMODE_BLEN_4)
318#define CONFIG_SYS_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_DISABLE | \
319 SDRAM_MEMODE_RTT_75OHM)
320
321/*-----------------------------------------------------------------------
322 * I2C
323 *----------------------------------------------------------------------*/
Dirk Eibach880540d2013-04-25 02:40:01 +0000324#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
Dirk Eibach255ef4d2011-10-20 11:12:55 +0200325
326#define CONFIG_PCA9698 1 /* NXP PCA9698 */
327
328#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */
329#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
330#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
331#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
332
333/* I2C bootstrap EEPROM */
334#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54
335#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
336#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
337
338/* Temp sensor/hwmon/dtt */
339#define CONFIG_DTT_LM63 1 /* National LM63 */
340#define CONFIG_DTT_SENSORS { 0x18, 0x4c, 0x4e } /* Sensor addresses */
341#define CONFIG_DTT_PWM_LOOKUPTABLE \
342 { { 40, 10 }, { 43, 13 }, { 46, 16 }, \
343 { 50, 20 }, { 53, 27 }, { 56, 34 }, { 60, 40 } }
344#define CONFIG_DTT_TACH_LIMIT 0xa10
345
346/*-----------------------------------------------------------------------
347 * Ethernet
348 *----------------------------------------------------------------------*/
349#define CONFIG_M88E1111_PHY 1
350#define CONFIG_IBM_EMAC4_V4 1
351#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII
352#define CONFIG_PHY_ADDR 0x12 /* PHY address, See schematics */
353
354#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
355#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
356
357#define CONFIG_HAS_ETH0 1
358
359#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
360#define CONFIG_PHY1_ADDR 0x13
361
362/* Debug messages for the DDR autocalibration */
363#define CONFIG_AUTOCALIB "silent\0"
364
365/*
366 * Default environment variables
367 */
368#define CONFIG_EXTRA_ENV_SETTINGS \
369 CONFIG_AMCC_DEF_ENV \
370 CONFIG_AMCC_DEF_ENV_POWERPC \
371 CONFIG_AMCC_DEF_ENV_PPC_OLD \
372 CONFIG_AMCC_DEF_ENV_NOR_UPD \
373 "logversion=2\0" \
374 "kernel_addr=fc000000\0" \
375 "fdt_addr=fc1e0000\0" \
376 "ramdisk_addr=fc200000\0" \
377 "pciconfighost=1\0" \
378 "pcie_mode=RP:RP\0" \
379 ""
380
381/*
382 * Commands additional to the ones defined in amcc-common.h
383 */
384#define CONFIG_CMD_CHIP_CONFIG
385#define CONFIG_CMD_DTT
386
387#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
388
389/* POST support */
390#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
391 CONFIG_SYS_POST_CPU | \
392 CONFIG_SYS_POST_ETHER | \
393 CONFIG_SYS_POST_I2C | \
394 CONFIG_SYS_POST_MEMORY_ON | \
395 CONFIG_SYS_POST_UART)
396
397/* Define here the base-addresses of the UARTs to test in POST */
398#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
399 CONFIG_SYS_NS16550_COM2 }
400
401#define CONFIG_LOGBUFFER
402#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
403
404#define CONFIG_SYS_CONSOLE_IS_IN_ENV
405
406/*-----------------------------------------------------------------------
407 * External Bus Controller (EBC) Setup
408 *----------------------------------------------------------------------*/
409
410/* Memory Bank 0 (NOR-flash) */
411#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
412 EBC_BXAP_TWT_ENCODE(11) | \
413 EBC_BXAP_BCE_DISABLE | \
414 EBC_BXAP_BCT_2TRANS | \
415 EBC_BXAP_CSN_ENCODE(0) | \
416 EBC_BXAP_OEN_ENCODE(0) | \
417 EBC_BXAP_WBN_ENCODE(1) | \
418 EBC_BXAP_WBF_ENCODE(2) | \
419 EBC_BXAP_TH_ENCODE(2) | \
420 EBC_BXAP_RE_DISABLED | \
421 EBC_BXAP_SOR_NONDELAYED | \
422 EBC_BXAP_BEM_WRITEONLY | \
423 EBC_BXAP_PEN_DISABLED)
424#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
425 EBC_BXCR_BS_64MB | \
426 EBC_BXCR_BU_RW | \
427 EBC_BXCR_BW_16BIT)
428
429/* Memory Bank 1 (NVRAM/Uart) */
430#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_ENABLED | \
431 EBC_BXAP_FWT_ENCODE(8) | \
432 EBC_BXAP_BWT_ENCODE(4) | \
433 EBC_BXAP_BCE_DISABLE | \
434 EBC_BXAP_BCT_2TRANS | \
435 EBC_BXAP_CSN_ENCODE(0) | \
436 EBC_BXAP_OEN_ENCODE(1) | \
437 EBC_BXAP_WBN_ENCODE(1) | \
438 EBC_BXAP_WBF_ENCODE(1) | \
439 EBC_BXAP_TH_ENCODE(2) | \
440 EBC_BXAP_RE_DISABLED | \
441 EBC_BXAP_SOR_NONDELAYED | \
442 EBC_BXAP_BEM_WRITEONLY | \
443 EBC_BXAP_PEN_DISABLED)
444#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_NVRAM_BASE) | \
445 EBC_BXCR_BS_1MB | \
446 EBC_BXCR_BU_RW | \
447 EBC_BXCR_BW_8BIT)
448
449/* Memory Bank 2 (FPGA) */
450#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \
451 EBC_BXAP_TWT_ENCODE(5) | \
452 EBC_BXAP_BCE_DISABLE | \
453 EBC_BXAP_BCT_2TRANS | \
454 EBC_BXAP_CSN_ENCODE(0) | \
455 EBC_BXAP_OEN_ENCODE(2) | \
456 EBC_BXAP_WBN_ENCODE(1) | \
457 EBC_BXAP_WBF_ENCODE(1) | \
458 EBC_BXAP_TH_ENCODE(0) | \
459 EBC_BXAP_RE_DISABLED | \
460 EBC_BXAP_SOR_NONDELAYED | \
461 EBC_BXAP_BEM_WRITEONLY | \
462 EBC_BXAP_PEN_DISABLED)
463#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
464 EBC_BXCR_BS_1MB | \
465 EBC_BXCR_BU_RW | \
466 EBC_BXCR_BW_16BIT)
467
468/* Memory Bank 3 (Latches) */
469#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_ENABLED | \
470 EBC_BXAP_FWT_ENCODE(8) | \
471 EBC_BXAP_BWT_ENCODE(4) | \
472 EBC_BXAP_BCE_DISABLE | \
473 EBC_BXAP_BCT_2TRANS | \
474 EBC_BXAP_CSN_ENCODE(0) | \
475 EBC_BXAP_OEN_ENCODE(1) | \
476 EBC_BXAP_WBN_ENCODE(1) | \
477 EBC_BXAP_WBF_ENCODE(1) | \
478 EBC_BXAP_TH_ENCODE(2) | \
479 EBC_BXAP_RE_DISABLED | \
480 EBC_BXAP_SOR_NONDELAYED | \
481 EBC_BXAP_BEM_WRITEONLY | \
482 EBC_BXAP_PEN_DISABLED)
483#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
484 EBC_BXCR_BS_1MB | \
485 EBC_BXCR_BU_RW | \
486 EBC_BXCR_BW_16BIT)
487
488/* EBC peripherals */
489
490#define CONFIG_SYS_FPGA_BASE(k) \
491 (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
492
493#define CONFIG_SYS_FPGA_DONE(k) \
494 (k ? 0x0040 : 0x0080)
495
496#define CONFIG_SYS_FPGA_COUNT 2
497
Dirk Eibachaba27ac2013-06-26 16:04:26 +0200498#define CONFIG_SYS_FPGA_PTR { \
499 (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
500 (struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
501
502#define CONFIG_SYS_FPGA_COMMON
503
Dirk Eibach255ef4d2011-10-20 11:12:55 +0200504#define CONFIG_SYS_LATCH0_RESET 0xffff
505#define CONFIG_SYS_LATCH0_BOOT 0xffff
506#define CONFIG_SYS_LATCH1_RESET 0xffbf
507#define CONFIG_SYS_LATCH1_BOOT 0xffff
508
509/*-----------------------------------------------------------------------
510 * GPIO Setup
511 *----------------------------------------------------------------------*/
512#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO */ \
513{ \
514/* GPIO Core 0 */ \
515{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO0 */ \
516{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO1 */ \
517{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO2 */ \
518{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO3 */ \
519{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO4 */ \
520{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO5 */ \
521{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO6 */ \
522{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 */ \
523{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO8 */ \
524{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO9 */ \
525{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO10 */ \
526{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO11 */ \
527{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO12 */ \
528{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO13 */ \
529{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO14 */ \
530{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO15 */ \
531{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO16 */ \
532{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO17 */ \
533{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO18 */ \
534{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO19 */ \
535{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO20 */ \
536{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO21 */ \
537{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO22 */ \
538{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO23 */ \
539{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO24 */ \
540{GPIO0_BASE, GPIO_IN, GPIO_ALT3, GPIO_OUT_0 }, /* GPIO25 */ \
541{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO26 */ \
542{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO27 */ \
543{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO28 */ \
544{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO29 */ \
545{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO30 */ \
546{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO31 */ \
547} \
548}
549
550#define CONFIG_SYS_GPIO_STARTUP_FINISHED 15
551#define CONFIG_SYS_GPIO_STARTUP_FINISHED_N 14
552
553#endif /* __CONFIG_H */