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Roy Zang111fd192012-10-08 07:44:21 +00001/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Roy Zang <tie-fei.zang@freescale.com>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Roy Zang111fd192012-10-08 07:44:21 +00006 */
7
8#ifndef __MEMAC_H__
9#define __MEMAC_H__
10
11#include <phy.h>
12
13struct memac {
14 /* memac general control and status registers */
15 u32 res_0[2];
16 u32 command_config; /* Control and configuration register */
17 u32 mac_addr_0; /* Lower 32 bits of 48-bit MAC address */
18 u32 mac_addr_1; /* Upper 16 bits of 48-bit MAC address */
19 u32 maxfrm; /* Maximum frame length register */
20 u32 res_18[5];
21 u32 hashtable_ctrl; /* Hash table control register */
22 u32 res_30[4];
23 u32 ievent; /* Interrupt event register */
24 u32 tx_ipg_length; /* Transmitter inter-packet-gap register */
25 u32 res_48;
26 u32 imask; /* interrupt mask register */
27 u32 res_50;
28 u32 cl_pause_quanta[4]; /* CL01-CL67 pause quanta register */
29 u32 cl_pause_thresh[4]; /* CL01-CL67 pause thresh register */
30 u32 rx_pause_status; /* Receive pause status register */
31 u32 res_78[2];
32 u32 mac_addr[14]; /* MAC address */
33 u32 lpwake_timer; /* EEE low power wakeup timer register */
34 u32 sleep_timer; /* Transmit EEE Low Power Timer register */
35 u32 res_c0[8];
36 u32 statn_config; /* Statistics configuration register */
37 u32 res_e4[7];
38
39 /* memac statistics counter registers */
40 u32 rx_eoct_l; /* Rx ethernet octests lower */
41 u32 rx_eoct_u; /* Rx ethernet octests upper */
42 u32 rx_oct_l; /* Rx octests lower */
43 u32 rx_oct_u; /* Rx octests upper */
44 u32 rx_align_err_l; /* Rx alignment error lower */
45 u32 rx_align_err_u; /* Rx alignment error upper */
46 u32 rx_pause_frame_l; /* Rx valid pause frame upper */
47 u32 rx_pause_frame_u; /* Rx valid pause frame upper */
48 u32 rx_frame_l; /* Rx frame counter lower */
49 u32 rx_frame_u; /* Rx frame counter upper */
50 u32 rx_frame_crc_err_l; /* Rx frame check sequence error lower */
51 u32 rx_frame_crc_err_u; /* Rx frame check sequence error upper */
52 u32 rx_vlan_l; /* Rx VLAN frame lower */
53 u32 rx_vlan_u; /* Rx VLAN frame upper */
54 u32 rx_err_l; /* Rx frame error lower */
55 u32 rx_err_u; /* Rx frame error upper */
56 u32 rx_uni_l; /* Rx unicast frame lower */
57 u32 rx_uni_u; /* Rx unicast frame upper */
58 u32 rx_multi_l; /* Rx multicast frame lower */
59 u32 rx_multi_u; /* Rx multicast frame upper */
60 u32 rx_brd_l; /* Rx broadcast frame lower */
61 u32 rx_brd_u; /* Rx broadcast frame upper */
62 u32 rx_drop_l; /* Rx dropped packets lower */
63 u32 rx_drop_u; /* Rx dropped packets upper */
64 u32 rx_pkt_l; /* Rx packets lower */
65 u32 rx_pkt_u; /* Rx packets upper */
66 u32 rx_undsz_l; /* Rx undersized packet lower */
67 u32 rx_undsz_u; /* Rx undersized packet upper */
68 u32 rx_64_l; /* Rx 64 oct packet lower */
69 u32 rx_64_u; /* Rx 64 oct packet upper */
70 u32 rx_127_l; /* Rx 65 to 127 oct packet lower */
71 u32 rx_127_u; /* Rx 65 to 127 oct packet upper */
72 u32 rx_255_l; /* Rx 128 to 255 oct packet lower */
73 u32 rx_255_u; /* Rx 128 to 255 oct packet upper */
74 u32 rx_511_l; /* Rx 256 to 511 oct packet lower */
75 u32 rx_511_u; /* Rx 256 to 511 oct packet upper */
76 u32 rx_1023_l; /* Rx 512 to 1023 oct packet lower */
77 u32 rx_1023_u; /* Rx 512 to 1023 oct packet upper */
78 u32 rx_1518_l; /* Rx 1024 to 1518 oct packet lower */
79 u32 rx_1518_u; /* Rx 1024 to 1518 oct packet upper */
80 u32 rx_1519_l; /* Rx 1519 to max oct packet lower */
81 u32 rx_1519_u; /* Rx 1519 to max oct packet upper */
82 u32 rx_oversz_l; /* Rx oversized packet lower */
83 u32 rx_oversz_u; /* Rx oversized packet upper */
84 u32 rx_jabber_l; /* Rx Jabber packet lower */
85 u32 rx_jabber_u; /* Rx Jabber packet upper */
86 u32 rx_frag_l; /* Rx Fragment packet lower */
87 u32 rx_frag_u; /* Rx Fragment packet upper */
88 u32 rx_cnp_l; /* Rx control packet lower */
89 u32 rx_cnp_u; /* Rx control packet upper */
90 u32 rx_drntp_l; /* Rx dripped not truncated packet lower */
91 u32 rx_drntp_u; /* Rx dripped not truncated packet upper */
92 u32 res_1d0[0xc];
93
94 u32 tx_eoct_l; /* Tx ethernet octests lower */
95 u32 tx_eoct_u; /* Tx ethernet octests upper */
96 u32 tx_oct_l; /* Tx octests lower */
97 u32 tx_oct_u; /* Tx octests upper */
98 u32 res_210[0x2];
99 u32 tx_pause_frame_l; /* Tx valid pause frame lower */
100 u32 tx_pause_frame_u; /* Tx valid pause frame upper */
101 u32 tx_frame_l; /* Tx frame counter lower */
102 u32 tx_frame_u; /* Tx frame counter upper */
103 u32 tx_frame_crc_err_l; /* Tx frame check sequence error lower */
104 u32 tx_frame_crc_err_u; /* Tx frame check sequence error upper */
105 u32 tx_vlan_l; /* Tx VLAN frame lower */
106 u32 tx_vlan_u; /* Tx VLAN frame upper */
107 u32 tx_frame_err_l; /* Tx frame error lower */
108 u32 tx_frame_err_u; /* Tx frame error upper */
109 u32 tx_uni_l; /* Tx unicast frame lower */
110 u32 tx_uni_u; /* Tx unicast frame upper */
111 u32 tx_multi_l; /* Tx multicast frame lower */
112 u32 tx_multi_u; /* Tx multicast frame upper */
113 u32 tx_brd_l; /* Tx broadcast frame lower */
114 u32 tx_brd_u; /* Tx broadcast frame upper */
115 u32 res_258[0x2];
116 u32 tx_pkt_l; /* Tx packets lower */
117 u32 tx_pkt_u; /* Tx packets upper */
118 u32 tx_undsz_l; /* Tx undersized packet lower */
119 u32 tx_undsz_u; /* Tx undersized packet upper */
120 u32 tx_64_l; /* Tx 64 oct packet lower */
121 u32 tx_64_u; /* Tx 64 oct packet upper */
122 u32 tx_127_l; /* Tx 65 to 127 oct packet lower */
123 u32 tx_127_u; /* Tx 65 to 127 oct packet upper */
124 u32 tx_255_l; /* Tx 128 to 255 oct packet lower */
125 u32 tx_255_u; /* Tx 128 to 255 oct packet upper */
126 u32 tx_511_l; /* Tx 256 to 511 oct packet lower */
127 u32 tx_511_u; /* Tx 256 to 511 oct packet upper */
128 u32 tx_1023_l; /* Tx 512 to 1023 oct packet lower */
129 u32 tx_1023_u; /* Tx 512 to 1023 oct packet upper */
130 u32 tx_1518_l; /* Tx 1024 to 1518 oct packet lower */
131 u32 tx_1518_u; /* Tx 1024 to 1518 oct packet upper */
132 u32 tx_1519_l; /* Tx 1519 to max oct packet lower */
133 u32 tx_1519_u; /* Tx 1519 to max oct packet upper */
134 u32 res_2a8[0x6];
135 u32 tx_cnp_l; /* Tx control packet lower */
136 u32 tx_cnp_u; /* Tx control packet upper */
137 u32 res_2c8[0xe];
138
139 /* Line interface control register */
140 u32 if_mode; /* interface mode control */
141 u32 if_status; /* interface status */
142 u32 res_308[0xe];
143
144 /* HiGig/2 Register */
145 u32 hg_config; /* HiGig2 control and configuration */
146 u32 res_344[0x3];
147 u32 hg_pause_quanta; /* HiGig2 pause quanta */
148 u32 res_354[0x3];
149 u32 hg_pause_thresh; /* HiGig2 pause quanta threshold */
150 u32 res_364[0x3];
151 u32 hgrx_pause_status; /* HiGig2 rx pause quanta status */
152 u32 hg_fifos_status; /* HiGig2 fifos status */
153 u32 rhm; /* Rx HiGig2 message counter register */
154 u32 thm;/* Tx HiGig2 message counter register */
155 u32 res_380[0x320];
156};
157
158/* COMMAND_CONFIG - command and configuration register */
159#define MEMAC_CMD_CFG_RX_EN 0x00000002 /* MAC Rx path enable */
160#define MEMAC_CMD_CFG_TX_EN 0x00000001 /* MAC Tx path enable */
161#define MEMAC_CMD_CFG_RXTX_EN (MEMAC_CMD_CFG_RX_EN | MEMAC_CMD_CFG_TX_EN)
Shaohui Xieff5fb2a2014-08-13 18:32:19 +0800162#define MEMAC_CMD_CFG_NO_LEN_CHK 0x20000 /* Payload length check disable */
Roy Zang111fd192012-10-08 07:44:21 +0000163
164/* HASHTABLE_CTRL - Hashtable control register */
165#define HASHTABLE_CTRL_MCAST_EN 0x00000200 /* enable mulitcast Rx hash */
166#define HASHTABLE_CTRL_ADDR_MASK 0x000001ff
167
168/* TX_IPG_LENGTH - Transmit inter-packet gap length register */
169#define TX_IPG_LENGTH_IPG_LEN_MASK 0x000003ff
170
171/* IMASK - interrupt mask register */
172#define IMASK_MDIO_SCAN_EVENT 0x00010000 /* MDIO scan event mask */
173#define IMASK_MDIO_CMD_CMPL 0x00008000 /* MDIO cmd completion mask */
174#define IMASK_REM_FAULT 0x00004000 /* remote fault mask */
175#define IMASK_LOC_FAULT 0x00002000 /* local fault mask */
176#define IMASK_TX_ECC_ER 0x00001000 /* Tx frame ECC error mask */
177#define IMASK_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow mask */
178#define IMASK_TX_ER 0x00000200 /* Tx frame error mask */
179#define IMASK_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow mask */
180#define IMASK_RX_ECC_ER 0x00000080 /* Rx frame ECC error mask */
181#define IMASK_RX_JAB_FRM 0x00000040 /* Rx jabber frame mask */
182#define IMASK_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame mask */
183#define IMASK_RX_RUNT_FRM 0x00000010 /* Rx runt frame mask */
184#define IMASK_RX_FRAG_FRM 0x00000008 /* Rx fragment frame mask */
185#define IMASK_RX_LEN_ER 0x00000004 /* Rx payload length error mask */
186#define IMASK_RX_CRC_ER 0x00000002 /* Rx CRC error mask */
187#define IMASK_RX_ALIGN_ER 0x00000001 /* Rx alignment error mask */
188
189#define IMASK_MASK_ALL 0x00000000
190
191/* IEVENT - interrupt event register */
192#define IEVENT_MDIO_SCAN_EVENT 0x00010000 /* MDIO scan event */
193#define IEVENT_MDIO_CMD_CMPL 0x00008000 /* MDIO cmd completion */
194#define IEVENT_REM_FAULT 0x00004000 /* remote fault */
195#define IEVENT_LOC_FAULT 0x00002000 /* local fault */
196#define IEVENT_TX_ECC_ER 0x00001000 /* Tx frame ECC error */
197#define IEVENT_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow */
198#define IEVENT_TX_ER 0x00000200 /* Tx frame error */
199#define IEVENT_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow */
200#define IEVENT_RX_ECC_ER 0x00000080 /* Rx frame ECC error */
201#define IEVENT_RX_JAB_FRM 0x00000040 /* Rx jabber frame */
202#define IEVENT_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame */
203#define IEVENT_RX_RUNT_FRM 0x00000010 /* Rx runt frame */
204#define IEVENT_RX_FRAG_FRM 0x00000008 /* Rx fragment frame */
205#define IEVENT_RX_LEN_ER 0x00000004 /* Rx payload length error */
206#define IEVENT_RX_CRC_ER 0x00000002 /* Rx CRC error */
207#define IEVENT_RX_ALIGN_ER 0x00000001 /* Rx alignment error */
208
209#define IEVENT_CLEAR_ALL 0xffffffff
210
211/* IF_MODE - Interface Mode Register */
212#define IF_MODE_EN_AUTO 0x00008000 /* 1 - Enable automatic speed selection */
Zang Roy-R61911c5729f02013-03-04 03:59:20 +0000213#define IF_MODE_SETSP_100M 0x00000000 /* 00 - 100Mbps RGMII */
214#define IF_MODE_SETSP_10M 0x00002000 /* 01 - 10Mbps RGMII */
215#define IF_MODE_SETSP_1000M 0x00004000 /* 10 - 1000Mbps RGMII */
216#define IF_MODE_SETSP_MASK 0x00006000 /* setsp mask bits */
Roy Zang111fd192012-10-08 07:44:21 +0000217#define IF_MODE_XGMII 0x00000000 /* 00- XGMII(10) interface mode */
218#define IF_MODE_GMII 0x00000002 /* 10- GMII interface mode */
219#define IF_MODE_MASK 0x00000003 /* mask for mode interface mode */
220#define IF_MODE_RG 0x00000004 /* 1- RGMII */
221#define IF_MODE_RM 0x00000008 /* 1- RGMII */
222
223#define IF_DEFAULT (IF_GMII)
224
225/* Internal PHY Registers - SGMII */
226#define PHY_SGMII_CR_PHY_RESET 0x8000
227#define PHY_SGMII_CR_RESET_AN 0x0200
228#define PHY_SGMII_CR_DEF_VAL 0x1140
229#define PHY_SGMII_DEV_ABILITY_SGMII 0x4001
230#define PHY_SGMII_IF_MODE_AN 0x0002
231#define PHY_SGMII_IF_MODE_SGMII 0x0001
232
233struct memac_mdio_controller {
234 u32 res0[0xc];
235 u32 mdio_stat; /* MDIO configuration and status */
236 u32 mdio_ctl; /* MDIO control */
237 u32 mdio_data; /* MDIO data */
238 u32 mdio_addr; /* MDIO address */
239};
240
241#define MDIO_STAT_CLKDIV(x) (((x>>1) & 0xff) << 8)
242#define MDIO_STAT_BSY (1 << 0)
243#define MDIO_STAT_RD_ER (1 << 1)
244#define MDIO_STAT_PRE (1 << 5)
245#define MDIO_STAT_ENC (1 << 6)
246#define MDIO_STAT_HOLD_15_CLK (7 << 2)
Shaohui Xieae6b4582014-08-13 18:38:09 +0800247#define MDIO_STAT_NEG (1 << 23)
Roy Zang111fd192012-10-08 07:44:21 +0000248
249#define MDIO_CTL_DEV_ADDR(x) (x & 0x1f)
250#define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5)
251#define MDIO_CTL_PRE_DIS (1 << 10)
252#define MDIO_CTL_SCAN_EN (1 << 11)
253#define MDIO_CTL_POST_INC (1 << 14)
254#define MDIO_CTL_READ (1 << 15)
255
256#define MDIO_DATA(x) (x & 0xffff)
257#define MDIO_DATA_BSY (1 << 31)
258
259struct fsl_enet_mac;
260
261void init_memac(struct fsl_enet_mac *mac, void *base, void *phyregs,
262 int max_rx_len);
263
264#endif