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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 6ba8b6a8f8d284bea437d51ab86b8d7b8ad80f9c / . / arch / arm / dts / fsl-ls1012a.dtsi
blob: c401ba33ac532689bbfca5dda48dc2951d868d59 [file] [log] [blame]
Tom Rini4549e782018-05-06 18:27:01 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR X11
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +0530[diff] [blame]2/*
Wasim Khan6ba8b6a2020-09-28 16:26:10 +0530[diff] [blame^]3 * Copyright 2020 NXP
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +0530[diff] [blame]4 * Copyright 2016 Freescale Semiconductor
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +0530[diff] [blame]5 */
6
7/include/ "skeleton64.dtsi"
8
9/ {
10 compatible = "fsl,ls1012a";
11 interrupt-parent = <&gic>;
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +0530[diff] [blame]12
13 sysclk: sysclk {
14 compatible = "fixed-clock";
15 #clock-cells = <0>;
16 clock-frequency = <100000000>;
17 clock-output-names = "sysclk";
18 };
19
20 gic: interrupt-controller@1400000 {
21 compatible = "arm,gic-400";
22 #interrupt-cells = <3>;
23 interrupt-controller;
24 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
25 <0x0 0x1402000 0 0x2000>, /* GICC */
26 <0x0 0x1404000 0 0x2000>, /* GICH */
27 <0x0 0x1406000 0 0x2000>; /* GICV */
28 interrupts = <1 9 0xf08>;
29 };
30
31 soc {
32 compatible = "simple-bus";
33 #address-cells = <2>;
34 #size-cells = <2>;
35 ranges;
36
37 clockgen: clocking@1ee1000 {
38 compatible = "fsl,ls1012a-clockgen";
39 reg = <0x0 0x1ee1000 0x0 0x1000>;
40 #clock-cells = <2>;
41 clocks = <&sysclk>;
42 };
43
44 dspi0: dspi@2100000 {
45 compatible = "fsl,vf610-dspi";
46 #address-cells = <1>;
47 #size-cells = <0>;
48 reg = <0x0 0x2100000 0x0 0x10000>;
49 interrupts = <0 64 0x4>;
50 clock-names = "dspi";
51 clocks = <&clockgen 4 0>;
52 num-cs = <6>;
53 big-endian;
54 status = "disabled";
55 };
56
Yangbo Lue1f39752016-12-07 11:54:32 +0800[diff] [blame]57 esdhc0: esdhc@1560000 {
58 compatible = "fsl,esdhc";
59 reg = <0x0 0x1560000 0x0 0x10000>;
60 interrupts = <0 62 0x4>;
61 big-endian;
62 bus-width = <4>;
63 };
64
65 esdhc1: esdhc@1580000 {
66 compatible = "fsl,esdhc";
67 reg = <0x0 0x1580000 0x0 0x10000>;
68 interrupts = <0 65 0x4>;
69 big-endian;
70 non-removable;
71 bus-width = <4>;
72 };
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +0530[diff] [blame]73
74 i2c0: i2c@2180000 {
75 compatible = "fsl,vf610-i2c";
76 #address-cells = <1>;
77 #size-cells = <0>;
78 reg = <0x0 0x2180000 0x0 0x10000>;
79 interrupts = <0 56 0x4>;
80 clock-names = "i2c";
81 clocks = <&clockgen 4 0>;
82 status = "disabled";
83 };
84
85 i2c1: i2c@2190000 {
86 compatible = "fsl,vf610-i2c";
87 #address-cells = <1>;
88 #size-cells = <0>;
89 reg = <0x0 0x2190000 0x0 0x10000>;
90 interrupts = <0 57 0x4>;
91 clock-names = "i2c";
92 clocks = <&clockgen 4 0>;
93 status = "disabled";
94 };
95
96 duart0: serial@21c0500 {
97 compatible = "fsl,ns16550", "ns16550a";
98 reg = <0x00 0x21c0500 0x0 0x100>;
99 interrupts = <0 54 0x4>;
100 clocks = <&clockgen 4 0>;
101 };
102
103 duart1: serial@21c0600 {
104 compatible = "fsl,ns16550", "ns16550a";
105 reg = <0x00 0x21c0600 0x0 0x100>;
106 interrupts = <0 54 0x4>;
107 clocks = <&clockgen 4 0>;
108 };
109
110 qspi: quadspi@1550000 {
Kuldeep Singhb480bcc2019-12-12 11:49:24 +0530[diff] [blame]111 compatible = "fsl,ls1021a-qspi";
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +0530[diff] [blame]112 #address-cells = <1>;
113 #size-cells = <0>;
114 reg = <0x0 0x1550000 0x0 0x10000>,
115 <0x0 0x40000000 0x0 0x4000000>;
116 reg-names = "QuadSPI", "QuadSPI-memory";
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +0530[diff] [blame]117 status = "disabled";
118 };
119
Wasim Khan6ba8b6a2020-09-28 16:26:10 +0530[diff] [blame^]120 pcie1: pcie@3400000 {
Minghuan Lian048a0452016-12-13 14:54:12 +0800[diff] [blame]121 compatible = "fsl,ls-pcie", "snps,dw-pcie";
122 reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
123 0x00 0x03480000 0x0 0x40000 /* lut registers */
124 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
125 0x40 0x00000000 0x0 0x20000>; /* configuration space */
126 reg-names = "dbi", "lut", "ctrl", "config";
127 big-endian;
128 #address-cells = <3>;
129 #size-cells = <2>;
130 device_type = "pci";
131 bus-range = <0x0 0xff>;
132 ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */
133 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
134 };
Tang Yuantiana7305872016-12-27 10:24:44 +0800[diff] [blame]135
Yuantian Tang86bff2b2018-07-13 17:25:29 +0800[diff] [blame]136 sata: sata@3200000 {
137 compatible = "fsl,ls1012a-ahci";
Peng Mae765ee52019-04-17 10:10:49 +0000[diff] [blame]138 reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
139 0x0 0x20140520 0x0 0x4>; /* ecc sata addr */
140 reg-names = "sata-base", "ecc-addr";
Yuantian Tang86bff2b2018-07-13 17:25:29 +0800[diff] [blame]141 interrupts = <0 69 4>;
142 clocks = <&clockgen 4 0>;
143 status = "disabled";
144 };
145
Tang Yuantiana7305872016-12-27 10:24:44 +0800[diff] [blame]146 usb0: usb2@8600000 {
147 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
148 reg = <0x0 0x8600000 0x0 0x1000>;
149 interrupts = <0 139 0x4>;
150 dr_mode = "host";
151 fsl,usb-erratum-a005697;
152 };
153
154 usb1: usb3@2f00000 {
155 compatible = "fsl,layerscape-dwc3";
156 reg = <0x0 0x2f00000 0x0 0x10000>;
157 interrupts = <0 61 0x4>;
158 dr_mode = "host";
159 };
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +0530[diff] [blame]160 };
161};