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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 6bb92fcf7d2fea2314d616e5e2391a8bf2b0fdfa / . / src / arm / renesas / r7s72100.dtsi
blob: e6d8da6faffb55763e84b6b97e683d49838fdc2d [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r7s72100 SoC
4 *
5 * Copyright (C) 2013-14 Renesas Solutions Corp.
6 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
7 */
8
9#include <dt-bindings/clock/r7s72100-clock.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12
13/ {
14 compatible = "renesas,r7s72100";
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 aliases {
19 i2c0 = &i2c0;
20 i2c1 = &i2c1;
21 i2c2 = &i2c2;
22 i2c3 = &i2c3;
23 spi0 = &spi0;
24 spi1 = &spi1;
25 spi2 = &spi2;
26 spi3 = &spi3;
27 spi4 = &spi4;
28 };
29
30 /* Fixed factor clocks */
31 b_clk: b {
32 #clock-cells = <0>;
33 compatible = "fixed-factor-clock";
34 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
35 clock-mult = <1>;
36 clock-div = <3>;
37 };
38
39 bsc: bsc {
40 compatible = "simple-bus";
41 #address-cells = <1>;
42 #size-cells = <1>;
43 ranges = <0 0 0x18000000>;
44 };
45
46 cpus {
47 #address-cells = <1>;
48 #size-cells = <0>;
49
50 cpu@0 {
51 device_type = "cpu";
52 compatible = "arm,cortex-a9";
53 reg = <0>;
54 clock-frequency = <400000000>;
55 clocks = <&cpg_clocks R7S72100_CLK_I>;
56 next-level-cache = <&L2>;
57 };
58 };
59
60 /* External clocks */
61 extal_clk: extal {
62 #clock-cells = <0>;
63 compatible = "fixed-clock";
64 /* If clk present, value must be set by board */
65 clock-frequency = <0>;
66 };
67
68 p0_clk: p0 {
69 #clock-cells = <0>;
70 compatible = "fixed-factor-clock";
71 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
72 clock-mult = <1>;
73 clock-div = <12>;
74 };
75
76 p1_clk: p1 {
77 #clock-cells = <0>;
78 compatible = "fixed-factor-clock";
79 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
80 clock-mult = <1>;
81 clock-div = <6>;
82 };
83
84 pmu {
85 compatible = "arm,cortex-a9-pmu";
86 interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
87 };
88
89 rtc_x1_clk: rtc_x1 {
90 #clock-cells = <0>;
91 compatible = "fixed-clock";
92 /* If clk present, value must be set by board to 32678 */
93 clock-frequency = <0>;
94 };
95
96 rtc_x3_clk: rtc_x3 {
97 #clock-cells = <0>;
98 compatible = "fixed-clock";
99 /* If clk present, value must be set by board to 4000000 */
100 clock-frequency = <0>;
101 };
102
103 soc {
104 compatible = "simple-bus";
105 interrupt-parent = <&gic>;
106
107 #address-cells = <1>;
108 #size-cells = <1>;
109 ranges;
110
111 L2: cache-controller@3ffff000 {
112 compatible = "arm,pl310-cache";
113 reg = <0x3ffff000 0x1000>;
114 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
115 arm,early-bresp-disable;
116 arm,full-line-zero-disable;
117 cache-unified;
118 cache-level = <2>;
119 };
120
121 scif0: serial@e8007000 {
122 compatible = "renesas,scif-r7s72100", "renesas,scif";
123 reg = <0xe8007000 64>;
124 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
126 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
127 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
128 clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
129 clock-names = "fck";
130 power-domains = <&cpg_clocks>;
131 status = "disabled";
132 };
133
134 scif1: serial@e8007800 {
135 compatible = "renesas,scif-r7s72100", "renesas,scif";
136 reg = <0xe8007800 64>;
137 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
138 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
139 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
141 clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
142 clock-names = "fck";
143 power-domains = <&cpg_clocks>;
144 status = "disabled";
145 };
146
147 scif2: serial@e8008000 {
148 compatible = "renesas,scif-r7s72100", "renesas,scif";
149 reg = <0xe8008000 64>;
150 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
154 clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
155 clock-names = "fck";
156 power-domains = <&cpg_clocks>;
157 status = "disabled";
158 };
159
160 scif3: serial@e8008800 {
161 compatible = "renesas,scif-r7s72100", "renesas,scif";
162 reg = <0xe8008800 64>;
163 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
167 clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
168 clock-names = "fck";
169 power-domains = <&cpg_clocks>;
170 status = "disabled";
171 };
172
173 scif4: serial@e8009000 {
174 compatible = "renesas,scif-r7s72100", "renesas,scif";
175 reg = <0xe8009000 64>;
176 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
180 clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
181 clock-names = "fck";
182 power-domains = <&cpg_clocks>;
183 status = "disabled";
184 };
185
186 scif5: serial@e8009800 {
187 compatible = "renesas,scif-r7s72100", "renesas,scif";
188 reg = <0xe8009800 64>;
189 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
193 clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
194 clock-names = "fck";
195 power-domains = <&cpg_clocks>;
196 status = "disabled";
197 };
198
199 scif6: serial@e800a000 {
200 compatible = "renesas,scif-r7s72100", "renesas,scif";
201 reg = <0xe800a000 64>;
202 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
206 clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
207 clock-names = "fck";
208 power-domains = <&cpg_clocks>;
209 status = "disabled";
210 };
211
212 scif7: serial@e800a800 {
213 compatible = "renesas,scif-r7s72100", "renesas,scif";
214 reg = <0xe800a800 64>;
215 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
220 clock-names = "fck";
221 power-domains = <&cpg_clocks>;
222 status = "disabled";
223 };
224
225 spi0: spi@e800c800 {
226 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
227 reg = <0xe800c800 0x24>;
228 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
231 interrupt-names = "error", "rx", "tx";
232 clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
233 power-domains = <&cpg_clocks>;
234 num-cs = <1>;
235 #address-cells = <1>;
236 #size-cells = <0>;
237 status = "disabled";
238 };
239
240 spi1: spi@e800d000 {
241 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
242 reg = <0xe800d000 0x24>;
243 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
245 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
246 interrupt-names = "error", "rx", "tx";
247 clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
248 power-domains = <&cpg_clocks>;
249 num-cs = <1>;
250 #address-cells = <1>;
251 #size-cells = <0>;
252 status = "disabled";
253 };
254
255 spi2: spi@e800d800 {
256 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
257 reg = <0xe800d800 0x24>;
258 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
259 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
260 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
261 interrupt-names = "error", "rx", "tx";
262 clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
263 power-domains = <&cpg_clocks>;
264 num-cs = <1>;
265 #address-cells = <1>;
266 #size-cells = <0>;
267 status = "disabled";
268 };
269
270 spi3: spi@e800e000 {
271 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
272 reg = <0xe800e000 0x24>;
273 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
276 interrupt-names = "error", "rx", "tx";
277 clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
278 power-domains = <&cpg_clocks>;
279 num-cs = <1>;
280 #address-cells = <1>;
281 #size-cells = <0>;
282 status = "disabled";
283 };
284
285 spi4: spi@e800e800 {
286 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
287 reg = <0xe800e800 0x24>;
288 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
291 interrupt-names = "error", "rx", "tx";
292 clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
293 power-domains = <&cpg_clocks>;
294 num-cs = <1>;
295 #address-cells = <1>;
296 #size-cells = <0>;
297 status = "disabled";
298 };
299
300 usbhs0: usb@e8010000 {
301 compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
302 reg = <0xe8010000 0x1a0>;
303 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&mstp7_clks R7S72100_CLK_USB0>;
305 renesas,buswait = <4>;
306 power-domains = <&cpg_clocks>;
307 status = "disabled";
308 };
309
310 usbhs1: usb@e8207000 {
311 compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
312 reg = <0xe8207000 0x1a0>;
313 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
314 clocks = <&mstp7_clks R7S72100_CLK_USB1>;
315 renesas,buswait = <4>;
316 power-domains = <&cpg_clocks>;
317 status = "disabled";
318 };
319
320 mmcif: mmc@e804c800 {
321 compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
322 reg = <0xe804c800 0x80>;
323 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
327 power-domains = <&cpg_clocks>;
328 reg-io-width = <4>;
329 bus-width = <8>;
330 status = "disabled";
331 };
332
333 sdhi0: mmc@e804e000 {
334 compatible = "renesas,sdhi-r7s72100";
335 reg = <0xe804e000 0x100>;
336 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
337 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
339
340 clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
341 <&mstp12_clks R7S72100_CLK_SDHI01>;
342 clock-names = "core", "cd";
343 power-domains = <&cpg_clocks>;
344 cap-sd-highspeed;
345 cap-sdio-irq;
346 status = "disabled";
347 };
348
349 sdhi1: mmc@e804e800 {
350 compatible = "renesas,sdhi-r7s72100";
351 reg = <0xe804e800 0x100>;
352 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
353 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
354 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
355
356 clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
357 <&mstp12_clks R7S72100_CLK_SDHI11>;
358 clock-names = "core", "cd";
359 power-domains = <&cpg_clocks>;
360 cap-sd-highspeed;
361 cap-sdio-irq;
362 status = "disabled";
363 };
364
365 gic: interrupt-controller@e8201000 {
366 compatible = "arm,pl390";
367 #interrupt-cells = <3>;
368 #address-cells = <0>;
369 interrupt-controller;
370 reg = <0xe8201000 0x1000>,
371 <0xe8202000 0x1000>;
372 };
373
374 ether: ethernet@e8203000 {
375 compatible = "renesas,ether-r7s72100";
376 reg = <0xe8203000 0x800>,
377 <0xe8204800 0x200>;
378 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
380 power-domains = <&cpg_clocks>;
381 phy-mode = "mii";
382 #address-cells = <1>;
383 #size-cells = <0>;
384 status = "disabled";
385 };
386
387 ceu: camera@e8210000 {
388 reg = <0xe8210000 0x3000>;
389 compatible = "renesas,r7s72100-ceu";
390 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&mstp6_clks R7S72100_CLK_CEU>;
392 power-domains = <&cpg_clocks>;
393 status = "disabled";
394 };
395
396 wdt: watchdog@fcfe0000 {
397 compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
398 reg = <0xfcfe0000 0x6>;
399 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&p0_clk>;
401 };
402
403 /* Special CPG clocks */
404 cpg_clocks: cpg_clocks@fcfe0000 {
405 #clock-cells = <1>;
406 compatible = "renesas,r7s72100-cpg-clocks",
407 "renesas,rz-cpg-clocks";
408 reg = <0xfcfe0000 0x18>;
409 clocks = <&extal_clk>, <&usb_x1_clk>;
410 clock-output-names = "pll", "i", "g";
411 #power-domain-cells = <0>;
412 };
413
414 /* MSTP clocks */
415 mstp3_clks: mstp3_clks@fcfe0420 {
416 #clock-cells = <1>;
417 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
418 reg = <0xfcfe0420 4>;
419 clocks = <&p0_clk>;
420 clock-indices = <R7S72100_CLK_MTU2>;
421 clock-output-names = "mtu2";
422 };
423
424 mstp4_clks: mstp4_clks@fcfe0424 {
425 #clock-cells = <1>;
426 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
427 reg = <0xfcfe0424 4>;
428 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
429 <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
430 clock-indices = <
431 R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3
432 R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7
433 >;
434 clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
435 };
436
437 mstp5_clks: mstp5_clks@fcfe0428 {
438 #clock-cells = <1>;
439 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
440 reg = <0xfcfe0428 4>;
441 clocks = <&p0_clk>, <&p0_clk>;
442 clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>;
443 clock-output-names = "ostm0", "ostm1";
444 };
445
446 mstp6_clks: mstp6_clks@fcfe042c {
447 #clock-cells = <1>;
448 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
449 reg = <0xfcfe042c 4>;
450 clocks = <&b_clk>, <&p0_clk>;
451 clock-indices = <R7S72100_CLK_CEU R7S72100_CLK_RTC>;
452 clock-output-names = "ceu", "rtc";
453 };
454
455 mstp7_clks: mstp7_clks@fcfe0430 {
456 #clock-cells = <1>;
457 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
458 reg = <0xfcfe0430 4>;
459 clocks = <&b_clk>, <&p1_clk>, <&p1_clk>;
460 clock-indices = <R7S72100_CLK_ETHER R7S72100_CLK_USB0 R7S72100_CLK_USB1>;
461 clock-output-names = "ether", "usb0", "usb1";
462 };
463
464 mstp8_clks: mstp8_clks@fcfe0434 {
465 #clock-cells = <1>;
466 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
467 reg = <0xfcfe0434 4>;
468 clocks = <&p1_clk>;
469 clock-indices = <R7S72100_CLK_MMCIF>;
470 clock-output-names = "mmcif";
471 };
472
473 mstp9_clks: mstp9_clks@fcfe0438 {
474 #clock-cells = <1>;
475 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
476 reg = <0xfcfe0438 4>;
477 clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>, <&b_clk>, <&b_clk>;
478 clock-indices = <
479 R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
480 R7S72100_CLK_SPIBSC0 R7S72100_CLK_SPIBSC1
481 >;
482 clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3", "spibsc0", "spibsc1";
483 };
484
485 mstp10_clks: mstp10_clks@fcfe043c {
486 #clock-cells = <1>;
487 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
488 reg = <0xfcfe043c 4>;
489 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
490 <&p1_clk>;
491 clock-indices = <
492 R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3
493 R7S72100_CLK_SPI4
494 >;
495 clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";
496 };
497 mstp12_clks: mstp12_clks@fcfe0444 {
498 #clock-cells = <1>;
499 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
500 reg = <0xfcfe0444 4>;
501 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
502 clock-indices = <
503 R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01
504 R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11
505 >;
506 clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
507 };
508
509 pinctrl: pinctrl@fcfe3000 {
510 compatible = "renesas,r7s72100-ports";
511
512 reg = <0xfcfe3000 0x4230>;
513
514 port0: gpio-0 {
515 gpio-controller;
516 #gpio-cells = <2>;
517 gpio-ranges = <&pinctrl 0 0 6>;
518 };
519
520 port1: gpio-1 {
521 gpio-controller;
522 #gpio-cells = <2>;
523 gpio-ranges = <&pinctrl 0 16 16>;
524 };
525
526 port2: gpio-2 {
527 gpio-controller;
528 #gpio-cells = <2>;
529 gpio-ranges = <&pinctrl 0 32 16>;
530 };
531
532 port3: gpio-3 {
533 gpio-controller;
534 #gpio-cells = <2>;
535 gpio-ranges = <&pinctrl 0 48 16>;
536 };
537
538 port4: gpio-4 {
539 gpio-controller;
540 #gpio-cells = <2>;
541 gpio-ranges = <&pinctrl 0 64 16>;
542 };
543
544 port5: gpio-5 {
545 gpio-controller;
546 #gpio-cells = <2>;
547 gpio-ranges = <&pinctrl 0 80 11>;
548 };
549
550 port6: gpio-6 {
551 gpio-controller;
552 #gpio-cells = <2>;
553 gpio-ranges = <&pinctrl 0 96 16>;
554 };
555
556 port7: gpio-7 {
557 gpio-controller;
558 #gpio-cells = <2>;
559 gpio-ranges = <&pinctrl 0 112 16>;
560 };
561
562 port8: gpio-8 {
563 gpio-controller;
564 #gpio-cells = <2>;
565 gpio-ranges = <&pinctrl 0 128 16>;
566 };
567
568 port9: gpio-9 {
569 gpio-controller;
570 #gpio-cells = <2>;
571 gpio-ranges = <&pinctrl 0 144 8>;
572 };
573
574 port10: gpio-10 {
575 gpio-controller;
576 #gpio-cells = <2>;
577 gpio-ranges = <&pinctrl 0 160 16>;
578 };
579
580 port11: gpio-11 {
581 gpio-controller;
582 #gpio-cells = <2>;
583 gpio-ranges = <&pinctrl 0 176 16>;
584 };
585 };
586
587 ostm0: timer@fcfec000 {
588 compatible = "renesas,r7s72100-ostm", "renesas,ostm";
589 reg = <0xfcfec000 0x30>;
590 interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
591 clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
592 power-domains = <&cpg_clocks>;
593 status = "disabled";
594 };
595
596 ostm1: timer@fcfec400 {
597 compatible = "renesas,r7s72100-ostm", "renesas,ostm";
598 reg = <0xfcfec400 0x30>;
599 interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;
600 clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;
601 power-domains = <&cpg_clocks>;
602 status = "disabled";
603 };
604
605 i2c0: i2c@fcfee000 {
606 #address-cells = <1>;
607 #size-cells = <0>;
608 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
609 reg = <0xfcfee000 0x44>;
610 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
612 <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
613 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
615 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
616 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
617 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
618 interrupt-names = "tei", "ri", "ti", "spi", "sti",
619 "naki", "ali", "tmoi";
620 clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
621 clock-frequency = <100000>;
622 power-domains = <&cpg_clocks>;
623 status = "disabled";
624 };
625
626 i2c1: i2c@fcfee400 {
627 #address-cells = <1>;
628 #size-cells = <0>;
629 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
630 reg = <0xfcfee400 0x44>;
631 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
632 <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
633 <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
634 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
635 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
636 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
637 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
638 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
639 interrupt-names = "tei", "ri", "ti", "spi", "sti",
640 "naki", "ali", "tmoi";
641 clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
642 clock-frequency = <100000>;
643 power-domains = <&cpg_clocks>;
644 status = "disabled";
645 };
646
647 i2c2: i2c@fcfee800 {
648 #address-cells = <1>;
649 #size-cells = <0>;
650 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
651 reg = <0xfcfee800 0x44>;
652 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
653 <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
654 <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
655 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
656 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
657 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
658 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
659 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
660 interrupt-names = "tei", "ri", "ti", "spi", "sti",
661 "naki", "ali", "tmoi";
662 clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
663 clock-frequency = <100000>;
664 power-domains = <&cpg_clocks>;
665 status = "disabled";
666 };
667
668 i2c3: i2c@fcfeec00 {
669 #address-cells = <1>;
670 #size-cells = <0>;
671 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
672 reg = <0xfcfeec00 0x44>;
673 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
674 <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
675 <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
676 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
677 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
678 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
679 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
680 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
681 interrupt-names = "tei", "ri", "ti", "spi", "sti",
682 "naki", "ali", "tmoi";
683 clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
684 clock-frequency = <100000>;
685 power-domains = <&cpg_clocks>;
686 status = "disabled";
687 };
688
689 irqc: interrupt-controller@fcfef800 {
690 compatible = "renesas,r7s72100-irqc",
691 "renesas,rza1-irqc";
692 #interrupt-cells = <2>;
693 #address-cells = <0>;
694 interrupt-controller;
695 reg = <0xfcfef800 0x6>;
696 interrupt-map =
697 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
698 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
699 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
700 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
701 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
702 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
703 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
704 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
705 interrupt-map-mask = <7 0>;
706 };
707
708 mtu2: timer@fcff0000 {
709 compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
710 reg = <0xfcff0000 0x400>;
711 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
712 interrupt-names = "tgi0a";
713 clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
714 clock-names = "fck";
715 power-domains = <&cpg_clocks>;
716 status = "disabled";
717 };
718
719 rtc: rtc@fcff1000 {
720 compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc";
721 reg = <0xfcff1000 0x2e>;
722 interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
723 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
724 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
725 interrupt-names = "alarm", "period", "carry";
726 clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>,
727 <&rtc_x3_clk>, <&extal_clk>;
728 clock-names = "fck", "rtc_x1", "rtc_x3", "extal";
729 power-domains = <&cpg_clocks>;
730 status = "disabled";
731 };
732 };
733
734 usb_x1_clk: usb_x1 {
735 #clock-cells = <0>;
736 compatible = "fixed-clock";
737 /* If clk present, value must be set by board */
738 clock-frequency = <0>;
739 };
740};