src/arm/ti/omap/am35xx-clocks.dtsi

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Device Tree Source for OMAP3 clock data
 *
 * Copyright (C) 2013 Texas Instruments, Inc.
 */
&scm_clocks {
	emac_ick: emac_ick@32c {
		#clock-cells = <0>;
		compatible = "ti,am35xx-gate-clock";
		clocks = <&ipss_ick>;
		reg = <0x032c>;
		ti,bit-shift = <1>;
	};

	emac_fck: emac_fck@32c {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&rmii_ck>;
		reg = <0x032c>;
		ti,bit-shift = <9>;
	};

	vpfe_ick: vpfe_ick@32c {
		#clock-cells = <0>;
		compatible = "ti,am35xx-gate-clock";
		clocks = <&ipss_ick>;
		reg = <0x032c>;
		ti,bit-shift = <2>;
	};

	vpfe_fck: vpfe_fck@32c {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&pclk_ck>;
		reg = <0x032c>;
		ti,bit-shift = <10>;
	};

	hsotgusb_ick_am35xx: hsotgusb_ick_am35xx@32c {
		#clock-cells = <0>;
		compatible = "ti,am35xx-gate-clock";
		clocks = <&ipss_ick>;
		reg = <0x032c>;
		ti,bit-shift = <0>;
	};

	hsotgusb_fck_am35xx: hsotgusb_fck_am35xx@32c {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&sys_ck>;
		reg = <0x032c>;
		ti,bit-shift = <8>;
	};

	hecc_ck: hecc_ck@32c {
		#clock-cells = <0>;
		compatible = "ti,am35xx-gate-clock";
		clocks = <&sys_ck>;
		reg = <0x032c>;
		ti,bit-shift = <3>;
	};
};
&cm_clocks {
	clock@a10 {
		compatible = "ti,clksel";
		reg = <0xa10>;
		#clock-cells = <2>;
		#address-cells = <1>;
		#size-cells = <0>;

		ipss_ick: clock-ipss-ick@4 {
			reg = <4>;
			#clock-cells = <0>;
			compatible = "ti,am35xx-interface-clock";
			clock-output-names = "ipss_ick";
			clocks = <&core_l3_ick>;
		};

		uart4_ick_am35xx: clock-uart4-ick-am35xx@23 {
			reg = <23>;
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "uart4_ick_am35xx";
			clocks = <&core_l4_ick>;
		};
	};

	rmii_ck: rmii_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <50000000>;
	};

	pclk_ck: pclk_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <27000000>;
	};

	clock@a00 {
		compatible = "ti,clksel";
		reg = <0xa00>;
		#clock-cells = <2>;
		#address-cells = <1>;
		#size-cells = <0>;

		uart4_fck_am35xx: clock-uart4-fck-am35xx@23 {
			reg = <23>;
			#clock-cells = <0>;
			compatible = "ti,wait-gate-clock";
			clock-output-names = "uart4_fck_am35xx";
			clocks = <&core_48m_fck>;
		};
	};
};

&cm_clockdomains {
	core_l3_clkdm: core_l3_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&sdrc_ick>, <&ipss_ick>, <&emac_ick>, <&vpfe_ick>,
			 <&hsotgusb_ick_am35xx>, <&hsotgusb_fck_am35xx>,
			 <&hecc_ck>;
	};

	core_l4_clkdm: core_l4_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
			 <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
			 <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
			 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
			 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
			 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
			 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
			 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
			 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
			 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
			 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
			 <&uart4_ick_am35xx>, <&uart4_fck_am35xx>;
	};
};