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Bill Richardson55ae10f2012-10-20 11:44:34 +00001/*
2 * Copyright (c) 2012, Google Inc. All rights reserved.
Simon Glass1b4f25f2014-11-12 22:42:24 -07003 * SPDX-License-Identifier: GPL-2.0
Bill Richardson55ae10f2012-10-20 11:44:34 +00004 */
5
6#ifndef _X86_GPIO_H_
7#define _X86_GPIO_H_
8
Simon Glass1b4f25f2014-11-12 22:42:24 -07009#include <linux/compiler.h>
Simon Glassc15b0b82014-10-10 07:49:17 -060010#include <asm/arch/gpio.h>
Bill Richardson55ae10f2012-10-20 11:44:34 +000011#include <asm-generic/gpio.h>
12
Simon Glass1b4f25f2014-11-12 22:42:24 -070013struct ich6_bank_platdata {
Bin Mengb71eec32014-12-17 15:50:38 +080014 uint16_t base_addr;
Simon Glass1b4f25f2014-11-12 22:42:24 -070015 const char *bank_name;
16};
17
18#define GPIO_MODE_NATIVE 0
19#define GPIO_MODE_GPIO 1
20#define GPIO_MODE_NONE 1
21
22#define GPIO_DIR_OUTPUT 0
23#define GPIO_DIR_INPUT 1
24
25#define GPIO_NO_INVERT 0
26#define GPIO_INVERT 1
27
28#define GPIO_LEVEL_LOW 0
29#define GPIO_LEVEL_HIGH 1
30
31#define GPIO_NO_BLINK 0
32#define GPIO_BLINK 1
33
34#define GPIO_RESET_PWROK 0
35#define GPIO_RESET_RSMRST 1
36
37struct pch_gpio_set1 {
38 u32 gpio0:1;
39 u32 gpio1:1;
40 u32 gpio2:1;
41 u32 gpio3:1;
42 u32 gpio4:1;
43 u32 gpio5:1;
44 u32 gpio6:1;
45 u32 gpio7:1;
46 u32 gpio8:1;
47 u32 gpio9:1;
48 u32 gpio10:1;
49 u32 gpio11:1;
50 u32 gpio12:1;
51 u32 gpio13:1;
52 u32 gpio14:1;
53 u32 gpio15:1;
54 u32 gpio16:1;
55 u32 gpio17:1;
56 u32 gpio18:1;
57 u32 gpio19:1;
58 u32 gpio20:1;
59 u32 gpio21:1;
60 u32 gpio22:1;
61 u32 gpio23:1;
62 u32 gpio24:1;
63 u32 gpio25:1;
64 u32 gpio26:1;
65 u32 gpio27:1;
66 u32 gpio28:1;
67 u32 gpio29:1;
68 u32 gpio30:1;
69 u32 gpio31:1;
70} __packed;
71
72struct pch_gpio_set2 {
73 u32 gpio32:1;
74 u32 gpio33:1;
75 u32 gpio34:1;
76 u32 gpio35:1;
77 u32 gpio36:1;
78 u32 gpio37:1;
79 u32 gpio38:1;
80 u32 gpio39:1;
81 u32 gpio40:1;
82 u32 gpio41:1;
83 u32 gpio42:1;
84 u32 gpio43:1;
85 u32 gpio44:1;
86 u32 gpio45:1;
87 u32 gpio46:1;
88 u32 gpio47:1;
89 u32 gpio48:1;
90 u32 gpio49:1;
91 u32 gpio50:1;
92 u32 gpio51:1;
93 u32 gpio52:1;
94 u32 gpio53:1;
95 u32 gpio54:1;
96 u32 gpio55:1;
97 u32 gpio56:1;
98 u32 gpio57:1;
99 u32 gpio58:1;
100 u32 gpio59:1;
101 u32 gpio60:1;
102 u32 gpio61:1;
103 u32 gpio62:1;
104 u32 gpio63:1;
105} __packed;
106
107struct pch_gpio_set3 {
108 u32 gpio64:1;
109 u32 gpio65:1;
110 u32 gpio66:1;
111 u32 gpio67:1;
112 u32 gpio68:1;
113 u32 gpio69:1;
114 u32 gpio70:1;
115 u32 gpio71:1;
116 u32 gpio72:1;
117 u32 gpio73:1;
118 u32 gpio74:1;
119 u32 gpio75:1;
120} __packed;
121
122/*
123 * This hilariously complex structure came from Coreboot. The
124 * setup_pch_gpios() function uses it. It could be move to device tree, or
125 * adjust to use masks instead of bitfields.
126 */
127struct pch_gpio_map {
128 struct {
129 const struct pch_gpio_set1 *mode;
130 const struct pch_gpio_set1 *direction;
131 const struct pch_gpio_set1 *level;
132 const struct pch_gpio_set1 *reset;
133 const struct pch_gpio_set1 *invert;
134 const struct pch_gpio_set1 *blink;
135 } set1;
136 struct {
137 const struct pch_gpio_set2 *mode;
138 const struct pch_gpio_set2 *direction;
139 const struct pch_gpio_set2 *level;
140 const struct pch_gpio_set2 *reset;
141 } set2;
142 struct {
143 const struct pch_gpio_set3 *mode;
144 const struct pch_gpio_set3 *direction;
145 const struct pch_gpio_set3 *level;
146 const struct pch_gpio_set3 *reset;
147 } set3;
148};
149
Gabriel Huau5318f182015-05-25 22:27:37 -0700150int gpio_ich6_pinctrl_init(void);
Bin Mengb71eec32014-12-17 15:50:38 +0800151void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
Simon Glass1b4f25f2014-11-12 22:42:24 -0700152void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
153
Bill Richardson55ae10f2012-10-20 11:44:34 +0000154#endif /* _X86_GPIO_H_ */