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wdenkfe8c2802002-11-03 00:38:21 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * Changes for MATRIX Vision MVsensor (C) Copyright 2001
6 * MATRIX Vision GmbH / hg, info@matrix-vision.de
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <mpc8xx.h>
29
30/* ------------------------------------------------------------------------- */
31
32static long int dram_size (long int, long int *, long int);
33
34/* ------------------------------------------------------------------------- */
35
36#define _NOT_USED_ 0xFFFFFFFF
37
38const uint sdram_table[] =
39{
40 /*
41 * Single Read. (Offset 0 in UPMA RAM)
42 */
43 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
44 0x1FF5FC47, /* last */
45 /*
46 * SDRAM Initialization (offset 5 in UPMA RAM)
47 *
48 * This is no UPM entry point. The following definition uses
49 * the remaining space to establish an initialization
50 * sequence, which is executed by a RUN command.
51 *
52 */
53 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
54 /*
55 * Burst Read. (Offset 8 in UPMA RAM)
56 */
57 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
58 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
59 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
60 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
61 /*
62 * Single Write. (Offset 18 in UPMA RAM)
63 */
64 0x1F0DFC04 /*0x1F2DFC04??*/, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
65 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
66 /*
67 * Burst Write. (Offset 20 in UPMA RAM)
68 */
69 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
70 0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */
71 _NOT_USED_,
72 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
73 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
74 /*
75 * Refresh (Offset 30 in UPMA RAM)
76 */
77 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
78 0xFFFFFC84, 0xFFFFFC07, /* last */
79 _NOT_USED_, _NOT_USED_,
80 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
81 /*
82 * Exception. (Offset 3c in UPMA RAM)
83 */
84 0x7FFFFC07, /* last */
85 _NOT_USED_, _NOT_USED_, _NOT_USED_,
86};
87
88/* ------------------------------------------------------------------------- */
89
90
91/*
92 * Check Board Identity:
93 */
94
95int checkboard (void)
96{
97 puts ("Board: MATRIX Vision MVsensor\n");
98 return 0;
99}
100
101
wdenkfe8c2802002-11-03 00:38:21 +0000102#ifdef DO_RAM_TEST
103/* ------------------------------------------------------------------------- */
104
105/*
106 * Test SDRAM by writing its address to itself and reading several times
107*/
108#define READ_RUNS 4
109static void test_dram (unsigned long *start, unsigned long *end)
110{
111 unsigned long *addr;
112 unsigned long value;
113 int read_runs, errors, addr_errors;
114
115 printf ("\nChecking SDRAM from %p to %p\n", start, end);
116 udelay (1000000);
117 for (addr = start; addr < end; addr++)
118 *addr = (unsigned long) addr;
119
120 for (addr = start, addr_errors = 0; addr < end; addr++) {
121 for (read_runs = READ_RUNS, errors = 0; read_runs > 0; read_runs--) {
122 if ((value = *addr) != (unsigned long) addr)
123 errors++;
124 }
125 if (errors > 0) {
126 addr_errors++;
127 printf ("SDRAM errors (%d) at %p, last read = %ld\n",
128 errors, addr, value);
129 udelay (10000);
130 }
131 }
132 printf ("SDRAM check finished, total errors = %d\n", addr_errors);
133}
134#endif /* DO_RAM_TEST */
135
136
137/* ------------------------------------------------------------------------- */
138
139long int initdram (int board_type)
140{
141 volatile immap_t *immap = (immap_t *) CFG_IMMR;
142 volatile memctl8xx_t *memctl = &immap->im_memctl;
143 long int size_b0, size_b1, size8, size9;
144
145 upmconfig (UPMA, (uint *) sdram_table,
146 sizeof (sdram_table) / sizeof (uint));
147
148 /*
149 * Preliminary prescaler for refresh (depends on number of
150 * banks): This value is selected for four cycles every 62.4 us
151 * with two SDRAM banks or four cycles every 31.2 us with one
152 * bank. It will be adjusted after memory sizing.
153 */
154 memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
155
156 memctl->memc_mar = 0x00000088;
157
158 /*
159 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
160 * preliminary addresses - these have to be modified after the
161 * SDRAM size has been determined.
162 */
163 memctl->memc_or2 = CFG_OR2_PRELIM;
164 memctl->memc_br2 = CFG_BR2_PRELIM;
165
166#if defined (CFG_OR3_PRELIM) && defined (CFG_BR3_PRELIM)
167 if (board_type == 0) { /* "L" type boards have only one bank SDRAM */
168 memctl->memc_or3 = CFG_OR3_PRELIM;
169 memctl->memc_br3 = CFG_BR3_PRELIM;
170 }
171#endif
172
173 memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
174
175 udelay (200);
176
177 /* perform SDRAM initializsation sequence */
178
179 memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
180 udelay (1);
181 memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
182 udelay (1);
183
184 if (board_type == 0) { /* "L" type boards have only one bank SDRAM */
185 memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
186 udelay (1);
187 memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */
188 udelay (1);
189 }
190
191 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
192
193 udelay (1000);
194
195 /*
196 * Check Bank 0 Memory Size for re-configuration
197 *
198 * try 8 column mode
199 */
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200200 size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM,
wdenkfe8c2802002-11-03 00:38:21 +0000201 SDRAM_MAX_SIZE);
202
203 udelay (1000);
204 /*
205 * try 9 column mode
206 */
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200207 size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM,
wdenkfe8c2802002-11-03 00:38:21 +0000208 SDRAM_MAX_SIZE);
209
210 if (size8 < size9) { /* leave configuration at 9 columns */
211 size_b0 = size9;
212 } else { /* back to 8 columns */
213 size_b0 = size8;
214 memctl->memc_mamr = CFG_MAMR_8COL;
215 udelay (500);
216 }
217
218 if (board_type == 0) { /* "L" type boards have only one bank SDRAM */
219 /*
220 * Check Bank 1 Memory Size
221 * use current column settings
222 * [9 column SDRAM may also be used in 8 column mode,
223 * but then only half the real size will be used.]
224 */
225#if defined (SDRAM_BASE3_PRELIM)
226 size_b1 =
227 dram_size (memctl->memc_mamr, (ulong *) SDRAM_BASE3_PRELIM,
228 SDRAM_MAX_SIZE);
229#else
230 size_b1 = 0;
231#endif
232 } else {
233 size_b1 = 0;
234 }
235
236 udelay (1000);
237
238 /*
239 * Adjust refresh rate depending on SDRAM type, both banks
240 * For types > 128 MBit leave it at the current (fast) rate
241 */
242 if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
243 /* reduce to 15.6 us (62.4 us / quad) */
244 memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
245 udelay (1000);
246 }
247
248 /*
249 * Final mapping: map bigger bank first
250 */
251 if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
252
253 memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
254 memctl->memc_br3 =
255 (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
256
257 if (size_b0 > 0) {
258 /*
259 * Position Bank 0 immediately above Bank 1
260 */
261 memctl->memc_or2 =
262 ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
263 memctl->memc_br2 =
264 ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
265 + size_b1;
266 } else {
267 unsigned long reg;
268
269 /*
270 * No bank 0
271 *
272 * invalidate bank
273 */
274 memctl->memc_br2 = 0;
275
276 /* adjust refresh rate depending on SDRAM type, one bank */
277 reg = memctl->memc_mptpr;
278 reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
279 memctl->memc_mptpr = reg;
280 }
281
282 } else { /* SDRAM Bank 0 is bigger - map first */
283
284 memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
285 memctl->memc_br2 =
286 (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
287
288 if (size_b1 > 0) {
289 /*
290 * Position Bank 1 immediately above Bank 0
291 */
292 memctl->memc_or3 =
293 ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
294 memctl->memc_br3 =
295 ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
296 + size_b0;
297 } else {
298 unsigned long reg;
299
300 /*
301 * No bank 1
302 *
303 * invalidate bank
304 */
305 memctl->memc_br3 = 0;
306
307 /* adjust refresh rate depending on SDRAM type, one bank */
308 reg = memctl->memc_mptpr;
309 reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
310 memctl->memc_mptpr = reg;
311 }
312 }
313
314 udelay (10000);
315
316#ifdef DO_RAM_TEST
317 if (size_b0 > 0)
318 test_dram ((unsigned long *) CFG_SDRAM_BASE,
319 (unsigned long *) (CFG_SDRAM_BASE + size_b0));
320#endif
321
322 return (size_b0 + size_b1);
323}
324
325/* ------------------------------------------------------------------------- */
326
327/*
328 * Check memory range for valid RAM. A simple memory test determines
329 * the actually available RAM size between addresses `base' and
330 * `base + maxsize'. Some (not all) hardware errors are detected:
331 * - short between address lines
332 * - short between data lines
333 */
334
335static long int dram_size (long int mamr_value, long int *base,
336 long int maxsize)
337{
338 volatile immap_t *immap = (immap_t *) CFG_IMMR;
339 volatile memctl8xx_t *memctl = &immap->im_memctl;
wdenkfe8c2802002-11-03 00:38:21 +0000340
341 memctl->memc_mamr = mamr_value;
342
wdenkc83bf6a2004-01-06 22:38:14 +0000343 return (get_ram_size(base, maxsize));
wdenkfe8c2802002-11-03 00:38:21 +0000344}
345
346
347/* ------------------------------------------------------------------------- */
348
349u8 *dhcp_vendorex_prep (u8 * e)
350{
351 char *ptr;
352
353/* DHCP vendor-class-identifier = 60 */
354 if ((ptr = getenv ("dhcp_vendor-class-identifier"))) {
355 *e++ = 60;
356 *e++ = strlen (ptr);
357 while (*ptr)
358 *e++ = *ptr++;
359 }
360/* my DHCP_CLIENT_IDENTIFIER = 61 */
361 if ((ptr = getenv ("dhcp_client_id"))) {
362 *e++ = 61;
363 *e++ = strlen (ptr);
364 while (*ptr)
365 *e++ = *ptr++;
366 }
367
368 return e;
369}
370
371
372/* ------------------------------------------------------------------------- */
373u8 *dhcp_vendorex_proc (u8 * popt)
374{
375 return NULL;
376}