Tim Schendekehl | 14c3261 | 2011-11-01 23:55:01 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2011 |
| 3 | * egnite GmbH <info@egnite.de> |
| 4 | * |
| 5 | * Configuation settings for Ethernut 5 with AT91SAM9XE. |
| 6 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 7 | * SPDX-License-Identifier: GPL-2.0+ |
Tim Schendekehl | 14c3261 | 2011-11-01 23:55:01 +0000 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef __CONFIG_H |
| 11 | #define __CONFIG_H |
| 12 | |
| 13 | #include <asm/hardware.h> |
| 14 | |
Tim Schendekehl | 6dbeb89 | 2014-06-12 17:25:36 +0200 | [diff] [blame] | 15 | #define CONFIG_SYS_GENERIC_BOARD |
| 16 | |
Tim Schendekehl | 14c3261 | 2011-11-01 23:55:01 +0000 | [diff] [blame] | 17 | /* The first stage boot loader expects u-boot running at this address. */ |
| 18 | #define CONFIG_SYS_TEXT_BASE 0x27000000 /* 16MB available */ |
| 19 | |
| 20 | /* The first stage boot loader takes care of low level initialization. */ |
| 21 | #define CONFIG_SKIP_LOWLEVEL_INIT |
| 22 | |
| 23 | /* Set our official architecture number. */ |
| 24 | #define MACH_TYPE_ETHERNUT5 1971 |
| 25 | #define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5 |
| 26 | |
| 27 | /* CPU information */ |
Tim Schendekehl | 14c3261 | 2011-11-01 23:55:01 +0000 | [diff] [blame] | 28 | #define CONFIG_DISPLAY_CPUINFO /* Display at console. */ |
| 29 | #define CONFIG_ARCH_CPU_INIT |
| 30 | |
| 31 | /* ARM asynchronous clock */ |
| 32 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ |
| 33 | #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ |
Tim Schendekehl | 14c3261 | 2011-11-01 23:55:01 +0000 | [diff] [blame] | 34 | |
| 35 | /* 32kB internal SRAM */ |
| 36 | #define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */ |
| 37 | #define CONFIG_SRAM_SIZE (32 << 10) |
Rob Herring | 3d6ba91 | 2012-07-13 09:44:01 +0000 | [diff] [blame] | 38 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \ |
| 39 | GENERATED_GBL_DATA_SIZE) |
Tim Schendekehl | 14c3261 | 2011-11-01 23:55:01 +0000 | [diff] [blame] | 40 | |
| 41 | /* 128MB SDRAM in 1 bank */ |
| 42 | #define CONFIG_NR_DRAM_BANKS 1 |
| 43 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 |
| 44 | #define CONFIG_SYS_SDRAM_SIZE (128 << 20) |
| 45 | #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE |
| 46 | #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR |
| 47 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) |
| 48 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE |
| 49 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE \ |
| 50 | - CONFIG_SYS_MALLOC_LEN) |
| 51 | |
| 52 | /* 512kB on-chip NOR flash */ |
| 53 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| 54 | # define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */ |
| 55 | # define CONFIG_AT91_EFLASH |
| 56 | # define CONFIG_SYS_MAX_FLASH_SECT 32 |
| 57 | # define CONFIG_SYS_FLASH_PROTECTION /* First stage loader in sector 0 */ |
| 58 | # define CONFIG_EFLASH_PROTSECTORS 1 |
| 59 | |
| 60 | /* 512kB DataFlash at NPCS0 */ |
| 61 | #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 |
| 62 | #define CONFIG_HAS_DATAFLASH |
Tim Schendekehl | 14c3261 | 2011-11-01 23:55:01 +0000 | [diff] [blame] | 63 | #define CONFIG_SPI_FLASH_ATMEL |
| 64 | #define CONFIG_ATMEL_DATAFLASH_SPI |
| 65 | #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 |
| 66 | #define DATAFLASH_TCSS (0x1a << 16) |
| 67 | #define DATAFLASH_TCHS (0x1 << 24) |
| 68 | |
| 69 | #define CONFIG_ENV_IS_IN_SPI_FLASH |
| 70 | #define CONFIG_ENV_OFFSET 0x3DE000 |
| 71 | #define CONFIG_ENV_SECT_SIZE (132 << 10) |
| 72 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE |
| 73 | #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \ |
| 74 | + CONFIG_ENV_OFFSET) |
| 75 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \ |
| 76 | + 0x042000) |
| 77 | |
| 78 | /* SPI */ |
| 79 | #define CONFIG_ATMEL_SPI |
Tim Schendekehl | 14c3261 | 2011-11-01 23:55:01 +0000 | [diff] [blame] | 80 | #define AT91_SPI_CLK 15000000 |
| 81 | |
| 82 | /* Serial port */ |
| 83 | #define CONFIG_ATMEL_USART |
| 84 | #define CONFIG_USART3 /* USART 3 is DBGU */ |
| 85 | #define CONFIG_BAUDRATE 115200 |
Tim Schendekehl | 14c3261 | 2011-11-01 23:55:01 +0000 | [diff] [blame] | 86 | #define CONFIG_USART_BASE ATMEL_BASE_DBGU |
| 87 | #define CONFIG_USART_ID ATMEL_ID_SYS |
| 88 | |
| 89 | /* Misc. hardware drivers */ |
| 90 | #define CONFIG_AT91_GPIO |
| 91 | |
| 92 | /* Command line configuration */ |
Tim Schendekehl | 14c3261 | 2011-11-01 23:55:01 +0000 | [diff] [blame] | 93 | #define CONFIG_CMD_JFFS2 |
| 94 | #define CONFIG_CMD_MII |
| 95 | #define CONFIG_CMD_MTDPARTS |
| 96 | #define CONFIG_CMD_NAND |
| 97 | #define CONFIG_CMD_SPI |
| 98 | |
Joe Hershberger | ef0f2f5 | 2015-06-22 16:15:30 -0500 | [diff] [blame] | 99 | #ifndef MINIMAL_LOADER |
Tim Schendekehl | 14c3261 | 2011-11-01 23:55:01 +0000 | [diff] [blame] | 100 | #define CONFIG_CMD_ASKENV |
| 101 | #define CONFIG_CMD_BSP |
| 102 | #define CONFIG_CMD_CACHE |
| 103 | #define CONFIG_CMD_CDP |
| 104 | #define CONFIG_CMD_DATE |
| 105 | #define CONFIG_CMD_DHCP |
| 106 | #define CONFIG_CMD_DNS |
| 107 | #define CONFIG_CMD_EXT2 |
| 108 | #define CONFIG_CMD_FAT |
| 109 | #define CONFIG_CMD_I2C |
| 110 | #define CONFIG_CMD_MMC |
| 111 | #define CONFIG_CMD_PING |
| 112 | #define CONFIG_CMD_RARP |
| 113 | #define CONFIG_CMD_REISER |
| 114 | #define CONFIG_CMD_SAVES |
Tim Schendekehl | 14c3261 | 2011-11-01 23:55:01 +0000 | [diff] [blame] | 115 | #define CONFIG_CMD_SF |
| 116 | #define CONFIG_CMD_SNTP |
| 117 | #define CONFIG_CMD_UBI |
| 118 | #define CONFIG_CMD_UBIFS |
| 119 | #define CONFIG_CMD_UNZIP |
| 120 | #define CONFIG_CMD_USB |
| 121 | #endif |
| 122 | |
| 123 | /* NAND flash */ |
| 124 | #ifdef CONFIG_CMD_NAND |
| 125 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 126 | #define CONFIG_SYS_NAND_BASE 0x40000000 |
| 127 | #define CONFIG_SYS_NAND_DBW_8 |
| 128 | #define CONFIG_NAND_ATMEL |
| 129 | /* our ALE is AD21 */ |
| 130 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) |
| 131 | /* our CLE is AD22 */ |
| 132 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) |
Andreas Bießmann | ac45bb1 | 2013-11-29 12:13:45 +0100 | [diff] [blame] | 133 | #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) |
Tim Schendekehl | 14c3261 | 2011-11-01 23:55:01 +0000 | [diff] [blame] | 134 | #endif |
| 135 | |
| 136 | /* JFFS2 */ |
| 137 | #ifdef CONFIG_CMD_JFFS2 |
Tim Schendekehl | 14c3261 | 2011-11-01 23:55:01 +0000 | [diff] [blame] | 138 | #define CONFIG_JFFS2_CMDLINE |
| 139 | #define CONFIG_JFFS2_NAND |
| 140 | #endif |
| 141 | |
| 142 | /* Ethernet */ |
Tim Schendekehl | 14c3261 | 2011-11-01 23:55:01 +0000 | [diff] [blame] | 143 | #define CONFIG_NET_RETRY_COUNT 20 |
| 144 | #define CONFIG_MACB |
| 145 | #define CONFIG_RMII |
| 146 | #define CONFIG_PHY_ID 0 |
| 147 | #define CONFIG_MACB_SEARCH_PHY |
| 148 | |
| 149 | /* MMC */ |
| 150 | #ifdef CONFIG_CMD_MMC |
| 151 | #define CONFIG_MMC |
| 152 | #define CONFIG_GENERIC_MMC |
| 153 | #define CONFIG_GENERIC_ATMEL_MCI |
| 154 | #define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8 |
| 155 | #endif |
| 156 | |
| 157 | /* USB */ |
| 158 | #ifdef CONFIG_CMD_USB |
| 159 | #define CONFIG_USB_ATMEL |
Bo Shen | dcd2f1a | 2013-10-21 16:14:00 +0800 | [diff] [blame] | 160 | #define CONFIG_USB_ATMEL_CLK_SEL_PLLB |
Tim Schendekehl | 14c3261 | 2011-11-01 23:55:01 +0000 | [diff] [blame] | 161 | #define CONFIG_USB_OHCI_NEW |
| 162 | #define CONFIG_SYS_USB_OHCI_CPU_INIT |
| 163 | #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 |
| 164 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "host" |
| 165 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 |
| 166 | #define CONFIG_USB_STORAGE |
| 167 | #endif |
| 168 | |
| 169 | /* RTC */ |
| 170 | #if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP) |
| 171 | #define CONFIG_RTC_PCF8563 |
| 172 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 |
| 173 | #endif |
| 174 | |
| 175 | /* I2C */ |
| 176 | #define CONFIG_SYS_MAX_I2C_BUS 1 |
Tim Schendekehl | 14c3261 | 2011-11-01 23:55:01 +0000 | [diff] [blame] | 177 | |
Heiko Schocher | ea818db | 2013-01-29 08:53:15 +0100 | [diff] [blame] | 178 | #define CONFIG_SYS_I2C |
| 179 | #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ |
| 180 | #define CONFIG_SYS_I2C_SOFT_SPEED 100000 |
| 181 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0 |
| 182 | |
Tim Schendekehl | 14c3261 | 2011-11-01 23:55:01 +0000 | [diff] [blame] | 183 | #define I2C_SOFT_DECLARATIONS |
| 184 | |
| 185 | #define GPIO_I2C_SCL AT91_PIO_PORTA, 24 |
| 186 | #define GPIO_I2C_SDA AT91_PIO_PORTA, 23 |
| 187 | |
| 188 | #define I2C_INIT { \ |
| 189 | at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \ |
| 190 | at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \ |
| 191 | at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \ |
| 192 | at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \ |
| 193 | at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \ |
| 194 | } |
| 195 | |
| 196 | #define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0) |
| 197 | #define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0) |
| 198 | #define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit) |
| 199 | #define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit) |
| 200 | #define I2C_DELAY udelay(100) |
| 201 | #define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23) |
| 202 | |
| 203 | /* DHCP/BOOTP options */ |
| 204 | #ifdef CONFIG_CMD_DHCP |
| 205 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 206 | #define CONFIG_BOOTP_BOOTPATH |
| 207 | #define CONFIG_BOOTP_GATEWAY |
| 208 | #define CONFIG_BOOTP_HOSTNAME |
| 209 | #define CONFIG_SYS_AUTOLOAD "n" |
| 210 | #endif |
| 211 | |
| 212 | /* File systems */ |
| 213 | #define CONFIG_MTD_DEVICE |
| 214 | #define CONFIG_MTD_PARTITIONS |
| 215 | #if defined(CONFIG_CMD_MTDPARTS) || defined(CONFIG_CMD_NAND) |
| 216 | #define MTDIDS_DEFAULT "nand0=atmel_nand" |
| 217 | #define MTDPARTS_DEFAULT "mtdparts=atmel_nand:-(root)" |
| 218 | #endif |
| 219 | #if defined(CONFIG_CMD_REISER) || defined(CONFIG_CMD_EXT2) || \ |
| 220 | defined(CONFIG_CMD_USB) || defined(CONFIG_MMC) |
| 221 | #define CONFIG_DOS_PARTITION |
| 222 | #endif |
| 223 | #define CONFIG_LZO |
| 224 | #define CONFIG_RBTREE |
| 225 | |
| 226 | /* Boot command */ |
| 227 | #define CONFIG_BOOTDELAY 3 |
| 228 | #define CONFIG_CMDLINE_TAG |
| 229 | #define CONFIG_SETUP_MEMORY_TAGS |
| 230 | #define CONFIG_INITRD_TAG |
| 231 | #define CONFIG_BOOTCOMMAND "cp.b 0xC00C6000 ${loadaddr} 0x294000; bootm" |
| 232 | #if defined(CONFIG_CMD_NAND) |
| 233 | #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ |
| 234 | "root=/dev/mtdblock0 " \ |
| 235 | MTDPARTS_DEFAULT \ |
| 236 | " rw rootfstype=jffs2" |
| 237 | #endif |
| 238 | |
| 239 | /* Misc. u-boot settings */ |
| 240 | #define CONFIG_SYS_PROMPT "U-Boot> " |
| 241 | #define CONFIG_SYS_HUSH_PARSER |
Tim Schendekehl | 14c3261 | 2011-11-01 23:55:01 +0000 | [diff] [blame] | 242 | #define CONFIG_SYS_CBSIZE 256 |
| 243 | #define CONFIG_SYS_MAXARGS 16 |
| 244 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 16 \ |
| 245 | + sizeof(CONFIG_SYS_PROMPT)) |
| 246 | #define CONFIG_SYS_LONGHELP |
| 247 | #define CONFIG_CMDLINE_EDITING |
| 248 | |
| 249 | #endif |