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wdenk717b5aa2002-04-27 11:09:31 +00001/*
2 * NS16550 Serial Port
3 * originally from linux source (arch/ppc/boot/ns16550.h)
Detlev Zundel200779e2009-04-03 11:53:01 +02004 *
5 * Cleanup and unification
6 * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH
7 *
wdenk717b5aa2002-04-27 11:09:31 +00008 * modified slightly to
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02009 * have addresses as offsets from CONFIG_SYS_ISA_BASE
wdenk717b5aa2002-04-27 11:09:31 +000010 * added a few more definitions
11 * added prototypes for ns16550.c
12 * reduced no of com ports to 2
13 * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020014 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +020015 * added support for port on 64-bit bus
16 * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
wdenk717b5aa2002-04-27 11:09:31 +000017 */
18
Detlev Zundel453c0d72009-04-03 16:45:46 +020019/*
20 * Note that the following macro magic uses the fact that the compiler
21 * will not allocate storage for arrays of size 0
22 */
23
24#if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0)
wdenk717b5aa2002-04-27 11:09:31 +000025#error "Please define NS16550 registers size."
Detlev Zundel453c0d72009-04-03 16:45:46 +020026#elif (CONFIG_SYS_NS16550_REG_SIZE > 0)
27#define UART_REG(x) \
28 unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \
29 unsigned char x;
30#elif (CONFIG_SYS_NS16550_REG_SIZE < 0)
31#define UART_REG(x) \
32 unsigned char x; \
33 unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1];
wdenk717b5aa2002-04-27 11:09:31 +000034#endif
35
Detlev Zundel453c0d72009-04-03 16:45:46 +020036struct NS16550 {
37 UART_REG(rbr); /* 0 */
38 UART_REG(ier); /* 1 */
39 UART_REG(fcr); /* 2 */
40 UART_REG(lcr); /* 3 */
41 UART_REG(mcr); /* 4 */
42 UART_REG(lsr); /* 5 */
43 UART_REG(msr); /* 6 */
44 UART_REG(spr); /* 7 */
45 UART_REG(mdr1); /* 8 */
46 UART_REG(reg9); /* 9 */
47 UART_REG(regA); /* A */
48 UART_REG(regB); /* B */
49 UART_REG(regC); /* C */
50 UART_REG(regD); /* D */
51 UART_REG(regE); /* E */
52 UART_REG(uasr); /* F */
53 UART_REG(scr); /* 10*/
54 UART_REG(ssr); /* 11*/
55 UART_REG(reg12); /* 12*/
56 UART_REG(osc_12m_sel); /* 13*/
57};
58
wdenk717b5aa2002-04-27 11:09:31 +000059#define thr rbr
60#define iir fcr
61#define dll rbr
62#define dlm ier
63
64typedef volatile struct NS16550 *NS16550_t;
65
Detlev Zundel200779e2009-04-03 11:53:01 +020066/*
67 * These are the definitions for the FIFO Control Register
68 */
69#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
70#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
71#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
72#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
73#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
74#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
75#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
76#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
77#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
wdenk717b5aa2002-04-27 11:09:31 +000078
Detlev Zundel200779e2009-04-03 11:53:01 +020079#define UART_FCR_RXSR 0x02 /* Receiver soft reset */
80#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
wdenk717b5aa2002-04-27 11:09:31 +000081
Detlev Zundel200779e2009-04-03 11:53:01 +020082/*
83 * These are the definitions for the Modem Control Register
84 */
85#define UART_MCR_DTR 0x01 /* DTR */
86#define UART_MCR_RTS 0x02 /* RTS */
87#define UART_MCR_OUT1 0x04 /* Out 1 */
88#define UART_MCR_OUT2 0x08 /* Out 2 */
89#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
wdenk717b5aa2002-04-27 11:09:31 +000090
Detlev Zundel200779e2009-04-03 11:53:01 +020091#define UART_MCR_DMA_EN 0x04
92#define UART_MCR_TX_DFR 0x08
wdenk717b5aa2002-04-27 11:09:31 +000093
Detlev Zundel200779e2009-04-03 11:53:01 +020094/*
95 * These are the definitions for the Line Control Register
96 *
97 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
98 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
99 */
100#define UART_LCR_WLS_MSK 0x03 /* character length select mask */
101#define UART_LCR_WLS_5 0x00 /* 5 bit character length */
102#define UART_LCR_WLS_6 0x01 /* 6 bit character length */
103#define UART_LCR_WLS_7 0x02 /* 7 bit character length */
104#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
105#define UART_LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
106#define UART_LCR_PEN 0x08 /* Parity eneble */
107#define UART_LCR_EPS 0x10 /* Even Parity Select */
108#define UART_LCR_STKP 0x20 /* Stick Parity */
109#define UART_LCR_SBRK 0x40 /* Set Break */
110#define UART_LCR_BKSE 0x80 /* Bank select enable */
111#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
112
113/*
114 * These are the definitions for the Line Status Register
115 */
116#define UART_LSR_DR 0x01 /* Data ready */
117#define UART_LSR_OE 0x02 /* Overrun */
118#define UART_LSR_PE 0x04 /* Parity error */
119#define UART_LSR_FE 0x08 /* Framing error */
120#define UART_LSR_BI 0x10 /* Break */
121#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
122#define UART_LSR_TEMT 0x40 /* Xmitter empty */
123#define UART_LSR_ERR 0x80 /* Error */
124
125#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
126#define UART_MSR_RI 0x40 /* Ring Indicator */
127#define UART_MSR_DSR 0x20 /* Data Set Ready */
128#define UART_MSR_CTS 0x10 /* Clear to Send */
129#define UART_MSR_DDCD 0x08 /* Delta DCD */
130#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
131#define UART_MSR_DDSR 0x02 /* Delta DSR */
132#define UART_MSR_DCTS 0x01 /* Delta CTS */
133
134/*
135 * These are the definitions for the Interrupt Identification Register
136 */
137#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
138#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
139
140#define UART_IIR_MSI 0x00 /* Modem status interrupt */
141#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
142#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
143#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
144
145/*
146 * These are the definitions for the Interrupt Enable Register
147 */
148#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
149#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
150#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
151#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
152
Detlev Zundel7b5611c2009-03-30 00:31:34 +0200153
wdenk2e5983d2003-07-15 20:04:06 +0000154#ifdef CONFIG_OMAP1510
Detlev Zundel200779e2009-04-03 11:53:01 +0200155#define OSC_12M_SEL 0x01 /* selects 6.5 * current clk div */
wdenk2e5983d2003-07-15 20:04:06 +0000156#endif
157
wdenk717b5aa2002-04-27 11:09:31 +0000158/* useful defaults for LCR */
Detlev Zundel200779e2009-04-03 11:53:01 +0200159#define UART_LCR_8N1 0x03
wdenk717b5aa2002-04-27 11:09:31 +0000160
161void NS16550_init (NS16550_t com_port, int baud_divisor);
162void NS16550_putc (NS16550_t com_port, char c);
163char NS16550_getc (NS16550_t com_port);
164int NS16550_tstc (NS16550_t com_port);
165void NS16550_reinit (NS16550_t com_port, int baud_divisor);