blob: f23ca63f3b84d02d6227ae43e0be7bca22b292f7 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Andy Fleming5f184712011-04-08 02:10:27 -05002/*
3 * Copyright 2011 Freescale Semiconductor, Inc.
Andy Flemingb21f87a32014-07-25 17:39:08 -05004 * Andy Fleming <afleming@gmail.com>
Andy Fleming5f184712011-04-08 02:10:27 -05005 *
Andy Fleming5f184712011-04-08 02:10:27 -05006 * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
7 */
8
9#ifndef _PHY_H
10#define _PHY_H
11
Grygorii Strashkoeef0b8a2018-07-05 12:02:48 -050012#include <dm.h>
Andy Fleming5f184712011-04-08 02:10:27 -050013#include <linux/list.h>
14#include <linux/mii.h>
15#include <linux/ethtool.h>
16#include <linux/mdio.h>
Joe Hershbergerf070b1a2018-07-17 15:02:30 -050017#include <phy_interface.h>
Andy Fleming5f184712011-04-08 02:10:27 -050018
Hannes Schmelzerdb40c1a2017-03-23 15:11:43 +010019#define PHY_FIXED_ID 0xa5a55a5a
20
Andy Fleming5f184712011-04-08 02:10:27 -050021#define PHY_MAX_ADDR 32
22
Shaohui Xieddcd1f32016-01-28 15:55:46 +080023#define PHY_FLAG_BROKEN_RESET (1 << 0) /* soft reset not supported */
24
Florian Fainelli4dae6102016-01-13 16:59:33 +030025#define PHY_DEFAULT_FEATURES (SUPPORTED_Autoneg | \
Andy Fleming5f184712011-04-08 02:10:27 -050026 SUPPORTED_TP | \
27 SUPPORTED_MII)
28
Florian Fainelli4dae6102016-01-13 16:59:33 +030029#define PHY_10BT_FEATURES (SUPPORTED_10baseT_Half | \
30 SUPPORTED_10baseT_Full)
31
32#define PHY_100BT_FEATURES (SUPPORTED_100baseT_Half | \
33 SUPPORTED_100baseT_Full)
34
35#define PHY_1000BT_FEATURES (SUPPORTED_1000baseT_Half | \
Andy Fleming5f184712011-04-08 02:10:27 -050036 SUPPORTED_1000baseT_Full)
37
Florian Fainelli4dae6102016-01-13 16:59:33 +030038#define PHY_BASIC_FEATURES (PHY_10BT_FEATURES | \
39 PHY_100BT_FEATURES | \
40 PHY_DEFAULT_FEATURES)
41
42#define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \
43 PHY_1000BT_FEATURES)
44
Andy Fleming5f184712011-04-08 02:10:27 -050045#define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \
46 SUPPORTED_10000baseT_Full)
47
Stefan Roese4fb3f0c2014-10-22 12:13:15 +020048#ifndef PHY_ANEG_TIMEOUT
Andy Fleming5f184712011-04-08 02:10:27 -050049#define PHY_ANEG_TIMEOUT 4000
Stefan Roese4fb3f0c2014-10-22 12:13:15 +020050#endif
Andy Fleming5f184712011-04-08 02:10:27 -050051
52
Andy Fleming5f184712011-04-08 02:10:27 -050053struct phy_device;
54
55#define MDIO_NAME_LEN 32
56
57struct mii_dev {
58 struct list_head link;
59 char name[MDIO_NAME_LEN];
60 void *priv;
61 int (*read)(struct mii_dev *bus, int addr, int devad, int reg);
62 int (*write)(struct mii_dev *bus, int addr, int devad, int reg,
63 u16 val);
64 int (*reset)(struct mii_dev *bus);
65 struct phy_device *phymap[PHY_MAX_ADDR];
66 u32 phy_mask;
67};
68
69/* struct phy_driver: a structure which defines PHY behavior
70 *
71 * uid will contain a number which represents the PHY. During
72 * startup, the driver will poll the PHY to find out what its
73 * UID--as defined by registers 2 and 3--is. The 32-bit result
74 * gotten from the PHY will be masked to
75 * discard any bits which may change based on revision numbers
76 * unimportant to functionality
77 *
78 */
79struct phy_driver {
80 char *name;
81 unsigned int uid;
82 unsigned int mask;
83 unsigned int mmds;
84
85 u32 features;
86
87 /* Called to do any driver startup necessities */
88 /* Will be called during phy_connect */
89 int (*probe)(struct phy_device *phydev);
90
91 /* Called to configure the PHY, and modify the controller
92 * based on the results. Should be called after phy_connect */
93 int (*config)(struct phy_device *phydev);
94
95 /* Called when starting up the controller */
96 int (*startup)(struct phy_device *phydev);
97
98 /* Called when bringing down the controller */
99 int (*shutdown)(struct phy_device *phydev);
100
Stefano Babicb71841b2013-09-02 15:42:30 +0200101 int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
102 int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
103 u16 val);
Andy Fleming5f184712011-04-08 02:10:27 -0500104 struct list_head list;
105};
106
107struct phy_device {
108 /* Information about the PHY type */
109 /* And management functions */
110 struct mii_dev *bus;
111 struct phy_driver *drv;
112 void *priv;
113
Simon Glassc74c8e62015-04-05 16:07:39 -0600114#ifdef CONFIG_DM_ETH
115 struct udevice *dev;
Grygorii Strashkoeef0b8a2018-07-05 12:02:48 -0500116 ofnode node;
Simon Glassc74c8e62015-04-05 16:07:39 -0600117#else
Andy Fleming5f184712011-04-08 02:10:27 -0500118 struct eth_device *dev;
Simon Glassc74c8e62015-04-05 16:07:39 -0600119#endif
Andy Fleming5f184712011-04-08 02:10:27 -0500120
121 /* forced speed & duplex (no autoneg)
122 * partner speed & duplex & pause (autoneg)
123 */
124 int speed;
125 int duplex;
126
127 /* The most recently read link state */
128 int link;
129 int port;
130 phy_interface_t interface;
131
132 u32 advertising;
133 u32 supported;
134 u32 mmds;
135
136 int autoneg;
137 int addr;
138 int pause;
139 int asym_pause;
140 u32 phy_id;
Pankaj Bansalb3eabd82018-11-16 06:26:18 +0000141 bool is_c45;
Andy Fleming5f184712011-04-08 02:10:27 -0500142 u32 flags;
143};
144
Shaohui Xief55a7762013-11-14 19:00:31 +0800145struct fixed_link {
146 int phy_id;
147 int duplex;
148 int link_speed;
149 int pause;
150 int asym_pause;
151};
152
Andy Fleming5f184712011-04-08 02:10:27 -0500153static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
154{
155 struct mii_dev *bus = phydev->bus;
156
157 return bus->read(bus, phydev->addr, devad, regnum);
158}
159
160static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
161 u16 val)
162{
163 struct mii_dev *bus = phydev->bus;
164
165 return bus->write(bus, phydev->addr, devad, regnum, val);
166}
167
168#ifdef CONFIG_PHYLIB_10G
169extern struct phy_driver gen10g_driver;
170
171/* For now, XGMII is the only 10G interface */
172static inline int is_10g_interface(phy_interface_t interface)
173{
174 return interface == PHY_INTERFACE_MODE_XGMII;
175}
176
177#endif
178
179int phy_init(void);
180int phy_reset(struct phy_device *phydev);
Troy Kisky1adb4062012-10-22 16:40:43 +0000181struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
182 phy_interface_t interface);
Simon Glassc74c8e62015-04-05 16:07:39 -0600183#ifdef CONFIG_DM_ETH
184void phy_connect_dev(struct phy_device *phydev, struct udevice *dev);
185struct phy_device *phy_connect(struct mii_dev *bus, int addr,
186 struct udevice *dev,
187 phy_interface_t interface);
Grygorii Strashkoeef0b8a2018-07-05 12:02:48 -0500188static inline ofnode phy_get_ofnode(struct phy_device *phydev)
189{
190 if (ofnode_valid(phydev->node))
191 return phydev->node;
192 else
193 return dev_ofnode(phydev->dev);
194}
Simon Glassc74c8e62015-04-05 16:07:39 -0600195#else
Troy Kisky1adb4062012-10-22 16:40:43 +0000196void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev);
Andy Fleming5f184712011-04-08 02:10:27 -0500197struct phy_device *phy_connect(struct mii_dev *bus, int addr,
198 struct eth_device *dev,
199 phy_interface_t interface);
Grygorii Strashkoeef0b8a2018-07-05 12:02:48 -0500200static inline ofnode phy_get_ofnode(struct phy_device *phydev)
201{
202 return ofnode_null();
203}
Simon Glassc74c8e62015-04-05 16:07:39 -0600204#endif
Andy Fleming5f184712011-04-08 02:10:27 -0500205int phy_startup(struct phy_device *phydev);
206int phy_config(struct phy_device *phydev);
207int phy_shutdown(struct phy_device *phydev);
208int phy_register(struct phy_driver *drv);
Alexey Brodkinb18acb02016-01-13 16:59:34 +0300209int phy_set_supported(struct phy_device *phydev, u32 max_speed);
Andy Fleming5f184712011-04-08 02:10:27 -0500210int genphy_config_aneg(struct phy_device *phydev);
Troy Kisky8682aba2012-02-07 14:08:48 +0000211int genphy_restart_aneg(struct phy_device *phydev);
Andy Fleming5f184712011-04-08 02:10:27 -0500212int genphy_update_link(struct phy_device *phydev);
Yegor Yefremove2043f52012-11-28 11:15:17 +0100213int genphy_parse_link(struct phy_device *phydev);
Andy Fleming5f184712011-04-08 02:10:27 -0500214int genphy_config(struct phy_device *phydev);
215int genphy_startup(struct phy_device *phydev);
216int genphy_shutdown(struct phy_device *phydev);
217int gen10g_config(struct phy_device *phydev);
218int gen10g_startup(struct phy_device *phydev);
219int gen10g_shutdown(struct phy_device *phydev);
220int gen10g_discover_mmds(struct phy_device *phydev);
221
Florian Fainelli137963d2017-12-09 14:59:54 -0800222int phy_b53_init(void);
Kevin Smith24ae3962016-03-31 19:33:12 +0000223int phy_mv88e61xx_init(void);
Shaohui Xief7c38cf2014-12-30 18:32:04 +0800224int phy_aquantia_init(void);
Andy Fleming9082eea2011-04-07 21:56:05 -0500225int phy_atheros_init(void);
226int phy_broadcom_init(void);
Shengzhou Liu9b18e512014-11-10 18:32:29 +0800227int phy_cortina_init(void);
Andy Fleming9082eea2011-04-07 21:56:05 -0500228int phy_davicom_init(void);
Matt Porterf485c8a2013-03-20 05:38:13 +0000229int phy_et1011c_init(void);
Andy Fleming9082eea2011-04-07 21:56:05 -0500230int phy_lxt_init(void);
231int phy_marvell_init(void);
Alexandru Gagniucd397f7c2017-07-07 11:36:57 -0700232int phy_micrel_ksz8xxx_init(void);
233int phy_micrel_ksz90x1_init(void);
Neil Armstrong8995a962017-10-18 10:02:10 +0200234int phy_meson_gxl_init(void);
Andy Fleming9082eea2011-04-07 21:56:05 -0500235int phy_natsemi_init(void);
236int phy_realtek_init(void);
Vladimir Zapolskiyb6abf552011-12-29 15:18:37 +0000237int phy_smsc_init(void);
Andy Fleming9082eea2011-04-07 21:56:05 -0500238int phy_teranetics_init(void);
Edgar E. Iglesias721aed72015-09-25 23:46:08 -0700239int phy_ti_init(void);
Andy Fleming9082eea2011-04-07 21:56:05 -0500240int phy_vitesse_init(void);
Siva Durga Prasad Paladugued6fad32016-02-05 13:22:10 +0530241int phy_xilinx_init(void);
John Haechtena5fd13a2016-12-09 22:15:17 +0000242int phy_mscc_init(void);
Hannes Schmelzerdb40c1a2017-03-23 15:11:43 +0100243int phy_fixed_init(void);
Timur Tabia8366262011-10-18 18:44:34 -0500244
Fabio Estevam2fb63962014-02-15 14:52:00 -0200245int board_phy_config(struct phy_device *phydev);
Shengzhou Liu5707d5f2015-04-07 18:46:32 +0800246int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);
Fabio Estevam2fb63962014-02-15 14:52:00 -0200247
Simon Glassc74c8e62015-04-05 16:07:39 -0600248/**
249 * phy_get_interface_by_name() - Look up a PHY interface name
250 *
251 * @str: PHY interface name, e.g. "mii"
252 * @return PHY_INTERFACE_MODE_... value, or -1 if not found
253 */
254int phy_get_interface_by_name(const char *str);
255
Dan Murphy3ab72fe2016-05-02 15:46:00 -0500256/**
257 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
258 * is RGMII (all variants)
259 * @phydev: the phy_device struct
260 */
261static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
262{
263 return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
264 phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
265}
266
Dan Murphy3c221af2016-05-02 15:46:01 -0500267/**
268 * phy_interface_is_sgmii - Convenience function for testing if a PHY interface
269 * is SGMII (all variants)
270 * @phydev: the phy_device struct
271 */
272static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
273{
274 return phydev->interface >= PHY_INTERFACE_MODE_SGMII &&
275 phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
276}
277
Timur Tabia8366262011-10-18 18:44:34 -0500278/* PHY UIDs for various PHYs that are referenced in external code */
Priyanka Jain1ddcf5e2018-10-11 04:47:05 +0000279#define PHY_UID_CS4340 0x13e51002
280#define PHY_UID_CS4223 0x03e57003
281#define PHY_UID_TN2020 0x00a19410
282#define PHY_UID_IN112525_S03 0x02107440
Timur Tabia8366262011-10-18 18:44:34 -0500283
Andy Fleming5f184712011-04-08 02:10:27 -0500284#endif