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wdenk0f8c9762002-08-19 11:57:05 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2001-2005
wdenk0f8c9762002-08-19 11:57:05 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * Imported from global configuration:
wdenk27b207f2003-07-24 23:38:38 +000033 * CONFIG_MPC8255
34 * CONFIG_MPC8265
35 * CONFIG_200MHz
wdenk0f8c9762002-08-19 11:57:05 +000036 * CONFIG_266MHz
37 * CONFIG_300MHz
wdenk27b207f2003-07-24 23:38:38 +000038 * CONFIG_L2_CACHE
39 * CONFIG_BUSMODE_60x
wdenk0f8c9762002-08-19 11:57:05 +000040 */
41
42/*
43 * High Level Configuration Options
44 * (easy to change)
45 */
46
47#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
48
49#if 0
50#define CONFIG_TQM8260 100 /* ...on a TQM8260 module Rev.100 */
51#else
52#define CONFIG_TQM8260 200 /* ...on a TQM8260 module Rev.200 */
53#endif
54
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050055#define CONFIG_CPM2 1 /* Has a CPM2 */
56
wdenk0f8c9762002-08-19 11:57:05 +000057#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */
58
59#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
60
wdenkae3af052003-08-07 22:18:11 +000061#define CONFIG_BOOTCOUNT_LIMIT
62
63#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
64#define CONFIG_BAUDRATE 230400
65#else
66#define CONFIG_BAUDRATE 9600
67#endif
wdenk0f8c9762002-08-19 11:57:05 +000068
69#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
70
71#undef CONFIG_BOOTARGS
wdenk506f0442003-03-28 14:40:36 +000072
73#define CONFIG_EXTRA_ENV_SETTINGS \
wdenkae3af052003-08-07 22:18:11 +000074 "netdev=eth0\0" \
wdenk506f0442003-03-28 14:40:36 +000075 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010076 "nfsroot=${serverip}:${rootpath}\0" \
wdenk506f0442003-03-28 14:40:36 +000077 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010078 "addip=setenv bootargs ${bootargs} " \
79 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
80 ":${hostname}:${netdev}:off panic=1\0" \
wdenk506f0442003-03-28 14:40:36 +000081 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010082 "bootm ${kernel_addr}\0" \
wdenk506f0442003-03-28 14:40:36 +000083 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010084 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
85 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk506f0442003-03-28 14:40:36 +000086 "rootpath=/opt/eldk/ppc_82xx\0" \
87 "bootfile=/tftpboot/TQM8260/uImage\0" \
88 "kernel_addr=40040000\0" \
89 "ramdisk_addr=40100000\0" \
90 ""
91#define CONFIG_BOOTCOMMAND "run flash_self"
wdenk0f8c9762002-08-19 11:57:05 +000092
93/* enable I2C and select the hardware/software driver */
94#undef CONFIG_HARD_I2C /* I2C with hardware support */
95#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
96#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
97#define CFG_I2C_SLAVE 0x7F
98
99/*
100 * Software (bit-bang) I2C driver configuration
101 */
102
103/* TQM8260 Rev.100 has the clock and data pins swapped (!!!) on EEPROM */
104#if (CONFIG_TQM8260 <= 100)
105
106#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
107#define I2C_ACTIVE (iop->pdir |= 0x00020000)
108#define I2C_TRISTATE (iop->pdir &= ~0x00020000)
109#define I2C_READ ((iop->pdat & 0x00020000) != 0)
110#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00020000; \
111 else iop->pdat &= ~0x00020000
112#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00010000; \
113 else iop->pdat &= ~0x00010000
114#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
115
116#else
117
118#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
119#define I2C_ACTIVE (iop->pdir |= 0x00010000)
120#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
121#define I2C_READ ((iop->pdat & 0x00010000) != 0)
122#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
123 else iop->pdat &= ~0x00010000
124#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
125 else iop->pdat &= ~0x00020000
126#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
127#endif
128
129#define CFG_I2C_EEPROM_ADDR 0x50
130#define CFG_I2C_EEPROM_ADDR_LEN 2
131#define CFG_EEPROM_PAGE_WRITE_BITS 4
132#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
133
134#define CONFIG_I2C_X
135
136/*
137 * select serial console configuration
138 *
139 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
140 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
141 * for SCC).
142 *
143 * if CONFIG_CONS_NONE is defined, then the serial console routines must
144 * defined elsewhere (for example, on the cogent platform, there are serial
145 * ports on the motherboard which are used for the serial console - see
146 * cogent/cma101/serial.[ch]).
147 */
148#define CONFIG_CONS_ON_SMC /* define if console on SMC */
149#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
150#undef CONFIG_CONS_NONE /* define if console on something else*/
151#ifdef CONFIG_82xx_CONS_SMC1
152#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
153#endif
154#ifdef CONFIG_82xx_CONS_SMC2
155#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
156#endif
157
158#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
159#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
160#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */
161
162/*
163 * select ethernet configuration
164 *
165 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
166 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
167 * for FCC)
168 *
169 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
170 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
171 * from CONFIG_COMMANDS to remove support for networking.
172 *
173 * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
174 * X.29 connector, and FCC2 is hardwired to the X.1 connector)
175 */
176#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
177#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
178#undef CONFIG_ETHER_NONE /* define if ether on something else */
179#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
180
181#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
182
183/*
184 * - RX clk is CLK11
185 * - TX clk is CLK12
186 */
187# define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
188
189#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
190
191/*
192 * - Rx-CLK is CLK13
193 * - Tx-CLK is CLK14
194 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
195 * - Enable Full Duplex in FSMR
196 */
197# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
198# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
199# define CFG_CPMFCR_RAMTYPE 0
200# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
201
202#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
203
204
205/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
wdenk27b207f2003-07-24 23:38:38 +0000206#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265)
wdenk7aa78612003-05-03 15:50:43 +0000207# define CONFIG_8260_CLKIN 66666666 /* in Hz */
wdenk27b207f2003-07-24 23:38:38 +0000208#else /* !CONFIG_MPC8255 && !CONFIG_MPC8265 */
wdenk7aa78612003-05-03 15:50:43 +0000209# ifndef CONFIG_300MHz
210# define CONFIG_8260_CLKIN 66666666 /* in Hz */
211# else
212# define CONFIG_8260_CLKIN 83333000 /* in Hz */
213# endif
214#endif /* CONFIG_MPC8255 */
wdenk0f8c9762002-08-19 11:57:05 +0000215
wdenk0f8c9762002-08-19 11:57:05 +0000216#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
217#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
218
219#undef CONFIG_WATCHDOG /* watchdog disabled */
220
wdenk414eec32005-04-02 22:37:54 +0000221#define CONFIG_TIMESTAMP /* Print image info with timestamp */
222
wdenk0f8c9762002-08-19 11:57:05 +0000223#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
224
wdenk414eec32005-04-02 22:37:54 +0000225#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
226 CFG_CMD_DHCP | \
227 CFG_CMD_I2C | \
228 CFG_CMD_EEPROM | \
229 CFG_CMD_NFS | \
230 CFG_CMD_SNTP )
wdenk0f8c9762002-08-19 11:57:05 +0000231
232/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
233#include <cmd_confdefs.h>
234
235/*
236 * Miscellaneous configurable options
237 */
238#define CFG_LONGHELP /* undef to save memory */
239#define CFG_PROMPT "=> " /* Monitor Command Prompt */
240#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
241#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
242#else
243#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
244#endif
245#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
246#define CFG_MAXARGS 16 /* max number of command args */
247#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
248
249#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
250#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
251
252#define CFG_LOAD_ADDR 0x100000 /* default load address */
253
254#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
255
256#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
257
258#define CFG_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */
259
260/*
261 * For booting Linux, the board info and command line data
262 * have to be in the first 8 MB of memory, since this is
263 * the maximum mapped by the Linux kernel during initialization.
264 */
265#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
266
267
268/* What should the base address of the main FLASH be and how big is
269 * it (in MBytes)? This must contain TEXT_BASE from board/tqm8260/config.mk
270 * The main FLASH is whichever is connected to *CS0.
271 */
272#define CFG_FLASH0_BASE 0x40000000
273#define CFG_FLASH1_BASE 0x60000000
274#define CFG_FLASH0_SIZE 32
275#define CFG_FLASH1_SIZE 32
276
277/* Flash bank size (for preliminary settings)
278 */
279#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
280
281/*-----------------------------------------------------------------------
282 * FLASH organization
283 */
284#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
285#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
286
287#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
288#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
289
290#if 0
291/* Start port with environment in flash; switch to EEPROM later */
292#define CFG_ENV_IS_IN_FLASH 1
293#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x40000)
294#define CFG_ENV_SIZE 0x40000
295#define CFG_ENV_SECT_SIZE 0x40000
296#else
297/* Final version: environment in EEPROM */
298#define CFG_ENV_IS_IN_EEPROM 1
299#define CFG_ENV_OFFSET 0
300#define CFG_ENV_SIZE 2048
301#endif
302
303/*-----------------------------------------------------------------------
304 * Hardware Information Block
305 */
306#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
307#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
308#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
309
310/*-----------------------------------------------------------------------
311 * Hard Reset Configuration Words
312 *
313 * if you change bits in the HRCW, you must also change the CFG_*
314 * defines for the various registers affected by the HRCW e.g. changing
315 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
316 */
wdenk7aa78612003-05-03 15:50:43 +0000317#define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
318
wdenk27b207f2003-07-24 23:38:38 +0000319#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265)
wdenk7aa78612003-05-03 15:50:43 +0000320# define CFG_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111)
wdenk27b207f2003-07-24 23:38:38 +0000321#else /* ! MPC8255 && !MPC8265 */
wdenk7aa78612003-05-03 15:50:43 +0000322# if defined(CONFIG_266MHz)
323# define CFG_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111)
324# elif defined(CONFIG_300MHz)
325# define CFG_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0110)
326# else
327# define CFG_HRCW_MASTER (__HRCW__ALL__)
328# endif
329#endif /* CONFIG_MPC8255 */
wdenk0f8c9762002-08-19 11:57:05 +0000330
331/* no slaves so just fill with zeros */
332#define CFG_HRCW_SLAVE1 0
333#define CFG_HRCW_SLAVE2 0
334#define CFG_HRCW_SLAVE3 0
335#define CFG_HRCW_SLAVE4 0
336#define CFG_HRCW_SLAVE5 0
337#define CFG_HRCW_SLAVE6 0
338#define CFG_HRCW_SLAVE7 0
339
340/*-----------------------------------------------------------------------
341 * Internal Memory Mapped Register
342 */
343#define CFG_IMMR 0xFFF00000
344
345/*-----------------------------------------------------------------------
346 * Definitions for initial stack pointer and data area (in DPRAM)
347 */
348#define CFG_INIT_RAM_ADDR CFG_IMMR
349#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
350#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
351#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
352#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
353
354/*-----------------------------------------------------------------------
355 * Start addresses for the final memory configuration
356 * (Set up by the startup code)
357 * Please note that CFG_SDRAM_BASE _must_ start at 0
358 *
359 * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
360 * is mapped at SDRAM_BASE2_PRELIM.
361 */
362#define CFG_SDRAM_BASE 0x00000000
363#define CFG_FLASH_BASE CFG_FLASH0_BASE
364#define CFG_MONITOR_BASE TEXT_BASE
365#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
366#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
367
368/*
369 * Internal Definitions
370 *
371 * Boot Flags
372 */
373#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
374#define BOOTFLAG_WARM 0x02 /* Software reboot */
375
376
377/*-----------------------------------------------------------------------
378 * Cache Configuration
379 */
380#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
381#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
382# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
383#endif
384
385/*-----------------------------------------------------------------------
386 * HIDx - Hardware Implementation-dependent Registers 2-11
387 *-----------------------------------------------------------------------
388 * HID0 also contains cache control - initially enable both caches and
389 * invalidate contents, then the final state leaves only the instruction
390 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
391 * but Soft reset does not.
392 *
393 * HID1 has only read-only information - nothing to set.
394 */
395#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
wdenk8bde7f72003-06-27 21:31:46 +0000396 HID0_IFEM|HID0_ABE)
wdenk0f8c9762002-08-19 11:57:05 +0000397#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE)
398#define CFG_HID2 0
399
400/*-----------------------------------------------------------------------
401 * RMR - Reset Mode Register 5-5
402 *-----------------------------------------------------------------------
403 * turn on Checkstop Reset Enable
404 */
405#define CFG_RMR RMR_CSRE
406
407/*-----------------------------------------------------------------------
408 * BCR - Bus Configuration 4-25
409 *-----------------------------------------------------------------------
410 */
411#ifdef CONFIG_BUSMODE_60x
412#define CFG_BCR (BCR_EBM|BCR_L2C|BCR_LETM|\
413 BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode */
414#else
415#define BCR_APD01 0x10000000
416#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
417#endif
418
419/*-----------------------------------------------------------------------
420 * SIUMCR - SIU Module Configuration 4-31
421 *-----------------------------------------------------------------------
422 */
423#if 0
424#define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10)
425#else
426#define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10)
427#endif
428
429
430/*-----------------------------------------------------------------------
431 * SYPCR - System Protection Control 4-35
432 * SYPCR can only be written once after reset!
433 *-----------------------------------------------------------------------
434 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
435 */
436#if defined(CONFIG_WATCHDOG)
437#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenk8bde7f72003-06-27 21:31:46 +0000438 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
wdenk0f8c9762002-08-19 11:57:05 +0000439#else
440#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenk8bde7f72003-06-27 21:31:46 +0000441 SYPCR_SWRI|SYPCR_SWP)
wdenk0f8c9762002-08-19 11:57:05 +0000442#endif /* CONFIG_WATCHDOG */
443
444/*-----------------------------------------------------------------------
445 * TMCNTSC - Time Counter Status and Control 4-40
446 *-----------------------------------------------------------------------
447 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
448 * and enable Time Counter
449 */
450#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
451
452/*-----------------------------------------------------------------------
453 * PISCR - Periodic Interrupt Status and Control 4-42
454 *-----------------------------------------------------------------------
455 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
456 * Periodic timer
457 */
458#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
459
460/*-----------------------------------------------------------------------
461 * SCCR - System Clock Control 9-8
462 *-----------------------------------------------------------------------
463 * Ensure DFBRG is Divide by 16
464 */
465#define CFG_SCCR 0
466
467/*-----------------------------------------------------------------------
468 * RCCR - RISC Controller Configuration 13-7
469 *-----------------------------------------------------------------------
470 */
471#define CFG_RCCR 0
472
473/*
474 * Init Memory Controller:
475 *
476 * Bank Bus Machine PortSz Device
477 * ---- --- ------- ------ ------
478 * 0 60x GPCM 64 bit FLASH
479 * 1 60x SDRAM 64 bit SDRAM
480 * 2 Local SDRAM 32 bit SDRAM
481 *
482 */
483
484 /* Initialize SDRAM on local bus
485 */
486#define CFG_INIT_LOCAL_SDRAM
487
488#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
489
490/* Minimum mask to separate preliminary
491 * address ranges for CS[0:2]
492 */
493#define CFG_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */
494#define CFG_LOCAL_SDRAM_LIMIT (128<<20) /* less than 128 MB */
495
496#define CFG_MPTPR 0x4000
497
498/*-----------------------------------------------------------------------------
499 * Address for Mode Register Set (MRS) command
500 *-----------------------------------------------------------------------------
501 * In fact, the address is rather configuration data presented to the SDRAM on
502 * its address lines. Because the address lines may be mux'ed externally either
503 * for 8 column or 9 column devices, some bits appear twice in the 8260's
504 * address:
505 *
506 * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length |
507 * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 |
508 * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 |
509 * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 |
510 * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 |
511 *-----------------------------------------------------------------------------
512 */
513#define CFG_MRS_OFFS 0x00000110
514
515
516/* Bank 0 - FLASH
517 */
518#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000519 BRx_PS_64 |\
520 BRx_MS_GPCM_P |\
521 BRx_V)
wdenk0f8c9762002-08-19 11:57:05 +0000522
523#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000524 ORxG_CSNT |\
525 ORxG_ACS_DIV1 |\
526 ORxG_SCY_3_CLK |\
527 ORxG_EHTR |\
528 ORxG_TRLX)
wdenk0f8c9762002-08-19 11:57:05 +0000529
530 /* SDRAM on TQM8260 can have either 8 or 9 columns.
531 * The number affects configuration values.
532 */
533
534/* Bank 1 - 60x bus SDRAM
535 */
536#define CFG_PSRT 0x20
537#define CFG_LSRT 0x20
538#ifndef CFG_RAMBOOT
539#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000540 BRx_PS_64 |\
541 BRx_MS_SDRAM_P |\
542 BRx_V)
wdenk0f8c9762002-08-19 11:57:05 +0000543
544#define CFG_OR1_PRELIM CFG_OR1_8COL
545
546
547 /* SDRAM initialization values for 8-column chips
548 */
549#define CFG_OR1_8COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000550 ORxS_BPD_4 |\
551 ORxS_ROWST_PBI1_A7 |\
552 ORxS_NUMR_12)
wdenk0f8c9762002-08-19 11:57:05 +0000553
554#define CFG_PSDMR_8COL (PSDMR_PBI |\
wdenk8bde7f72003-06-27 21:31:46 +0000555 PSDMR_SDAM_A15_IS_A5 |\
556 PSDMR_BSMA_A12_A14 |\
557 PSDMR_SDA10_PBI1_A8 |\
558 PSDMR_RFRC_7_CLK |\
559 PSDMR_PRETOACT_2W |\
560 PSDMR_ACTTORW_2W |\
561 PSDMR_LDOTOPRE_1C |\
562 PSDMR_WRC_2C |\
563 PSDMR_EAMUX |\
564 PSDMR_CL_2)
wdenk0f8c9762002-08-19 11:57:05 +0000565
566 /* SDRAM initialization values for 9-column chips
567 */
568#define CFG_OR1_9COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000569 ORxS_BPD_4 |\
570 ORxS_ROWST_PBI1_A5 |\
571 ORxS_NUMR_13)
wdenk0f8c9762002-08-19 11:57:05 +0000572
573#define CFG_PSDMR_9COL (PSDMR_PBI |\
wdenk8bde7f72003-06-27 21:31:46 +0000574 PSDMR_SDAM_A16_IS_A5 |\
575 PSDMR_BSMA_A12_A14 |\
576 PSDMR_SDA10_PBI1_A7 |\
577 PSDMR_RFRC_7_CLK |\
578 PSDMR_PRETOACT_2W |\
579 PSDMR_ACTTORW_2W |\
580 PSDMR_LDOTOPRE_1C |\
581 PSDMR_WRC_2C |\
582 PSDMR_EAMUX |\
583 PSDMR_CL_2)
wdenk0f8c9762002-08-19 11:57:05 +0000584
585/* Bank 2 - Local bus SDRAM
586 */
587#ifdef CFG_INIT_LOCAL_SDRAM
588#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000589 BRx_PS_32 |\
590 BRx_MS_SDRAM_L |\
591 BRx_V)
wdenk0f8c9762002-08-19 11:57:05 +0000592
593#define CFG_OR2_PRELIM CFG_OR2_8COL
594
595#define SDRAM_BASE2_PRELIM 0x80000000
596
597 /* SDRAM initialization values for 8-column chips
598 */
599#define CFG_OR2_8COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000600 ORxS_BPD_4 |\
601 ORxS_ROWST_PBI1_A8 |\
602 ORxS_NUMR_12)
wdenk0f8c9762002-08-19 11:57:05 +0000603
604#define CFG_LSDMR_8COL (PSDMR_PBI |\
wdenk8bde7f72003-06-27 21:31:46 +0000605 PSDMR_SDAM_A15_IS_A5 |\
606 PSDMR_BSMA_A13_A15 |\
607 PSDMR_SDA10_PBI1_A9 |\
608 PSDMR_RFRC_7_CLK |\
609 PSDMR_PRETOACT_2W |\
610 PSDMR_ACTTORW_2W |\
611 PSDMR_BL |\
612 PSDMR_LDOTOPRE_1C |\
613 PSDMR_WRC_2C |\
614 PSDMR_CL_2)
wdenk0f8c9762002-08-19 11:57:05 +0000615
616 /* SDRAM initialization values for 9-column chips
617 */
618#define CFG_OR2_9COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000619 ORxS_BPD_4 |\
620 ORxS_ROWST_PBI1_A6 |\
621 ORxS_NUMR_13)
wdenk0f8c9762002-08-19 11:57:05 +0000622
623#define CFG_LSDMR_9COL (PSDMR_PBI |\
wdenk8bde7f72003-06-27 21:31:46 +0000624 PSDMR_SDAM_A16_IS_A5 |\
625 PSDMR_BSMA_A13_A15 |\
626 PSDMR_SDA10_PBI1_A8 |\
627 PSDMR_RFRC_7_CLK |\
628 PSDMR_PRETOACT_2W |\
629 PSDMR_ACTTORW_2W |\
630 PSDMR_BL |\
631 PSDMR_LDOTOPRE_1C |\
632 PSDMR_WRC_2C |\
633 PSDMR_CL_2)
wdenk0f8c9762002-08-19 11:57:05 +0000634
635#endif /* CFG_INIT_LOCAL_SDRAM */
636
637#endif /* CFG_RAMBOOT */
638
639#endif /* __CONFIG_H */