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wdenk5da627a2003-10-09 20:09:04 +00001/*
2 * (C) Copyright 2003
3 * Thomas.Lange@corelatus.se
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <command.h>
26#include <asm/au1x00.h>
27#include <asm/mipsregs.h>
Jean-Christophe PLAGNIOL-VILLARD5c150102007-11-13 09:11:05 +010028#include <asm/io.h>
wdenk5da627a2003-10-09 20:09:04 +000029
Becky Bruce9973e3c2008-06-09 16:03:40 -050030phys_size_t initdram(int board_type)
wdenk5da627a2003-10-09 20:09:04 +000031{
32 /* Sdram is setup by assembler code */
33 /* If memory could be changed, we should return the true value here */
wdenkff36fd82005-01-09 22:28:56 +000034 return MEM_SIZE*1024*1024;
wdenk5da627a2003-10-09 20:09:04 +000035}
36
37#define BCSR_PCMCIA_PC0DRVEN 0x0010
38#define BCSR_PCMCIA_PC0RST 0x0080
39
Peter Tyser1e3827d2010-04-12 22:28:14 -050040/* In arch/mips/cpu/cpu.c */
wdenk5da627a2003-10-09 20:09:04 +000041void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
42
43int checkboard (void)
44{
wdenkc3d2b4b2005-01-22 18:13:04 +000045#ifdef CONFIG_IDE_PCMCIA
wdenk5da627a2003-10-09 20:09:04 +000046 u16 status;
wdenkff36fd82005-01-09 22:28:56 +000047 volatile u32 *pcmcia_bcsr = (u32*)(DB1XX0_BCSR_ADDR+0x10);
wdenkc3d2b4b2005-01-22 18:13:04 +000048#endif /* CONFIG_IDE_PCMCIA */
wdenkff36fd82005-01-09 22:28:56 +000049 volatile u32 *phy = (u32*)(DB1XX0_BCSR_ADDR+0xC);
wdenk5da627a2003-10-09 20:09:04 +000050 volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
51 u32 proc_id;
52
53 *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
54
Shinya Kuribayashie2ad8422008-05-30 00:53:38 +090055 proc_id = read_c0_prid();
wdenk5da627a2003-10-09 20:09:04 +000056
wdenka2663ea2003-12-07 18:32:37 +000057 switch (proc_id >> 24) {
wdenk5da627a2003-10-09 20:09:04 +000058 case 0:
wdenka2663ea2003-12-07 18:32:37 +000059 puts ("Board: Merlot (DbAu1000)\n");
60 printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n",
61 (proc_id >> 8) & 0xFF, proc_id & 0xFF);
62 break;
63 case 1:
64 puts ("Board: DbAu1500\n");
65 printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n",
66 (proc_id >> 8) & 0xFF, proc_id & 0xFF);
67 break;
68 case 2:
69 puts ("Board: DbAu1100\n");
70 printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n",
71 (proc_id >> 8) & 0xFF, proc_id & 0xFF);
72 break;
wdenkff36fd82005-01-09 22:28:56 +000073 case 3:
74 puts ("Board: DbAu1550\n");
75 printf ("CPU: Au1550, id: 0x%02x, rev: 0x%02x\n",
76 (proc_id >> 8) & 0xFF, proc_id & 0xFF);
77 break;
wdenk5da627a2003-10-09 20:09:04 +000078 default:
wdenka2663ea2003-12-07 18:32:37 +000079 printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
wdenk5da627a2003-10-09 20:09:04 +000080 }
Jean-Christophe PLAGNIOL-VILLARD5c150102007-11-13 09:11:05 +010081
82 set_io_port_base(0);
83
wdenk5da627a2003-10-09 20:09:04 +000084#ifdef CONFIG_IDE_PCMCIA
85 /* Enable 3.3 V on slot 0 ( VCC )
86 No 5V */
87 status = 4;
88 *pcmcia_bcsr = status;
89
90 status |= BCSR_PCMCIA_PC0DRVEN;
91 *pcmcia_bcsr = status;
92 au_sync();
93
94 udelay(300*1000);
95
96 status |= BCSR_PCMCIA_PC0RST;
97 *pcmcia_bcsr = status;
98 au_sync();
99
100 udelay(100*1000);
101
102 /* PCMCIA is on a 36 bit physical address.
103 We need to map it into a 32 bit addresses */
104
105#if 0
106 /* We dont need theese unless we run whole pcmcia package */
107 write_one_tlb(20, /* index */
108 0x01ffe000, /* Pagemask, 16 MB pages */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109 CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */
wdenk5da627a2003-10-09 20:09:04 +0000110 0x3C000017, /* Lo0 */
111 0x3C200017); /* Lo1 */
112
113 write_one_tlb(21, /* index */
114 0x01ffe000, /* Pagemask, 16 MB pages */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115 CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */
wdenk5da627a2003-10-09 20:09:04 +0000116 0x3D000017, /* Lo0 */
117 0x3D200017); /* Lo1 */
wdenk697037f2004-06-09 15:29:49 +0000118#endif /* 0 */
wdenk5da627a2003-10-09 20:09:04 +0000119 write_one_tlb(22, /* index */
120 0x01ffe000, /* Pagemask, 16 MB pages */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121 CONFIG_SYS_PCMCIA_MEM_ADDR, /* Hi */
wdenk5da627a2003-10-09 20:09:04 +0000122 0x3E000017, /* Lo0 */
123 0x3E200017); /* Lo1 */
wdenk697037f2004-06-09 15:29:49 +0000124#endif /* CONFIG_IDE_PCMCIA */
wdenk5da627a2003-10-09 20:09:04 +0000125
126 /* Release reset of ethernet PHY chips */
127 /* Always do this, because linux does not know about it */
128 *phy = 3;
129
130 return 0;
wdenk5da627a2003-10-09 20:09:04 +0000131}