Dave Liu | 5f82043 | 2006-11-03 19:33:44 -0600 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2006 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | */ |
| 12 | |
| 13 | /* |
| 14 | * PCI Configuration space access support for MPC83xx PCI Bridge |
| 15 | */ |
| 16 | #include <asm/mmu.h> |
| 17 | #include <asm/io.h> |
| 18 | #include <common.h> |
| 19 | #include <pci.h> |
| 20 | #include <i2c.h> |
Kim Phillips | 781e026 | 2007-02-28 00:02:04 -0600 | [diff] [blame] | 21 | #if defined(CONFIG_OF_FLAT_TREE) |
| 22 | #include <ft_build.h> |
Jerry Van Baren | 26d02c9 | 2007-07-04 21:27:30 -0400 | [diff] [blame] | 23 | #elif defined(CONFIG_OF_LIBFDT) |
Gerald Van Baren | 213bf8c | 2007-03-31 12:23:51 -0400 | [diff] [blame] | 24 | #include <libfdt.h> |
| 25 | #include <libfdt_env.h> |
| 26 | #endif |
Dave Liu | 5f82043 | 2006-11-03 19:33:44 -0600 | [diff] [blame] | 27 | |
Timur Tabi | be5e618 | 2006-11-03 19:15:00 -0600 | [diff] [blame] | 28 | #include <asm/fsl_i2c.h> |
Dave Liu | 5f82043 | 2006-11-03 19:33:44 -0600 | [diff] [blame] | 29 | |
| 30 | DECLARE_GLOBAL_DATA_PTR; |
| 31 | |
| 32 | #if defined(CONFIG_PCI) |
| 33 | #define PCI_FUNCTION_CONFIG 0x44 |
| 34 | #define PCI_FUNCTION_CFG_LOCK 0x20 |
| 35 | |
| 36 | /* |
| 37 | * Initialize PCI Devices, report devices found |
| 38 | */ |
| 39 | #ifndef CONFIG_PCI_PNP |
| 40 | static struct pci_config_table pci_mpc83xxemds_config_table[] = { |
| 41 | { |
| 42 | PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
| 43 | pci_cfgfunc_config_device, |
| 44 | {PCI_ENET0_IOADDR, |
| 45 | PCI_ENET0_MEMADDR, |
| 46 | PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} |
| 47 | }, |
| 48 | {} |
| 49 | } |
| 50 | #endif |
| 51 | static struct pci_controller hose[] = { |
| 52 | { |
| 53 | #ifndef CONFIG_PCI_PNP |
| 54 | config_table:pci_mpc83xxemds_config_table, |
| 55 | #endif |
| 56 | }, |
| 57 | }; |
| 58 | |
| 59 | /********************************************************************** |
| 60 | * pci_init_board() |
| 61 | *********************************************************************/ |
| 62 | void pci_init_board(void) |
| 63 | #ifdef CONFIG_PCISLAVE |
| 64 | { |
| 65 | u16 reg16; |
| 66 | volatile immap_t *immr; |
| 67 | volatile law83xx_t *pci_law; |
| 68 | volatile pot83xx_t *pci_pot; |
| 69 | volatile pcictrl83xx_t *pci_ctrl; |
| 70 | volatile pciconf83xx_t *pci_conf; |
| 71 | |
Timur Tabi | d239d74 | 2006-11-03 12:00:28 -0600 | [diff] [blame] | 72 | immr = (immap_t *) CFG_IMMR; |
Dave Liu | 5f82043 | 2006-11-03 19:33:44 -0600 | [diff] [blame] | 73 | pci_law = immr->sysconf.pcilaw; |
| 74 | pci_pot = immr->ios.pot; |
| 75 | pci_ctrl = immr->pci_ctrl; |
| 76 | pci_conf = immr->pci_conf; |
| 77 | /* |
| 78 | * Configure PCI Inbound Translation Windows |
| 79 | */ |
| 80 | pci_ctrl[0].pitar0 = 0x0; |
| 81 | pci_ctrl[0].pibar0 = 0x0; |
| 82 | pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP | |
| 83 | PIWAR_WTT_SNOOP | PIWAR_IWS_4K; |
| 84 | |
| 85 | pci_ctrl[0].pitar1 = 0x0; |
| 86 | pci_ctrl[0].pibar1 = 0x0; |
| 87 | pci_ctrl[0].piebar1 = 0x0; |
| 88 | pci_ctrl[0].piwar1 &= ~PIWAR_EN; |
| 89 | |
| 90 | pci_ctrl[0].pitar2 = 0x0; |
| 91 | pci_ctrl[0].pibar2 = 0x0; |
| 92 | pci_ctrl[0].piebar2 = 0x0; |
| 93 | pci_ctrl[0].piwar2 &= ~PIWAR_EN; |
| 94 | |
| 95 | hose[0].first_busno = 0; |
| 96 | hose[0].last_busno = 0xff; |
| 97 | pci_setup_indirect(&hose[0], |
Timur Tabi | d239d74 | 2006-11-03 12:00:28 -0600 | [diff] [blame] | 98 | (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); |
Dave Liu | 5f82043 | 2006-11-03 19:33:44 -0600 | [diff] [blame] | 99 | reg16 = 0xff; |
| 100 | |
| 101 | pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), |
| 102 | PCI_COMMAND, ®16); |
| 103 | reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY; |
| 104 | pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), |
| 105 | PCI_COMMAND, reg16); |
| 106 | |
| 107 | /* |
| 108 | * Clear non-reserved bits in status register. |
| 109 | */ |
| 110 | pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), |
| 111 | PCI_STATUS, 0xffff); |
| 112 | pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0), |
| 113 | PCI_LATENCY_TIMER, 0x80); |
| 114 | |
| 115 | /* |
| 116 | * Unlock configuration lock in PCI function configuration register. |
| 117 | */ |
| 118 | pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), |
| 119 | PCI_FUNCTION_CONFIG, ®16); |
| 120 | reg16 &= ~(PCI_FUNCTION_CFG_LOCK); |
| 121 | pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), |
| 122 | PCI_FUNCTION_CONFIG, reg16); |
| 123 | |
| 124 | printf("Enabled PCI 32bit Agent Mode\n"); |
| 125 | } |
| 126 | #else |
| 127 | { |
| 128 | volatile immap_t *immr; |
| 129 | volatile clk83xx_t *clk; |
| 130 | volatile law83xx_t *pci_law; |
| 131 | volatile pot83xx_t *pci_pot; |
| 132 | volatile pcictrl83xx_t *pci_ctrl; |
| 133 | volatile pciconf83xx_t *pci_conf; |
| 134 | |
| 135 | u8 val8, orig_i2c_bus; |
| 136 | u16 reg16; |
| 137 | u32 val32; |
| 138 | u32 dev; |
| 139 | |
Timur Tabi | d239d74 | 2006-11-03 12:00:28 -0600 | [diff] [blame] | 140 | immr = (immap_t *) CFG_IMMR; |
Dave Liu | 5f82043 | 2006-11-03 19:33:44 -0600 | [diff] [blame] | 141 | clk = (clk83xx_t *) & immr->clk; |
| 142 | pci_law = immr->sysconf.pcilaw; |
| 143 | pci_pot = immr->ios.pot; |
| 144 | pci_ctrl = immr->pci_ctrl; |
| 145 | pci_conf = immr->pci_conf; |
| 146 | /* |
| 147 | * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode |
| 148 | */ |
| 149 | val32 = clk->occr; |
| 150 | udelay(2000); |
| 151 | #if defined(PCI_66M) |
| 152 | clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; |
| 153 | printf("PCI clock is 66MHz\n"); |
| 154 | #elif defined(PCI_33M) |
| 155 | clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 | |
| 156 | OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR; |
| 157 | printf("PCI clock is 33MHz\n"); |
| 158 | #else |
| 159 | clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; |
| 160 | printf("PCI clock is 66MHz\n"); |
| 161 | #endif |
| 162 | udelay(2000); |
| 163 | |
| 164 | /* |
| 165 | * Configure PCI Local Access Windows |
| 166 | */ |
| 167 | pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR; |
| 168 | pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; |
| 169 | |
| 170 | pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR; |
| 171 | pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; |
| 172 | |
| 173 | /* |
| 174 | * Configure PCI Outbound Translation Windows |
| 175 | */ |
| 176 | |
| 177 | /* PCI mem space - prefetch */ |
| 178 | pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK; |
| 179 | pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK; |
| 180 | pci_pot[0].pocmr = |
| 181 | POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK); |
| 182 | |
| 183 | /* PCI mmio - non-prefetch mem space */ |
| 184 | pci_pot[1].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK; |
| 185 | pci_pot[1].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK; |
| 186 | pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); |
| 187 | |
| 188 | /* PCI IO space */ |
| 189 | pci_pot[2].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK; |
| 190 | pci_pot[2].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK; |
| 191 | pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); |
| 192 | |
| 193 | /* |
| 194 | * Configure PCI Inbound Translation Windows |
| 195 | */ |
| 196 | pci_ctrl[0].pitar1 = (CFG_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK; |
| 197 | pci_ctrl[0].pibar1 = (CFG_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK; |
| 198 | pci_ctrl[0].piebar1 = 0x0; |
| 199 | pci_ctrl[0].piwar1 = |
| 200 | PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | |
| 201 | PIWAR_IWS_2G; |
| 202 | |
| 203 | /* |
| 204 | * Assign PIB PMC slot to desired PCI bus |
| 205 | */ |
| 206 | |
Timur Tabi | 9ca880a | 2006-10-31 21:23:16 -0600 | [diff] [blame] | 207 | /* Switch temporarily to I2C bus #2 */ |
| 208 | orig_i2c_bus = i2c_get_bus_num(); |
Jerry Van Baren | 26d02c9 | 2007-07-04 21:27:30 -0400 | [diff] [blame] | 209 | i2c_set_bus_num(1); |
Dave Liu | 5f82043 | 2006-11-03 19:33:44 -0600 | [diff] [blame] | 210 | |
| 211 | val8 = 0; |
| 212 | i2c_write(0x23, 0x6, 1, &val8, 1); |
| 213 | i2c_write(0x23, 0x7, 1, &val8, 1); |
| 214 | val8 = 0xff; |
| 215 | i2c_write(0x23, 0x2, 1, &val8, 1); |
| 216 | i2c_write(0x23, 0x3, 1, &val8, 1); |
| 217 | |
| 218 | val8 = 0; |
| 219 | i2c_write(0x26, 0x6, 1, &val8, 1); |
| 220 | val8 = 0x34; |
| 221 | i2c_write(0x26, 0x7, 1, &val8, 1); |
| 222 | |
| 223 | val8 = 0xf3; /*PMC1, PMC2, PMC3 slot to PCI bus */ |
| 224 | i2c_write(0x26, 0x2, 1, &val8, 1); |
| 225 | val8 = 0xff; |
| 226 | i2c_write(0x26, 0x3, 1, &val8, 1); |
| 227 | |
| 228 | val8 = 0; |
| 229 | i2c_write(0x27, 0x6, 1, &val8, 1); |
| 230 | i2c_write(0x27, 0x7, 1, &val8, 1); |
| 231 | val8 = 0xff; |
| 232 | i2c_write(0x27, 0x2, 1, &val8, 1); |
| 233 | val8 = 0xef; |
| 234 | i2c_write(0x27, 0x3, 1, &val8, 1); |
| 235 | asm("eieio"); |
| 236 | |
Timur Tabi | 9ca880a | 2006-10-31 21:23:16 -0600 | [diff] [blame] | 237 | /* Reset to original I2C bus */ |
Timur Tabi | be5e618 | 2006-11-03 19:15:00 -0600 | [diff] [blame] | 238 | i2c_set_bus_num(orig_i2c_bus); |
Kim Phillips | bf0b542 | 2006-11-01 00:10:40 -0600 | [diff] [blame] | 239 | |
Dave Liu | 5f82043 | 2006-11-03 19:33:44 -0600 | [diff] [blame] | 240 | /* |
| 241 | * Release PCI RST Output signal |
| 242 | */ |
| 243 | udelay(2000); |
| 244 | pci_ctrl[0].gcr = 1; |
| 245 | udelay(2000); |
| 246 | |
| 247 | hose[0].first_busno = 0; |
| 248 | hose[0].last_busno = 0xff; |
| 249 | |
| 250 | /* PCI memory prefetch space */ |
| 251 | pci_set_region(hose[0].regions + 0, |
| 252 | CFG_PCI_MEM_BASE, |
| 253 | CFG_PCI_MEM_PHYS, |
| 254 | CFG_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); |
| 255 | |
| 256 | /* PCI memory space */ |
| 257 | pci_set_region(hose[0].regions + 1, |
| 258 | CFG_PCI_MMIO_BASE, |
| 259 | CFG_PCI_MMIO_PHYS, CFG_PCI_MMIO_SIZE, PCI_REGION_MEM); |
| 260 | |
| 261 | /* PCI IO space */ |
| 262 | pci_set_region(hose[0].regions + 2, |
| 263 | CFG_PCI_IO_BASE, |
| 264 | CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO); |
| 265 | |
| 266 | /* System memory space */ |
| 267 | pci_set_region(hose[0].regions + 3, |
| 268 | CFG_PCI_SLV_MEM_LOCAL, |
| 269 | CFG_PCI_SLV_MEM_BUS, |
| 270 | CFG_PCI_SLV_MEM_SIZE, |
| 271 | PCI_REGION_MEM | PCI_REGION_MEMORY); |
| 272 | |
| 273 | hose[0].region_count = 4; |
| 274 | |
| 275 | pci_setup_indirect(&hose[0], |
Timur Tabi | d239d74 | 2006-11-03 12:00:28 -0600 | [diff] [blame] | 276 | (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); |
Dave Liu | 5f82043 | 2006-11-03 19:33:44 -0600 | [diff] [blame] | 277 | |
| 278 | pci_register_hose(hose); |
| 279 | |
| 280 | /* |
| 281 | * Write command register |
| 282 | */ |
| 283 | reg16 = 0xff; |
| 284 | dev = PCI_BDF(0, 0, 0); |
| 285 | pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, ®16); |
| 286 | reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
| 287 | pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16); |
| 288 | |
| 289 | /* |
| 290 | * Clear non-reserved bits in status register. |
| 291 | */ |
| 292 | pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff); |
| 293 | pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80); |
| 294 | pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08); |
| 295 | |
| 296 | printf("PCI 32bit bus on PMC1 & PMC2 & PMC3\n"); |
| 297 | |
| 298 | /* |
| 299 | * Hose scan. |
| 300 | */ |
| 301 | hose->last_busno = pci_hose_scan(hose); |
| 302 | } |
| 303 | #endif /* CONFIG_PCISLAVE */ |
Kim Phillips | bf0b542 | 2006-11-01 00:10:40 -0600 | [diff] [blame] | 304 | |
Gerald Van Baren | 213bf8c | 2007-03-31 12:23:51 -0400 | [diff] [blame] | 305 | #if defined(CONFIG_OF_LIBFDT) |
| 306 | void |
| 307 | ft_pci_setup(void *blob, bd_t *bd) |
| 308 | { |
| 309 | int nodeoffset; |
| 310 | int err; |
| 311 | int tmp[2]; |
| 312 | |
Kim Phillips | f57ac7a | 2007-07-25 19:25:22 -0500 | [diff] [blame] | 313 | nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500"); |
Gerald Van Baren | 213bf8c | 2007-03-31 12:23:51 -0400 | [diff] [blame] | 314 | if (nodeoffset >= 0) { |
| 315 | tmp[0] = cpu_to_be32(hose[0].first_busno); |
| 316 | tmp[1] = cpu_to_be32(hose[0].last_busno); |
Kim Phillips | f57ac7a | 2007-07-25 19:25:22 -0500 | [diff] [blame] | 317 | err = fdt_setprop(blob, nodeoffset, "bus-range", tmp, sizeof(tmp)); |
Gerald Van Baren | 213bf8c | 2007-03-31 12:23:51 -0400 | [diff] [blame] | 318 | } |
| 319 | } |
Jerry Van Baren | 26d02c9 | 2007-07-04 21:27:30 -0400 | [diff] [blame] | 320 | #elif defined(CONFIG_OF_FLAT_TREE) |
Kim Phillips | bf0b542 | 2006-11-01 00:10:40 -0600 | [diff] [blame] | 321 | void |
| 322 | ft_pci_setup(void *blob, bd_t *bd) |
| 323 | { |
Jerry Van Baren | 26d02c9 | 2007-07-04 21:27:30 -0400 | [diff] [blame] | 324 | u32 *p; |
| 325 | int len; |
Kim Phillips | bf0b542 | 2006-11-01 00:10:40 -0600 | [diff] [blame] | 326 | |
Jerry Van Baren | 26d02c9 | 2007-07-04 21:27:30 -0400 | [diff] [blame] | 327 | p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); |
| 328 | if (p != NULL) { |
Kim Phillips | bf0b542 | 2006-11-01 00:10:40 -0600 | [diff] [blame] | 329 | p[0] = hose[0].first_busno; |
| 330 | p[1] = hose[0].last_busno; |
Jerry Van Baren | 26d02c9 | 2007-07-04 21:27:30 -0400 | [diff] [blame] | 331 | } |
Kim Phillips | bf0b542 | 2006-11-01 00:10:40 -0600 | [diff] [blame] | 332 | } |
| 333 | #endif /* CONFIG_OF_FLAT_TREE */ |
Dave Liu | 5f82043 | 2006-11-03 19:33:44 -0600 | [diff] [blame] | 334 | #endif /* CONFIG_PCI */ |