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Michal Simek6d034092018-03-28 14:37:47 +02001/*
2 * Configuration for Xilinx ZynqMP zcu100
3 *
4 * (C) Copyright 2015 - 2016 Xilinx, Inc.
5 * Michal Simek <michal.simek@xilinx.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#ifndef __CONFIG_ZYNQMP_ZCU100_H
11#define __CONFIG_ZYNQMP_ZCU100_H
12
13/* FIXME Will go away soon */
14#define CONFIG_SYS_I2C_MAX_HOPS 1
15#define CONFIG_SYS_NUM_I2C_BUSES 9
16#define CONFIG_SYS_I2C_BUSES { \
17 {0, {I2C_NULL_HOP} }, \
18 {0, {{I2C_MUX_PCA9548, 0x75, 0} } }, \
19 {0, {{I2C_MUX_PCA9548, 0x75, 1} } }, \
20 {0, {{I2C_MUX_PCA9548, 0x75, 2} } }, \
21 {0, {{I2C_MUX_PCA9548, 0x75, 3} } }, \
22 {0, {{I2C_MUX_PCA9548, 0x75, 4} } }, \
23 {0, {{I2C_MUX_PCA9548, 0x75, 5} } }, \
24 {0, {{I2C_MUX_PCA9548, 0x75, 6} } }, \
25 {0, {{I2C_MUX_PCA9548, 0x75, 7} } }, \
26 }
27
28#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
29 ZYNQMP_USB1_XHCI_BASEADDR}
30
31#define CONFIG_USB_HOST_ETHER
32#define CONFIG_USB_ETHER_ASIX
33
34#include <configs/xilinx_zynqmp.h>
35
36#endif /* __CONFIG_ZYNQMP_ZCU100_H */