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Kumar Gala0db37dc2008-01-17 01:01:09 -06001/*
2 * Copyright 2008 Freescale Semiconductor, Inc.
3 *
4 * (C) Copyright 2000
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27#include <asm/mmu.h>
28
29struct fsl_e_tlb_entry tlb_table[] = {
30 /* TLB 0 - for temp stack in cache */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020031 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
Kumar Gala0db37dc2008-01-17 01:01:09 -060032 MAS3_SX|MAS3_SW|MAS3_SR, 0,
33 0, 0, BOOKE_PAGESZ_4K, 0),
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020034 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
Kumar Gala0db37dc2008-01-17 01:01:09 -060035 MAS3_SX|MAS3_SW|MAS3_SR, 0,
36 0, 0, BOOKE_PAGESZ_4K, 0),
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020037 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
Kumar Gala0db37dc2008-01-17 01:01:09 -060038 MAS3_SX|MAS3_SW|MAS3_SR, 0,
39 0, 0, BOOKE_PAGESZ_4K, 0),
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
Kumar Gala0db37dc2008-01-17 01:01:09 -060041 MAS3_SX|MAS3_SW|MAS3_SR, 0,
42 0, 0, BOOKE_PAGESZ_4K, 0),
43
44 /*
45 * TLB 0: 16M Non-cacheable, guarded
46 * 0xff000000 16M FLASH
47 * Out of reset this entry is only 4K.
48 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049 SET_TLB_ENTRY(1, CONFIG_SYS_BOOT_BLOCK, CONFIG_SYS_BOOT_BLOCK,
Kumar Gala0db37dc2008-01-17 01:01:09 -060050 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
51 0, 0, BOOKE_PAGESZ_16M, 1),
52
53 /*
54 * TLB 1: 1G Non-cacheable, guarded
55 * 0x80000000 1G PCI1/PCIE 8,9,a,b
56 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057 SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS, CONFIG_SYS_PCI_PHYS,
Kumar Gala0db37dc2008-01-17 01:01:09 -060058 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
59 0, 1, BOOKE_PAGESZ_1G, 1),
60
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061#ifdef CONFIG_SYS_RIO_MEM_PHYS
Kumar Gala0db37dc2008-01-17 01:01:09 -060062 /*
63 * TLB 2: 256M Non-cacheable, guarded
64 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065 SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
Kumar Gala0db37dc2008-01-17 01:01:09 -060066 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
67 0, 2, BOOKE_PAGESZ_256M, 1),
68
69 /*
70 * TLB 3: 256M Non-cacheable, guarded
71 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072 SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
Kumar Gala0db37dc2008-01-17 01:01:09 -060073 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
74 0, 3, BOOKE_PAGESZ_256M, 1),
75#endif
76 /*
77 * TLB 5: 64M Non-cacheable, guarded
78 * 0xe000_0000 1M CCSRBAR
79 * 0xe200_0000 1M PCI1 IO
80 * 0xe210_0000 1M PCI2 IO
81 * 0xe300_0000 1M PCIe IO
82 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
Kumar Gala0db37dc2008-01-17 01:01:09 -060084 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
85 0, 5, BOOKE_PAGESZ_64M, 1),
86
87 /*
88 * TLB 6: 64M Cacheable, non-guarded
89 * 0xf000_0000 64M LBC SDRAM
90 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091 SET_TLB_ENTRY(1, CONFIG_SYS_LBC_CACHE_BASE, CONFIG_SYS_LBC_CACHE_BASE,
Kumar Gala0db37dc2008-01-17 01:01:09 -060092 MAS3_SX|MAS3_SW|MAS3_SR, 0,
93 0, 6, BOOKE_PAGESZ_64M, 1),
94
95 /*
96 * TLB 7: 64M Non-cacheable, guarded
97 * 0xf8000000 64M CADMUS registers, relocated L2SRAM
98 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099 SET_TLB_ENTRY(1, CONFIG_SYS_LBC_NONCACHE_BASE, CONFIG_SYS_LBC_NONCACHE_BASE,
Kumar Gala0db37dc2008-01-17 01:01:09 -0600100 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
101 0, 7, BOOKE_PAGESZ_64M, 1),
102};
103
104int num_tlb_entries = ARRAY_SIZE(tlb_table);