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wdenk47d1a6e2002-11-03 00:01:44 +00001/*
2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2001 Josh Huber <huber@mclx.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/* U-Boot - Startup Code for PowerPC based Embedded Boards
27 *
28 *
29 * The processor starts at 0xfff00100 and the code is executed
30 * from flash. The code is organized to be at an other address
31 * in memory, but as long we don't jump around before relocating.
32 * board_init lies at a quite high address and when the cpu has
33 * jumped there, everything is ok.
34 */
35#include <config.h>
36#include <74xx_7xx.h>
37#include <version.h>
38
39#include <ppc_asm.tmpl>
40#include <ppc_defs.h>
41
42#include <asm/cache.h>
43#include <asm/mmu.h>
44
wdenk3a473b22004-01-03 00:43:19 +000045#if !defined(CONFIG_DB64360) && \
stroese0912e482004-12-16 18:10:54 +000046 !defined(CONFIG_DB64460) && \
Stefan Roese1eac2a72006-11-29 15:42:37 +010047 !defined(CONFIG_CPCI750) && \
48 !defined(CONFIG_P3Mx)
wdenk47d1a6e2002-11-03 00:01:44 +000049#include <galileo/gt64260R.h>
wdenk3a473b22004-01-03 00:43:19 +000050#endif
wdenk47d1a6e2002-11-03 00:01:44 +000051
52#ifndef CONFIG_IDENT_STRING
53#define CONFIG_IDENT_STRING ""
54#endif
55
56/* We don't want the MMU yet.
57*/
58#undef MSR_KERNEL
59/* Machine Check and Recoverable Interr. */
60#define MSR_KERNEL ( MSR_ME | MSR_RI )
61
62/*
63 * Set up GOT: Global Offset Table
64 *
65 * Use r14 to access the GOT
66 */
67 START_GOT
68 GOT_ENTRY(_GOT2_TABLE_)
69 GOT_ENTRY(_FIXUP_TABLE_)
70
71 GOT_ENTRY(_start)
72 GOT_ENTRY(_start_of_vectors)
73 GOT_ENTRY(_end_of_vectors)
74 GOT_ENTRY(transfer_to_handler)
75
wdenk3b57fe02003-05-30 12:48:29 +000076 GOT_ENTRY(__init_end)
wdenk47d1a6e2002-11-03 00:01:44 +000077 GOT_ENTRY(_end)
wdenk5d232d02003-05-22 22:52:13 +000078 GOT_ENTRY(__bss_start)
wdenk47d1a6e2002-11-03 00:01:44 +000079 END_GOT
80
81/*
82 * r3 - 1st arg to board_init(): IMMP pointer
83 * r4 - 2nd arg to board_init(): boot flag
84 */
85 .text
86 .long 0x27051956 /* U-Boot Magic Number */
87 .globl version_string
88version_string:
89 .ascii U_BOOT_VERSION
90 .ascii " (", __DATE__, " - ", __TIME__, ")"
91 .ascii CONFIG_IDENT_STRING, "\0"
92
93 . = EXC_OFF_SYS_RESET
94 .globl _start
95_start:
96 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
97 b boot_cold
98 sync
99
100 . = EXC_OFF_SYS_RESET + 0x10
101
102 .globl _start_warm
103_start_warm:
104 li r21, BOOTFLAG_WARM /* Software reboot */
105 b boot_warm
106 sync
107
108 /* the boot code is located below the exception table */
109
110 .globl _start_of_vectors
111_start_of_vectors:
112
113/* Machine check */
114 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
115
116/* Data Storage exception. "Never" generated on the 860. */
117 STD_EXCEPTION(0x300, DataStorage, UnknownException)
118
119/* Instruction Storage exception. "Never" generated on the 860. */
120 STD_EXCEPTION(0x400, InstStorage, UnknownException)
121
122/* External Interrupt exception. */
123 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
124
125/* Alignment exception. */
126 . = 0x600
127Alignment:
Rafal Jaworowski02032e82007-06-22 14:58:04 +0200128 EXCEPTION_PROLOG(SRR0, SRR1)
wdenk47d1a6e2002-11-03 00:01:44 +0000129 mfspr r4,DAR
130 stw r4,_DAR(r21)
131 mfspr r5,DSISR
132 stw r5,_DSISR(r21)
133 addi r3,r1,STACK_FRAME_OVERHEAD
134 li r20,MSR_KERNEL
135 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
136 lwz r6,GOT(transfer_to_handler)
137 mtlr r6
138 blrl
139.L_Alignment:
140 .long AlignmentException - _start + EXC_OFF_SYS_RESET
141 .long int_return - _start + EXC_OFF_SYS_RESET
142
143/* Program check exception */
144 . = 0x700
145ProgramCheck:
Rafal Jaworowski02032e82007-06-22 14:58:04 +0200146 EXCEPTION_PROLOG(SRR0, SRR1)
wdenk47d1a6e2002-11-03 00:01:44 +0000147 addi r3,r1,STACK_FRAME_OVERHEAD
148 li r20,MSR_KERNEL
149 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
150 lwz r6,GOT(transfer_to_handler)
151 mtlr r6
152 blrl
153.L_ProgramCheck:
154 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
155 .long int_return - _start + EXC_OFF_SYS_RESET
156
157 /* No FPU on MPC8xx. This exception is not supposed to happen.
158 */
159 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
160
161 /* I guess we could implement decrementer, and may have
162 * to someday for timekeeping.
163 */
164 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
165 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
166 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
wdenk27b207f2003-07-24 23:38:38 +0000167 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
wdenk47d1a6e2002-11-03 00:01:44 +0000168 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
169
170 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
171 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
172
wdenk8bde7f72003-06-27 21:31:46 +0000173 /*
174 * On the MPC8xx, this is a software emulation interrupt. It
175 * occurs for all unimplemented and illegal instructions.
wdenk47d1a6e2002-11-03 00:01:44 +0000176 */
177 STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
178
179 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
180 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
181 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
182 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
183
184 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
185 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
186 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
187 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
188 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
189 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
190 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
191
192 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
193 STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
194 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
195 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
196
197 .globl _end_of_vectors
198_end_of_vectors:
199
200 . = 0x2000
201
202boot_cold:
203boot_warm:
204 /* disable everything */
205 li r0, 0
206 mtspr HID0, r0
207 sync
208 mtmsr 0
209 bl invalidate_bats
210 sync
211
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#ifdef CONFIG_SYS_L2
wdenk47d1a6e2002-11-03 00:01:44 +0000213 /* init the L2 cache */
214 addis r3, r0, L2_INIT@h
215 ori r3, r3, L2_INIT@l
216 sync
217 mtspr l2cr, r3
218#endif
219#if defined(CONFIG_ALTIVEC) && defined(CONFIG_74xx)
220 .long 0x7e00066c
221 /*
wdenk8bde7f72003-06-27 21:31:46 +0000222 * dssall instruction, gas doesn't have it yet
223 * ...for altivec, data stream stop all this probably
224 * isn't needed unless we warm (software) reboot U-Boot
wdenk47d1a6e2002-11-03 00:01:44 +0000225 */
226#endif
227
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#ifdef CONFIG_SYS_L2
wdenk47d1a6e2002-11-03 00:01:44 +0000229 /* invalidate the L2 cache */
230 bl l2cache_invalidate
231 sync
232#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#ifdef CONFIG_SYS_BOARD_ASM_INIT
wdenk47d1a6e2002-11-03 00:01:44 +0000234 /* do early init */
235 bl board_asm_init
236#endif
237
238 /*
239 * Calculate absolute address in FLASH and jump there
240 *------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241 lis r3, CONFIG_SYS_MONITOR_BASE@h
242 ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
wdenk47d1a6e2002-11-03 00:01:44 +0000243 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
244 mtlr r3
245 blr
246
247in_flash:
248 /* let the C-code set up the rest */
249 /* */
250 /* Be careful to keep code relocatable ! */
251 /*------------------------------------------------------*/
252
253 /* perform low-level init */
254 /* sdram init, galileo init, etc */
255 /* r3: NHR bit from HID0 */
256
257 /* setup the bats */
258 bl setup_bats
259 sync
260
261 /*
262 * Cache must be enabled here for stack-in-cache trick.
263 * This means we need to enable the BATS.
264 * This means:
wdenk8bde7f72003-06-27 21:31:46 +0000265 * 1) for the EVB, original gt regs need to be mapped
wdenk47d1a6e2002-11-03 00:01:44 +0000266 * 2) need to have an IBAT for the 0xf region,
267 * we are running there!
wdenk8bde7f72003-06-27 21:31:46 +0000268 * Cache should be turned on after BATs, since by default
269 * everything is write-through.
270 * The init-mem BAT can be reused after reloc. The old
271 * gt-regs BAT can be reused after board_init_f calls
wdenkc837dcb2004-01-20 23:12:12 +0000272 * board_early_init_f (EVB only).
wdenk8bde7f72003-06-27 21:31:46 +0000273 */
Stefan Roese1eac2a72006-11-29 15:42:37 +0100274#if !defined(CONFIG_BAB7xx) && !defined(CONFIG_ELPPC) && !defined(CONFIG_P3Mx)
wdenk47d1a6e2002-11-03 00:01:44 +0000275 /* enable address translation */
276 bl enable_addr_trans
277 sync
278
279 /* enable and invalidate the data cache */
280 bl l1dcache_enable
281 sync
282#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#ifdef CONFIG_SYS_INIT_RAM_LOCK
wdenk47d1a6e2002-11-03 00:01:44 +0000284 bl lock_ram_in_cache
285 sync
286#endif
287
288 /* set up the stack pointer in our newly created
289 * cache-ram (r1) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
291 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
wdenk47d1a6e2002-11-03 00:01:44 +0000292
293 li r0, 0 /* Make room for stack frame header and */
294 stwu r0, -4(r1) /* clear final stack frame so that */
295 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
296
297 GET_GOT /* initialize GOT access */
298
299 /* run low-level CPU init code (from Flash) */
300 bl cpu_init_f
301 sync
302
303 mr r3, r21
304
305 /* r3: BOOTFLAG */
306 /* run 1st part of board init code (from Flash) */
307 bl board_init_f
308 sync
309
310 /* NOTREACHED */
311
312 .globl invalidate_bats
313invalidate_bats:
314 /* invalidate BATs */
315 mtspr IBAT0U, r0
316 mtspr IBAT1U, r0
317 mtspr IBAT2U, r0
318 mtspr IBAT3U, r0
Becky Bruce31d82672008-05-08 19:02:12 -0500319#ifdef CONFIG_HIGH_BATS
wdenk72755c72003-06-20 23:10:58 +0000320 mtspr IBAT4U, r0
321 mtspr IBAT5U, r0
322 mtspr IBAT6U, r0
323 mtspr IBAT7U, r0
324#endif
wdenk47d1a6e2002-11-03 00:01:44 +0000325 isync
326 mtspr DBAT0U, r0
327 mtspr DBAT1U, r0
328 mtspr DBAT2U, r0
329 mtspr DBAT3U, r0
Becky Bruce31d82672008-05-08 19:02:12 -0500330#ifdef CONFIG_HIGH_BATS
wdenk8bde7f72003-06-27 21:31:46 +0000331 mtspr DBAT4U, r0
332 mtspr DBAT5U, r0
333 mtspr DBAT6U, r0
334 mtspr DBAT7U, r0
wdenk72755c72003-06-20 23:10:58 +0000335#endif
wdenk47d1a6e2002-11-03 00:01:44 +0000336 isync
337 sync
338 blr
339
340 /* setup_bats - set them up to some initial state */
341 .globl setup_bats
342setup_bats:
343 addis r0, r0, 0x0000
344
345 /* IBAT 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346 addis r4, r0, CONFIG_SYS_IBAT0L@h
347 ori r4, r4, CONFIG_SYS_IBAT0L@l
348 addis r3, r0, CONFIG_SYS_IBAT0U@h
349 ori r3, r3, CONFIG_SYS_IBAT0U@l
wdenk47d1a6e2002-11-03 00:01:44 +0000350 mtspr IBAT0L, r4
351 mtspr IBAT0U, r3
352 isync
353
354 /* DBAT 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355 addis r4, r0, CONFIG_SYS_DBAT0L@h
356 ori r4, r4, CONFIG_SYS_DBAT0L@l
357 addis r3, r0, CONFIG_SYS_DBAT0U@h
358 ori r3, r3, CONFIG_SYS_DBAT0U@l
wdenk47d1a6e2002-11-03 00:01:44 +0000359 mtspr DBAT0L, r4
360 mtspr DBAT0U, r3
361 isync
362
363 /* IBAT 1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364 addis r4, r0, CONFIG_SYS_IBAT1L@h
365 ori r4, r4, CONFIG_SYS_IBAT1L@l
366 addis r3, r0, CONFIG_SYS_IBAT1U@h
367 ori r3, r3, CONFIG_SYS_IBAT1U@l
wdenk47d1a6e2002-11-03 00:01:44 +0000368 mtspr IBAT1L, r4
369 mtspr IBAT1U, r3
370 isync
371
372 /* DBAT 1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373 addis r4, r0, CONFIG_SYS_DBAT1L@h
374 ori r4, r4, CONFIG_SYS_DBAT1L@l
375 addis r3, r0, CONFIG_SYS_DBAT1U@h
376 ori r3, r3, CONFIG_SYS_DBAT1U@l
wdenk47d1a6e2002-11-03 00:01:44 +0000377 mtspr DBAT1L, r4
378 mtspr DBAT1U, r3
379 isync
380
381 /* IBAT 2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382 addis r4, r0, CONFIG_SYS_IBAT2L@h
383 ori r4, r4, CONFIG_SYS_IBAT2L@l
384 addis r3, r0, CONFIG_SYS_IBAT2U@h
385 ori r3, r3, CONFIG_SYS_IBAT2U@l
wdenk47d1a6e2002-11-03 00:01:44 +0000386 mtspr IBAT2L, r4
387 mtspr IBAT2U, r3
388 isync
389
390 /* DBAT 2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391 addis r4, r0, CONFIG_SYS_DBAT2L@h
392 ori r4, r4, CONFIG_SYS_DBAT2L@l
393 addis r3, r0, CONFIG_SYS_DBAT2U@h
394 ori r3, r3, CONFIG_SYS_DBAT2U@l
wdenk47d1a6e2002-11-03 00:01:44 +0000395 mtspr DBAT2L, r4
396 mtspr DBAT2U, r3
397 isync
398
399 /* IBAT 3 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200400 addis r4, r0, CONFIG_SYS_IBAT3L@h
401 ori r4, r4, CONFIG_SYS_IBAT3L@l
402 addis r3, r0, CONFIG_SYS_IBAT3U@h
403 ori r3, r3, CONFIG_SYS_IBAT3U@l
wdenk47d1a6e2002-11-03 00:01:44 +0000404 mtspr IBAT3L, r4
405 mtspr IBAT3U, r3
406 isync
407
408 /* DBAT 3 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200409 addis r4, r0, CONFIG_SYS_DBAT3L@h
410 ori r4, r4, CONFIG_SYS_DBAT3L@l
411 addis r3, r0, CONFIG_SYS_DBAT3U@h
412 ori r3, r3, CONFIG_SYS_DBAT3U@l
wdenk47d1a6e2002-11-03 00:01:44 +0000413 mtspr DBAT3L, r4
414 mtspr DBAT3U, r3
415 isync
416
Becky Bruce31d82672008-05-08 19:02:12 -0500417#ifdef CONFIG_HIGH_BATS
wdenk72755c72003-06-20 23:10:58 +0000418 /* IBAT 4 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200419 addis r4, r0, CONFIG_SYS_IBAT4L@h
420 ori r4, r4, CONFIG_SYS_IBAT4L@l
421 addis r3, r0, CONFIG_SYS_IBAT4U@h
422 ori r3, r3, CONFIG_SYS_IBAT4U@l
wdenk8bde7f72003-06-27 21:31:46 +0000423 mtspr IBAT4L, r4
424 mtspr IBAT4U, r3
425 isync
wdenk72755c72003-06-20 23:10:58 +0000426
427 /* DBAT 4 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200428 addis r4, r0, CONFIG_SYS_DBAT4L@h
429 ori r4, r4, CONFIG_SYS_DBAT4L@l
430 addis r3, r0, CONFIG_SYS_DBAT4U@h
431 ori r3, r3, CONFIG_SYS_DBAT4U@l
wdenk8bde7f72003-06-27 21:31:46 +0000432 mtspr DBAT4L, r4
433 mtspr DBAT4U, r3
434 isync
wdenk72755c72003-06-20 23:10:58 +0000435
wdenk8bde7f72003-06-27 21:31:46 +0000436 /* IBAT 5 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200437 addis r4, r0, CONFIG_SYS_IBAT5L@h
438 ori r4, r4, CONFIG_SYS_IBAT5L@l
439 addis r3, r0, CONFIG_SYS_IBAT5U@h
440 ori r3, r3, CONFIG_SYS_IBAT5U@l
wdenk8bde7f72003-06-27 21:31:46 +0000441 mtspr IBAT5L, r4
442 mtspr IBAT5U, r3
443 isync
wdenk72755c72003-06-20 23:10:58 +0000444
445 /* DBAT 5 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200446 addis r4, r0, CONFIG_SYS_DBAT5L@h
447 ori r4, r4, CONFIG_SYS_DBAT5L@l
448 addis r3, r0, CONFIG_SYS_DBAT5U@h
449 ori r3, r3, CONFIG_SYS_DBAT5U@l
wdenk8bde7f72003-06-27 21:31:46 +0000450 mtspr DBAT5L, r4
451 mtspr DBAT5U, r3
452 isync
wdenk72755c72003-06-20 23:10:58 +0000453
wdenk8bde7f72003-06-27 21:31:46 +0000454 /* IBAT 6 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200455 addis r4, r0, CONFIG_SYS_IBAT6L@h
456 ori r4, r4, CONFIG_SYS_IBAT6L@l
457 addis r3, r0, CONFIG_SYS_IBAT6U@h
458 ori r3, r3, CONFIG_SYS_IBAT6U@l
wdenk8bde7f72003-06-27 21:31:46 +0000459 mtspr IBAT6L, r4
460 mtspr IBAT6U, r3
461 isync
wdenk72755c72003-06-20 23:10:58 +0000462
463 /* DBAT 6 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200464 addis r4, r0, CONFIG_SYS_DBAT6L@h
465 ori r4, r4, CONFIG_SYS_DBAT6L@l
466 addis r3, r0, CONFIG_SYS_DBAT6U@h
467 ori r3, r3, CONFIG_SYS_DBAT6U@l
wdenk8bde7f72003-06-27 21:31:46 +0000468 mtspr DBAT6L, r4
469 mtspr DBAT6U, r3
470 isync
wdenk72755c72003-06-20 23:10:58 +0000471
wdenk8bde7f72003-06-27 21:31:46 +0000472 /* IBAT 7 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200473 addis r4, r0, CONFIG_SYS_IBAT7L@h
474 ori r4, r4, CONFIG_SYS_IBAT7L@l
475 addis r3, r0, CONFIG_SYS_IBAT7U@h
476 ori r3, r3, CONFIG_SYS_IBAT7U@l
wdenk8bde7f72003-06-27 21:31:46 +0000477 mtspr IBAT7L, r4
478 mtspr IBAT7U, r3
479 isync
wdenk72755c72003-06-20 23:10:58 +0000480
481 /* DBAT 7 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200482 addis r4, r0, CONFIG_SYS_DBAT7L@h
483 ori r4, r4, CONFIG_SYS_DBAT7L@l
484 addis r3, r0, CONFIG_SYS_DBAT7U@h
485 ori r3, r3, CONFIG_SYS_DBAT7U@l
wdenk8bde7f72003-06-27 21:31:46 +0000486 mtspr DBAT7L, r4
487 mtspr DBAT7U, r3
488 isync
wdenk72755c72003-06-20 23:10:58 +0000489#endif
490
wdenk47d1a6e2002-11-03 00:01:44 +0000491 /* bats are done, now invalidate the TLBs */
492
493 addis r3, 0, 0x0000
494 addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */
495
496 isync
497
498tlblp:
499 tlbie r3
500 sync
501 addi r3, r3, 0x1000
502 cmp 0, 0, r3, r5
503 blt tlblp
504
505 blr
506
507 .globl enable_addr_trans
508enable_addr_trans:
509 /* enable address translation */
510 mfmsr r5
511 ori r5, r5, (MSR_IR | MSR_DR)
512 mtmsr r5
513 isync
514 blr
515
516 .globl disable_addr_trans
517disable_addr_trans:
518 /* disable address translation */
519 mflr r4
520 mfmsr r3
521 andi. r0, r3, (MSR_IR | MSR_DR)
522 beqlr
523 andc r3, r3, r0
524 mtspr SRR0, r4
525 mtspr SRR1, r3
526 rfi
527
528/*
529 * This code finishes saving the registers to the exception frame
530 * and jumps to the appropriate handler for the exception.
531 * Register r21 is pointer into trap frame, r1 has new stack pointer.
532 */
533 .globl transfer_to_handler
534transfer_to_handler:
535 stw r22,_NIP(r21)
536 lis r22,MSR_POW@h
537 andc r23,r23,r22
538 stw r23,_MSR(r21)
539 SAVE_GPR(7, r21)
540 SAVE_4GPRS(8, r21)
541 SAVE_8GPRS(12, r21)
542 SAVE_8GPRS(24, r21)
543 mflr r23
544 andi. r24,r23,0x3f00 /* get vector offset */
545 stw r24,TRAP(r21)
546 li r22,0
547 stw r22,RESULT(r21)
548 mtspr SPRG2,r22 /* r1 is now kernel sp */
549 lwz r24,0(r23) /* virtual address of handler */
550 lwz r23,4(r23) /* where to go when done */
551 mtspr SRR0,r24
552 mtspr SRR1,r20
553 mtlr r23
554 SYNC
555 rfi /* jump to handler, enable MMU */
556
557int_return:
558 mfmsr r28 /* Disable interrupts */
559 li r4,0
560 ori r4,r4,MSR_EE
561 andc r28,r28,r4
562 SYNC /* Some chip revs need this... */
563 mtmsr r28
564 SYNC
565 lwz r2,_CTR(r1)
566 lwz r0,_LINK(r1)
567 mtctr r2
568 mtlr r0
569 lwz r2,_XER(r1)
570 lwz r0,_CCR(r1)
571 mtspr XER,r2
572 mtcrf 0xFF,r0
573 REST_10GPRS(3, r1)
574 REST_10GPRS(13, r1)
575 REST_8GPRS(23, r1)
576 REST_GPR(31, r1)
577 lwz r2,_NIP(r1) /* Restore environment */
578 lwz r0,_MSR(r1)
579 mtspr SRR0,r2
580 mtspr SRR1,r0
581 lwz r0,GPR0(r1)
582 lwz r2,GPR2(r1)
583 lwz r1,GPR1(r1)
584 SYNC
585 rfi
586
587 .globl dc_read
588dc_read:
589 blr
590
591 .globl get_pvr
592get_pvr:
593 mfspr r3, PVR
594 blr
595
596/*-----------------------------------------------------------------------*/
597/*
598 * void relocate_code (addr_sp, gd, addr_moni)
599 *
600 * This "function" does not return, instead it continues in RAM
601 * after relocating the monitor code.
602 *
603 * r3 = dest
604 * r4 = src
605 * r5 = length in bytes
606 * r6 = cachelinesize
607 */
608 .globl relocate_code
609relocate_code:
610 mr r1, r3 /* Set new stack pointer */
611 mr r9, r4 /* Save copy of Global Data pointer */
612 mr r10, r5 /* Save copy of Destination Address */
613
614 mr r3, r5 /* Destination Address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200615 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
616 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
wdenk3b57fe02003-05-30 12:48:29 +0000617 lwz r5, GOT(__init_end)
618 sub r5, r5, r4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200619 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
wdenk47d1a6e2002-11-03 00:01:44 +0000620
621 /*
622 * Fix GOT pointer:
623 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200624 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
wdenk47d1a6e2002-11-03 00:01:44 +0000625 *
626 * Offset:
627 */
628 sub r15, r10, r4
629
630 /* First our own GOT */
631 add r14, r14, r15
632 /* then the one used by the C code */
633 add r30, r30, r15
634
635 /*
636 * Now relocate code
637 */
638#ifdef CONFIG_ECC
639 bl board_relocate_rom
640 sync
641 mr r3, r10 /* Destination Address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200642 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
643 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
wdenk3b57fe02003-05-30 12:48:29 +0000644 lwz r5, GOT(__init_end)
645 sub r5, r5, r4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200646 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
wdenk47d1a6e2002-11-03 00:01:44 +0000647#else
648 cmplw cr1,r3,r4
649 addi r0,r5,3
650 srwi. r0,r0,2
651 beq cr1,4f /* In place copy is not necessary */
652 beq 7f /* Protect against 0 count */
653 mtctr r0
654 bge cr1,2f
655
656 la r8,-4(r4)
657 la r7,-4(r3)
6581: lwzu r0,4(r8)
659 stwu r0,4(r7)
660 bdnz 1b
661 b 4f
662
6632: slwi r0,r0,2
664 add r8,r4,r0
665 add r7,r3,r0
6663: lwzu r0,-4(r8)
667 stwu r0,-4(r7)
668 bdnz 3b
669#endif
670/*
671 * Now flush the cache: note that we must start from a cache aligned
672 * address. Otherwise we might miss one cache line.
673 */
6744: cmpwi r6,0
675 add r5,r3,r5
676 beq 7f /* Always flush prefetch queue in any case */
677 subi r0,r6,1
678 andc r3,r3,r0
679 mr r4,r3
6805: dcbst 0,r4
681 add r4,r4,r6
682 cmplw r4,r5
683 blt 5b
684 sync /* Wait for all dcbst to complete on bus */
685 mr r4,r3
6866: icbi 0,r4
687 add r4,r4,r6
688 cmplw r4,r5
689 blt 6b
6907: sync /* Wait for all icbi to complete on bus */
691 isync
692
693/*
694 * We are done. Do not return, instead branch to second part of board
695 * initialization, now running from RAM.
696 */
697 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
698 mtlr r0
699 blr
700
701in_ram:
702#ifdef CONFIG_ECC
703 bl board_init_ecc
704#endif
705 /*
706 * Relocation Function, r14 point to got2+0x8000
707 *
wdenk8bde7f72003-06-27 21:31:46 +0000708 * Adjust got2 pointers, no need to check for 0, this code
709 * already puts a few entries in the table.
wdenk47d1a6e2002-11-03 00:01:44 +0000710 */
711 li r0,__got2_entries@sectoff@l
712 la r3,GOT(_GOT2_TABLE_)
713 lwz r11,GOT(_GOT2_TABLE_)
714 mtctr r0
715 sub r11,r3,r11
716 addi r3,r3,-4
7171: lwzu r0,4(r3)
718 add r0,r0,r11
719 stw r0,0(r3)
720 bdnz 1b
721
722 /*
wdenk8bde7f72003-06-27 21:31:46 +0000723 * Now adjust the fixups and the pointers to the fixups
wdenk47d1a6e2002-11-03 00:01:44 +0000724 * in case we need to move ourselves again.
725 */
7262: li r0,__fixup_entries@sectoff@l
727 lwz r3,GOT(_FIXUP_TABLE_)
728 cmpwi r0,0
729 mtctr r0
730 addi r3,r3,-4
731 beq 4f
7323: lwzu r4,4(r3)
733 lwzux r0,r4,r11
734 add r0,r0,r11
735 stw r10,0(r3)
736 stw r0,0(r4)
737 bdnz 3b
7384:
739/* clear_bss: */
740 /*
741 * Now clear BSS segment
742 */
wdenk5d232d02003-05-22 22:52:13 +0000743 lwz r3,GOT(__bss_start)
wdenk47d1a6e2002-11-03 00:01:44 +0000744 lwz r4,GOT(_end)
745
746 cmplw 0, r3, r4
747 beq 6f
748
749 li r0, 0
7505:
751 stw r0, 0(r3)
752 addi r3, r3, 4
753 cmplw 0, r3, r4
754 bne 5b
7556:
756 mr r3, r10 /* Destination Address */
wdenk3a473b22004-01-03 00:43:19 +0000757#if defined(CONFIG_AMIGAONEG3SE) || \
758 defined(CONFIG_DB64360) || \
stroese0912e482004-12-16 18:10:54 +0000759 defined(CONFIG_DB64460) || \
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200760 defined(CONFIG_CPCI750) || \
Stefan Roese1eac2a72006-11-29 15:42:37 +0100761 defined(CONFIG_PPMC7XX) || \
762 defined(CONFIG_P3Mx)
wdenk7c7a23b2002-12-07 00:20:59 +0000763 mr r4, r9 /* Use RAM copy of the global data */
764#endif
wdenk47d1a6e2002-11-03 00:01:44 +0000765 bl after_reloc
766
767 /* not reached - end relocate_code */
768/*-----------------------------------------------------------------------*/
769
wdenk47d1a6e2002-11-03 00:01:44 +0000770 /*
771 * Copy exception vector code to low memory
772 *
773 * r3: dest_addr
774 * r7: source address, r8: end address, r9: target address
775 */
776 .globl trap_init
777trap_init:
778 lwz r7, GOT(_start)
779 lwz r8, GOT(_end_of_vectors)
780
wdenk682011f2003-06-03 23:54:09 +0000781 li r9, 0x100 /* reset vector always at 0x100 */
wdenk47d1a6e2002-11-03 00:01:44 +0000782
783 cmplw 0, r7, r8
784 bgelr /* return if r7>=r8 - just in case */
785
786 mflr r4 /* save link register */
7871:
788 lwz r0, 0(r7)
789 stw r0, 0(r9)
790 addi r7, r7, 4
791 addi r9, r9, 4
792 cmplw 0, r7, r8
793 bne 1b
794
795 /*
796 * relocate `hdlr' and `int_return' entries
797 */
798 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
799 li r8, Alignment - _start + EXC_OFF_SYS_RESET
8002:
801 bl trap_reloc
802 addi r7, r7, 0x100 /* next exception vector */
803 cmplw 0, r7, r8
804 blt 2b
805
806 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
807 bl trap_reloc
808
809 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
810 bl trap_reloc
811
812 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
813 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
8143:
815 bl trap_reloc
816 addi r7, r7, 0x100 /* next exception vector */
817 cmplw 0, r7, r8
818 blt 3b
819
820 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
821 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
8224:
823 bl trap_reloc
824 addi r7, r7, 0x100 /* next exception vector */
825 cmplw 0, r7, r8
826 blt 4b
827
828 /* enable execptions from RAM vectors */
829 mfmsr r7
830 li r8,MSR_IP
831 andc r7,r7,r8
832 mtmsr r7
833
834 mtlr r4 /* restore link register */
835 blr
836
837 /*
838 * Function: relocate entries for one exception vector
839 */
840trap_reloc:
841 lwz r0, 0(r7) /* hdlr ... */
842 add r0, r0, r3 /* ... += dest_addr */
843 stw r0, 0(r7)
844
845 lwz r0, 4(r7) /* int_return ... */
846 add r0, r0, r3 /* ... += dest_addr */
847 stw r0, 4(r7)
848
849 sync
850 isync
851
852 blr
853
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200854#ifdef CONFIG_SYS_INIT_RAM_LOCK
wdenk47d1a6e2002-11-03 00:01:44 +0000855lock_ram_in_cache:
856 /* Allocate Initial RAM in data cache.
857 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200858 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
859 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
860 li r2, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
861 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
wdenk47d1a6e2002-11-03 00:01:44 +0000862 mtctr r2
8631:
864 dcbz r0, r3
865 addi r3, r3, 32
866 bdnz 1b
867
868 /* Lock the data cache */
869 mfspr r0, HID0
870 ori r0, r0, 0x1000
871 sync
872 mtspr HID0, r0
873 sync
874 blr
875
876.globl unlock_ram_in_cache
877unlock_ram_in_cache:
878 /* invalidate the INIT_RAM section */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200879 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
880 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
881 li r2, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
882 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
wdenk47d1a6e2002-11-03 00:01:44 +0000883 mtctr r2
8841: icbi r0, r3
885 addi r3, r3, 32
886 bdnz 1b
887 sync /* Wait for all icbi to complete on bus */
888 isync
889
890 /* Unlock the data cache and invalidate it */
891 mfspr r0, HID0
892 li r3,0x1000
893 andc r0,r0,r3
894 li r3,0x0400
895 or r0,r0,r3
896 sync
897 mtspr HID0, r0
898 sync
899 blr
900#endif