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TsiChung Liew8e585f02007-06-18 13:50:13 -05001/*
2 *
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
TsiChungLiew84a015b2007-07-05 23:03:28 -05006 * (C) Copyright 2007 Freescale Semiconductor, Inc.
TsiChung Liew8e585f02007-06-18 13:50:13 -05007 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29#include <watchdog.h>
30
TsiChungLiew84a015b2007-07-05 23:03:28 -050031#include <asm/immap.h>
TsiChung Liew8e585f02007-06-18 13:50:13 -050032
33/*
34 * Breath some life into the CPU...
35 *
36 * Set up the memory map,
37 * initialize a bunch of registers,
38 * initialize the UPM's
39 */
40void cpu_init_f(void)
41{
42 volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
43 volatile scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
44 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
45 volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
46 volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG;
47
48 /* watchdog is enabled by default - disable the watchdog */
49#ifndef CONFIG_WATCHDOG
50 wdog->cr = 0;
51#endif
52
53 scm1->mpr0 = 0x77777777;
54 scm2->pacra = 0;
55 scm2->pacrb = 0;
56 scm2->pacrc = 0;
57 scm2->pacrd = 0;
58 scm2->pacre = 0;
59 scm2->pacrf = 0;
60 scm2->pacrg = 0;
61 scm1->pacrh = 0;
62
TsiChung Liew8e585f02007-06-18 13:50:13 -050063 /* Port configuration */
TsiChungLiewa41de1f2007-08-05 05:15:18 -050064 gpio->par_cs = 0;
TsiChung Liew8e585f02007-06-18 13:50:13 -050065
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
67 fbcs->csar0 = CONFIG_SYS_CS0_BASE;
68 fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
69 fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
TsiChung Liew8e585f02007-06-18 13:50:13 -050070#endif
71
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
TsiChung Liew8e585f02007-06-18 13:50:13 -050073 /* Latch chipselect */
Stefan Roese3ba4c2d2007-08-08 09:54:26 +020074 gpio->par_cs |= GPIO_PAR_CS1;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075 fbcs->csar1 = CONFIG_SYS_CS1_BASE;
76 fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
77 fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
TsiChung Liew8e585f02007-06-18 13:50:13 -050078#endif
79
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
Stefan Roese3ba4c2d2007-08-08 09:54:26 +020081 gpio->par_cs |= GPIO_PAR_CS2;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082 fbcs->csar2 = CONFIG_SYS_CS2_BASE;
83 fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
84 fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
TsiChung Liew8e585f02007-06-18 13:50:13 -050085#endif
86
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
Stefan Roese3ba4c2d2007-08-08 09:54:26 +020088 gpio->par_cs |= GPIO_PAR_CS3;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089 fbcs->csar3 = CONFIG_SYS_CS3_BASE;
90 fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
91 fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
TsiChung Liew8e585f02007-06-18 13:50:13 -050092#endif
93
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
Stefan Roese3ba4c2d2007-08-08 09:54:26 +020095 gpio->par_cs |= GPIO_PAR_CS4;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096 fbcs->csar4 = CONFIG_SYS_CS4_BASE;
97 fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
98 fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
TsiChung Liew8e585f02007-06-18 13:50:13 -050099#endif
100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
Stefan Roese3ba4c2d2007-08-08 09:54:26 +0200102 gpio->par_cs |= GPIO_PAR_CS5;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103 fbcs->csar5 = CONFIG_SYS_CS5_BASE;
104 fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
105 fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
TsiChung Liew8e585f02007-06-18 13:50:13 -0500106#endif
TsiChung0dca8742007-07-10 15:45:43 -0500107
TsiChungLiewa41de1f2007-08-05 05:15:18 -0500108#ifdef CONFIG_FSL_I2C
109 gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA;
110#endif
111
TsiChung0dca8742007-07-10 15:45:43 -0500112 icache_enable();
TsiChung Liew8e585f02007-06-18 13:50:13 -0500113}
114
115/*
116 * initialize higher level parts of CPU like timers
117 */
118int cpu_init_r(void)
119{
TsiChung Liew8e585f02007-06-18 13:50:13 -0500120 return (0);
121}
TsiChungLiew8d1d66a2007-08-05 03:55:21 -0500122
123void uart_port_conf(void)
124{
125 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
126
127 /* Setup Ports: */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128 switch (CONFIG_SYS_UART_PORT) {
TsiChungLiew8d1d66a2007-08-05 03:55:21 -0500129 case 0:
130 gpio->par_uart = (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
131 break;
132 case 1:
133 gpio->par_uart =
134 (GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
135 break;
136 case 2:
137 gpio->par_timer &= 0x0F;
138 gpio->par_timer |= (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2);
139 break;
140 }
141}