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wdenk5b1d7132002-11-03 00:07:02 +00001/*
2 * (C) Copyright 2000, 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
29 * U-Boot port on RPXlite board
30 */
31
32#ifndef __CONFIG_H
33#define __CONFIG_H
34
35#define RPXClassic_50MHz
36
37/*
38 * High Level Configuration Options
39 * (easy to change)
40 */
41
42#define CONFIG_MPC860 1
43#define CONFIG_RPXCLASSIC 1
44
45#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
46#undef CONFIG_8xx_CONS_SMC2
47#undef CONFIG_8xx_CONS_NONE
48#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
49
wdenk5b1d7132002-11-03 00:07:02 +000050/* Define CONFIG_FEC_ENET to use Fast ethernet instead of ethernet on SCC1 */
wdenka6c7ad22002-12-03 21:28:10 +000051#define CONFIG_FEC_ENET
wdenk5b1d7132002-11-03 00:07:02 +000052#ifdef CONFIG_FEC_ENET
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#define CONFIG_SYS_DISCOVER_PHY 1
wdenka6c7ad22002-12-03 21:28:10 +000054#define CONFIG_MII 1
wdenk5b1d7132002-11-03 00:07:02 +000055#endif /* CONFIG_FEC_ENET */
56
wdenka6c7ad22002-12-03 21:28:10 +000057/* Video console (graphic: Epson SED13806 on ECCX board, no keyboard */
58#if 1
59#define CONFIG_VIDEO_SED13806
60#define CONFIG_NEC_NL6448BC20
61#define CONFIG_VIDEO_SED13806_16BPP
62
63#define CONFIG_CFB_CONSOLE
64#define CONFIG_VIDEO_LOGO
65#define CONFIG_VIDEO_BMP_LOGO
66#define CONFIG_CONSOLE_EXTRA_INFO
67#define CONFIG_VGA_AS_SINGLE_DEVICE
68#define CONFIG_VIDEO_SW_CURSOR
69#endif
70
wdenk5b1d7132002-11-03 00:07:02 +000071#if 0
72#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
73#else
74#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
75#endif
76
77#define CONFIG_ZERO_BOOTDELAY_CHECK 1
78
79#undef CONFIG_BOOTARGS
80#define CONFIG_BOOTCOMMAND \
Wolfgang Denk53677ef2008-05-20 16:00:29 +020081 "tftpboot; " \
82 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
83 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenk5b1d7132002-11-03 00:07:02 +000084 "bootm"
85
86#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenk5b1d7132002-11-03 00:07:02 +000088
89#undef CONFIG_WATCHDOG /* watchdog disabled */
90
Jon Loeliger18225e82007-07-09 21:31:24 -050091/*
92 * BOOTP options
93 */
94#define CONFIG_BOOTP_SUBNETMASK
95#define CONFIG_BOOTP_GATEWAY
96#define CONFIG_BOOTP_HOSTNAME
97#define CONFIG_BOOTP_BOOTPATH
98#define CONFIG_BOOTP_BOOTFILESIZE
99
wdenk5b1d7132002-11-03 00:07:02 +0000100
101#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
102
103
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500104/*
105 * Command line configuration.
106 */
107#include <config_cmd_default.h>
wdenk5b1d7132002-11-03 00:07:02 +0000108
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500109#define CONFIG_CMD_ELF
110
wdenk5b1d7132002-11-03 00:07:02 +0000111
112/*
113 * Miscellaneous configurable options
114 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_RESET_ADDRESS 0x80000000
116#define CONFIG_SYS_LONGHELP /* undef to save memory */
117#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500118#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk5b1d7132002-11-03 00:07:02 +0000120#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk5b1d7132002-11-03 00:07:02 +0000122#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
124#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
125#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk5b1d7132002-11-03 00:07:02 +0000126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_MEMTEST_START 0x0040000 /* memtest works on */
128#define CONFIG_SYS_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */
wdenk5b1d7132002-11-03 00:07:02 +0000129
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk5b1d7132002-11-03 00:07:02 +0000131
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk5b1d7132002-11-03 00:07:02 +0000133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk5b1d7132002-11-03 00:07:02 +0000135
136/*
137 * Low Level Configuration Settings
138 * (address mappings, register initial values, etc.)
139 * You should know what you are doing if you make changes here.
140 */
141/*-----------------------------------------------------------------------
142 * Internal Memory Mapped Register
143 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_IMMR 0xFA200000
wdenk5b1d7132002-11-03 00:07:02 +0000145
146/*-----------------------------------------------------------------------------
147 * I2C Configuration
148 *-----------------------------------------------------------------------------
149 */
150#define CONFIG_I2C 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_I2C_SPEED 50000
152#define CONFIG_SYS_I2C_SLAVE 0x34
wdenk5b1d7132002-11-03 00:07:02 +0000153
154
155/* enable I2C and select the hardware/software driver */
156#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
157#undef CONFIG_SOFT_I2C /* I2C bit-banged */
158/*
159 * Software (bit-bang) I2C driver configuration
160 */
161#define I2C_PORT 1 /* Port A=0, B=1, C=2, D=3 */
162#define I2C_ACTIVE (iop->pdir |= 0x00000010)
163#define I2C_TRISTATE (iop->pdir &= ~0x00000010)
164#define I2C_READ ((iop->pdat & 0x00000010) != 0)
165#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000010; \
166 else iop->pdat &= ~0x00000010
167#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000020; \
168 else iop->pdat &= ~0x00000020
169#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
170
171
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172# define CONFIG_SYS_I2C_SPEED 50000
173# define CONFIG_SYS_I2C_SLAVE 0x34
174# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */
175# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
wdenk5b1d7132002-11-03 00:07:02 +0000176/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
wdenk5b1d7132002-11-03 00:07:02 +0000178
179/*-----------------------------------------------------------------------
180 * Definitions for initial stack pointer and data area (in DPRAM)
181 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
183#define CONFIG_SYS_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
184#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
185#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
186#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk5b1d7132002-11-03 00:07:02 +0000187
188/*-----------------------------------------------------------------------
189 * Start addresses for the final memory configuration
190 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk5b1d7132002-11-03 00:07:02 +0000192 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_SDRAM_BASE 0x00000000
194#define CONFIG_SYS_FLASH_BASE 0xFF000000
wdenk5b1d7132002-11-03 00:07:02 +0000195
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500196#if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || defined(CONFIG_CMD_IDE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
wdenk5b1d7132002-11-03 00:07:02 +0000198#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
wdenk5b1d7132002-11-03 00:07:02 +0000200#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_MONITOR_BASE 0xFF000000
202/*%%% #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE */
203#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk5b1d7132002-11-03 00:07:02 +0000204
205/*
206 * For booting Linux, the board info and command line data
207 * have to be in the first 8 MB of memory, since this is
208 * the maximum mapped by the Linux kernel during initialization.
209 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk5b1d7132002-11-03 00:07:02 +0000211
212/*-----------------------------------------------------------------------
213 * FLASH organization
214 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
216#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
wdenk5b1d7132002-11-03 00:07:02 +0000217
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
219#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk5b1d7132002-11-03 00:07:02 +0000220
221#if 0
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200222#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200223#define CONFIG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */
224#define CONFIG_ENV_SECT_SIZE 0x8000
225#define CONFIG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */
wdenk5b1d7132002-11-03 00:07:02 +0000226#else
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200227#define CONFIG_ENV_IS_IN_NVRAM 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200228#define CONFIG_ENV_ADDR 0xfa000100
229#define CONFIG_ENV_SIZE 0x1000
wdenk5b1d7132002-11-03 00:07:02 +0000230#endif
231
232/*-----------------------------------------------------------------------
233 * Cache Configuration
234 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500236#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenk5b1d7132002-11-03 00:07:02 +0000238#endif
239
240/*-----------------------------------------------------------------------
241 * SYPCR - System Protection Control 11-9
242 * SYPCR can only be written once after reset!
243 *-----------------------------------------------------------------------
244 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
245 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk5b1d7132002-11-03 00:07:02 +0000247 SYPCR_SWP)
248
249/*-----------------------------------------------------------------------
250 * SIUMCR - SIU Module Configuration 11-6
251 *-----------------------------------------------------------------------
252 * PCMCIA config., multi-function pin tri-state
253 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10)
wdenk5b1d7132002-11-03 00:07:02 +0000255
256/*-----------------------------------------------------------------------
257 * TBSCR - Time Base Status and Control 11-26
258 *-----------------------------------------------------------------------
259 * Clear Reference Interrupt Status, Timebase freezing enabled
260 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
wdenk5b1d7132002-11-03 00:07:02 +0000262
263/*-----------------------------------------------------------------------
264 * RTCSC - Real-Time Clock Status and Control Register 11-27
265 *-----------------------------------------------------------------------
266 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267/*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
268#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE)
wdenk5b1d7132002-11-03 00:07:02 +0000269
270/*-----------------------------------------------------------------------
271 * PISCR - Periodic Interrupt Status and Control 11-31
272 *-----------------------------------------------------------------------
273 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
274 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
wdenk5b1d7132002-11-03 00:07:02 +0000276
277/*-----------------------------------------------------------------------
278 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
279 *-----------------------------------------------------------------------
280 * Reset PLL lock status sticky bit, timer expired status bit and timer
281 * interrupt status bit
282 *
283 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
284 */
285/* up to 50 MHz we use a 1:1 clock */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_PLPRCR ( (4 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS | PLPRCR_SPLSS | PLPRCR_TMIST)
wdenk5b1d7132002-11-03 00:07:02 +0000287
288/*-----------------------------------------------------------------------
289 * SCCR - System Clock and reset Control Register 15-27
290 *-----------------------------------------------------------------------
291 * Set clock output, timebase and RTC source and divider,
292 * power management and some other internal clocks
293 */
294#define SCCR_MASK SCCR_EBDF00
295/* up to 50 MHz we use a 1:1 clock */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS)
wdenk5b1d7132002-11-03 00:07:02 +0000297
298/*-----------------------------------------------------------------------
299 * PCMCIA stuff
300 *-----------------------------------------------------------------------
301 *
302 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
304#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
305#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
306#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
307#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
308#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
309#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
310#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenk5b1d7132002-11-03 00:07:02 +0000311
312/*-----------------------------------------------------------------------
313 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
314 *-----------------------------------------------------------------------
315 */
316
317#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
318
319#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
320#undef CONFIG_IDE_LED /* LED for ide not supported */
321#undef CONFIG_IDE_RESET /* reset for ide not supported */
322
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
324#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenk5b1d7132002-11-03 00:07:02 +0000325
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenk5b1d7132002-11-03 00:07:02 +0000327
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenk5b1d7132002-11-03 00:07:02 +0000329
330/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenk5b1d7132002-11-03 00:07:02 +0000332
333/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenk5b1d7132002-11-03 00:07:02 +0000335
336/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenk5b1d7132002-11-03 00:07:02 +0000338
339/*-----------------------------------------------------------------------
340 *
341 *-----------------------------------------------------------------------
342 *
343 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344/* #define CONFIG_SYS_DER 0x2002000F */
345#define CONFIG_SYS_DER 0
wdenk5b1d7132002-11-03 00:07:02 +0000346
347/*
348 * Init Memory Controller:
349 *
350 * BR0 and OR0 (FLASH)
351 */
352
353#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_PRELIM_OR_AM 0xFE000000 /* OR addr mask */
wdenk5b1d7132002-11-03 00:07:02 +0000355
356/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
wdenk5b1d7132002-11-03 00:07:02 +0000358
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
360#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
wdenk5b1d7132002-11-03 00:07:02 +0000361
362/*
363 * BR1 and OR1 (SDRAM)
364 *
365 */
366#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
367#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */
368
369/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00
wdenk5b1d7132002-11-03 00:07:02 +0000371
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
373#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenk5b1d7132002-11-03 00:07:02 +0000374
375/* RPXLITE mem setting */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* BCSR */
377#define CONFIG_SYS_OR3_PRELIM 0xff7f8970
378#define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
379#define CONFIG_SYS_OR4_PRELIM 0xFFF80970
wdenk5b1d7132002-11-03 00:07:02 +0000380
wdenka6c7ad22002-12-03 21:28:10 +0000381/* ECCX CS settings */
382#define SED13806_OR 0xFFC00108 /* - 4 Mo
wdenk8bde7f72003-06-27 21:31:46 +0000383 - Burst inhibit
384 - external TA */
wdenka6c7ad22002-12-03 21:28:10 +0000385#define SED13806_REG_ADDR 0xa0000000
386#define SED13806_ACCES 0x801 /* 16 bit access */
387
388
389/* Global definitions for the ECCX board */
390#define ECCX_CSR_ADDR (0xfac00000)
391#define ECCX_CSR8_OFFSET (0x8)
392#define ECCX_CSR11_OFFSET (0xB)
393#define ECCX_CSR12_OFFSET (0xC)
394
395#define ECCX_CSR8 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR8_OFFSET)
396#define ECCX_CSR11 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR11_OFFSET)
397#define ECCX_CSR12 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR12_OFFSET)
398
399
400#define REG_GPIO_CTRL 0x008
401
402/* Definitions for CSR8 */
403#define ECCX_ENEPSON 0x80 /* Bit 0:
wdenk8bde7f72003-06-27 21:31:46 +0000404 0= disable and reset SED1386
405 1= enable SED1386 */
wdenka6c7ad22002-12-03 21:28:10 +0000406/* Bit 1: 0= SED1386 in Big Endian mode */
407/* 1= SED1386 in little endian mode */
408#define ECCX_LE 0x40
409#define ECCX_BE 0x00
410
411/* Bit 2,3: Selection */
412/* 00 = Disabled */
413/* 01 = CS2 is used for the SED1386 */
414/* 10 = CS5 is used for the SED1386 */
415/* 11 = reserved */
416#define ECCX_CS2 0x10
417#define ECCX_CS5 0x20
418
419/* Definitions for CSR12 */
420#define ECCX_ID 0x02
421#define ECCX_860 0x01
422
wdenk5b1d7132002-11-03 00:07:02 +0000423/*
424 * Memory Periodic Timer Prescaler
425 */
426
427/* periodic timer for refresh */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200428#define CONFIG_SYS_MAMR_PTA 58
wdenk5b1d7132002-11-03 00:07:02 +0000429
430/*
431 * Refresh clock Prescalar
432 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200433#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV8
wdenk5b1d7132002-11-03 00:07:02 +0000434
435/*
436 * MAMR settings for SDRAM
437 */
438
439/* 10 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200440#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk5b1d7132002-11-03 00:07:02 +0000441 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \
442 MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
443
444/*
445 * Internal Definitions
446 *
447 * Boot Flags
448 */
449#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
450#define BOOTFLAG_WARM 0x02 /* Software reboot */
451
452
453/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
454/* Configuration variable added by yooth. */
455/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
456
457/*
458 * BCSRx
459 *
460 * Board Status and Control Registers
461 *
462 */
463
464#define BCSR0 0xFA400000
465#define BCSR1 0xFA400001
466#define BCSR2 0xFA400002
467#define BCSR3 0xFA400003
468
469#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200470#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
wdenk5b1d7132002-11-03 00:07:02 +0000471#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
472#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
473#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
474#define BCSR0_COLTEST 0x20
475#define BCSR0_ETHLPBK 0x40
476#define BCSR0_ETHEN 0x80
477
478#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
479#define BCSR1_PCVCTL6 0x02
480#define BCSR1_PCVCTL5 0x04
481#define BCSR1_PCVCTL4 0x08
482#define BCSR1_IPB5SEL 0x10
483
484#define BCSR2_MIIRST 0x80
485#define BCSR2_MIIPWRDWN 0x40
486#define BCSR2_MIICTL 0x08
487
488#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */
489#define BCSR3_BWNVR 0x02 /* NVRAM Battery */
490#define BCSR3_RDY_BSY 0x04 /* Flash Operation */
491#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */
492#define BCSR3_D27 0x10 /* Dip Switch settings */
493#define BCSR3_D26 0x20
494#define BCSR3_D25 0x40
495#define BCSR3_D24 0x80
496
497
498/*
499 * Environment setting
500 */
501
502/* #define CONFIG_ETHADDR 00:10:EC:00:2C:A2 */
503/* #define CONFIG_IPADDR 10.10.106.1 */
504/* #define CONFIG_SERVERIP 10.10.104.11 */
505
506#endif /* __CONFIG_H */