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wdenkbf9e3b32004-02-12 00:47:09 +00001/*
2 * Configuation settings for the Motorola MC5282EVB board.
3 *
4 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
26 * board/config.h - configuration options, board specific
27 */
28
wdenk4e5ca3e2003-12-08 01:34:36 +000029#ifndef _CONFIG_M5282EVB_H
30#define _CONFIG_M5282EVB_H
31
wdenkbf9e3b32004-02-12 00:47:09 +000032/*
33 * High Level Configuration Options
34 * (easy to change)
35 */
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050036#define CONFIG_MCF52x2 /* define processor family */
37#define CONFIG_M5282 /* define processor type */
wdenk4e5ca3e2003-12-08 01:34:36 +000038
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050039#define CONFIG_MCFTMR
wdenk4e5ca3e2003-12-08 01:34:36 +000040
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050041#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042#define CONFIG_SYS_UART_PORT (0)
TsiChung Liew79e07992008-08-15 16:50:07 +000043#define CONFIG_BAUDRATE 115200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
wdenkbf9e3b32004-02-12 00:47:09 +000045
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050046#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
wdenkbf9e3b32004-02-12 00:47:09 +000047
48/* Configuration for environment
49 * Environment is embedded in u-boot in the second sector of the flash
50 */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020051#define CONFIG_ENV_ADDR 0xffe04000
52#define CONFIG_ENV_SIZE 0x2000
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020053#define CONFIG_ENV_IS_IN_FLASH 1
wdenkbf9e3b32004-02-12 00:47:09 +000054
Jon Loeliger8353e132007-07-08 14:14:17 -050055/*
Jon Loeliger659e2f62007-07-10 09:10:49 -050056 * BOOTP options
57 */
58#define CONFIG_BOOTP_BOOTFILESIZE
59#define CONFIG_BOOTP_BOOTPATH
60#define CONFIG_BOOTP_GATEWAY
61#define CONFIG_BOOTP_HOSTNAME
62
Jon Loeliger659e2f62007-07-10 09:10:49 -050063/*
Jon Loeliger8353e132007-07-08 14:14:17 -050064 * Command line configuration.
65 */
66#include <config_cmd_default.h>
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050067#define CONFIG_CMD_NET
68#define CONFIG_CMD_PING
69#define CONFIG_CMD_MII
wdenkbf9e3b32004-02-12 00:47:09 +000070
Jon Loeliger8353e132007-07-08 14:14:17 -050071#undef CONFIG_CMD_LOADS
72#undef CONFIG_CMD_LOADB
73
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050074#define CONFIG_MCFFEC
75#ifdef CONFIG_MCFFEC
76# define CONFIG_NET_MULTI 1
77# define CONFIG_MII 1
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -050078# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079# define CONFIG_SYS_DISCOVER_PHY
80# define CONFIG_SYS_RX_ETH_BUFFER 8
81# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050082
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083# define CONFIG_SYS_FEC0_PINMUX 0
84# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
Wolfgang Denk53677ef2008-05-20 16:00:29 +020085# define MCFFEC_TOUT_LOOP 50000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
87# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050088# define FECDUPLEX FULL
89# define FECSPEED _100BASET
90# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
92# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050093# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050095#endif
Jon Loeliger8353e132007-07-08 14:14:17 -050096
wdenkbf9e3b32004-02-12 00:47:09 +000097#define CONFIG_BOOTDELAY 5
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050098#ifdef CONFIG_MCFFEC
99# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
100# define CONFIG_IPADDR 192.162.1.2
101# define CONFIG_NETMASK 255.255.255.0
102# define CONFIG_SERVERIP 192.162.1.1
103# define CONFIG_GATEWAYIP 192.162.1.1
104# define CONFIG_OVERWRITE_ETHADDR_ONCE
105#endif /* CONFIG_MCFFEC */
106
TsiChung Liew4cb4e652008-08-11 15:54:25 +0000107#define CONFIG_HOSTNAME M5282EVB
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500108#define CONFIG_EXTRA_ENV_SETTINGS \
109 "netdev=eth0\0" \
110 "loadaddr=10000\0" \
111 "u-boot=u-boot.bin\0" \
112 "load=tftp ${loadaddr) ${u-boot}\0" \
113 "upd=run load; run prog\0" \
114 "prog=prot off ffe00000 ffe3ffff;" \
115 "era ffe00000 ffe3ffff;" \
116 "cp.b ${loadaddr} ffe00000 ${filesize};"\
117 "save\0" \
118 ""
wdenkbf9e3b32004-02-12 00:47:09 +0000119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_PROMPT "-> "
121#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenkbf9e3b32004-02-12 00:47:09 +0000122
Jon Loeliger8353e132007-07-08 14:14:17 -0500123#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkbf9e3b32004-02-12 00:47:09 +0000125#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkbf9e3b32004-02-12 00:47:09 +0000127#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
129#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
130#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkbf9e3b32004-02-12 00:47:09 +0000131
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_LOAD_ADDR 0x20000
wdenkbf9e3b32004-02-12 00:47:09 +0000133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_MEMTEST_START 0x400
135#define CONFIG_SYS_MEMTEST_END 0x380000
wdenkbf9e3b32004-02-12 00:47:09 +0000136
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_HZ 1000
138#define CONFIG_SYS_CLK 64000000
wdenkbf9e3b32004-02-12 00:47:09 +0000139
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500140/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
141
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
143#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
wdenkbf9e3b32004-02-12 00:47:09 +0000144
145/*
146 * Low Level Configuration Settings
147 * (address mappings, register initial values, etc.)
148 * You should know what you are doing if you make changes here.
149 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_MBAR 0x40000000
wdenkbf9e3b32004-02-12 00:47:09 +0000151
wdenkbf9e3b32004-02-12 00:47:09 +0000152/*-----------------------------------------------------------------------
153 * Definitions for initial stack pointer and data area (in DPRAM)
154 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
156#define CONFIG_SYS_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
157#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
158#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
159#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkbf9e3b32004-02-12 00:47:09 +0000160
161/*-----------------------------------------------------------------------
162 * Start addresses for the final memory configuration
163 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkbf9e3b32004-02-12 00:47:09 +0000165 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_SDRAM_BASE 0x00000000
167#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
TsiChung Liew012522f2008-10-21 10:03:07 +0000168#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_INT_FLASH_BASE 0xf0000000
170#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
wdenkbf9e3b32004-02-12 00:47:09 +0000171
172/* If M5282 port is fully implemented the monitor base will be behind
173 * the vector table. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#if (TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
175#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500176#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500178#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000179
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_MONITOR_LEN 0x20000
181#define CONFIG_SYS_MALLOC_LEN (256 << 10)
182#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
wdenkbf9e3b32004-02-12 00:47:09 +0000183
wdenkbf9e3b32004-02-12 00:47:09 +0000184/*
185 * For booting Linux, the board info and command line data
186 * have to be in the first 8 MB of memory, since this is
187 * the maximum mapped by the Linux kernel during initialization ??
188 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
wdenkbf9e3b32004-02-12 00:47:09 +0000190
191/*-----------------------------------------------------------------------
192 * FLASH organization
193 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_FLASH_CFI
195#ifdef CONFIG_SYS_FLASH_CFI
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500196
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200197# define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
199# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
200# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
201# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
202# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
203# define CONFIG_SYS_FLASH_CHECKSUM
204# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500205#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000206
207/*-----------------------------------------------------------------------
208 * Cache Configuration
209 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_CACHELINE_SIZE 16
wdenkbf9e3b32004-02-12 00:47:09 +0000211
wdenkbf9e3b32004-02-12 00:47:09 +0000212/*-----------------------------------------------------------------------
213 * Memory bank definitions
214 */
TsiChung Liew012522f2008-10-21 10:03:07 +0000215#define CONFIG_SYS_CS0_BASE 0xFFE00000
216#define CONFIG_SYS_CS0_CTRL 0x00001980
217#define CONFIG_SYS_CS0_MASK 0x001F0001
218
wdenkbf9e3b32004-02-12 00:47:09 +0000219/*-----------------------------------------------------------------------
220 * Port configuration
221 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
223#define CONFIG_SYS_PADDR 0x0000000
224#define CONFIG_SYS_PADAT 0x0000000
wdenkbf9e3b32004-02-12 00:47:09 +0000225
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
227#define CONFIG_SYS_PBDDR 0x0000000
228#define CONFIG_SYS_PBDAT 0x0000000
wdenk4e5ca3e2003-12-08 01:34:36 +0000229
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */
231#define CONFIG_SYS_PCDDR 0x0000000
232#define CONFIG_SYS_PCDAT 0x0000000
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500233
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
235#define CONFIG_SYS_PCDDR 0x0000000
236#define CONFIG_SYS_PCDAT 0x0000000
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500237
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_PEHLPAR 0xC0
239#define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
240#define CONFIG_SYS_DDRUA 0x05
241#define CONFIG_SYS_PJPAR 0xFF
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500242
243#endif /* _CONFIG_M5282EVB_H */