blob: a4606923ffc1f1d9f220f4f0732d6fa6b39fa257 [file] [log] [blame]
Yannick Fertréd4f7ea82019-10-07 15:29:06 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2016, Fuzhou Rockchip Electronics Co., Ltd
4 * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
5 * Author(s): Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
6 * Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
7 *
8 * This generic Synopsys DesignWare MIPI DSI host driver is inspired from
9 * the Linux Kernel driver drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c.
10 */
11
12#include <common.h>
13#include <clk.h>
14#include <dsi_host.h>
15#include <dm.h>
16#include <errno.h>
17#include <panel.h>
18#include <video.h>
19#include <asm/io.h>
Yannick Fertréd4f7ea82019-10-07 15:29:06 +020020#include <dm/device-internal.h>
Simon Glass336d4612020-02-03 07:36:16 -070021#include <dm/device_compat.h>
Simon Glasscd93d622020-05-10 11:40:13 -060022#include <linux/bitops.h>
Simon Glassc05ed002020-05-10 11:40:11 -060023#include <linux/delay.h>
Yannick Fertréd4f7ea82019-10-07 15:29:06 +020024#include <linux/iopoll.h>
25#include <video_bridge.h>
26
27#define HWVER_131 0x31333100 /* IP version 1.31 */
28
29#define DSI_VERSION 0x00
30#define VERSION GENMASK(31, 8)
31
32#define DSI_PWR_UP 0x04
33#define RESET 0
34#define POWERUP BIT(0)
35
36#define DSI_CLKMGR_CFG 0x08
37#define TO_CLK_DIVISION(div) (((div) & 0xff) << 8)
38#define TX_ESC_CLK_DIVISION(div) ((div) & 0xff)
39
40#define DSI_DPI_VCID 0x0c
41#define DPI_VCID(vcid) ((vcid) & 0x3)
42
43#define DSI_DPI_COLOR_CODING 0x10
44#define LOOSELY18_EN BIT(8)
45#define DPI_COLOR_CODING_16BIT_1 0x0
46#define DPI_COLOR_CODING_16BIT_2 0x1
47#define DPI_COLOR_CODING_16BIT_3 0x2
48#define DPI_COLOR_CODING_18BIT_1 0x3
49#define DPI_COLOR_CODING_18BIT_2 0x4
50#define DPI_COLOR_CODING_24BIT 0x5
51
52#define DSI_DPI_CFG_POL 0x14
53#define COLORM_ACTIVE_LOW BIT(4)
54#define SHUTD_ACTIVE_LOW BIT(3)
55#define HSYNC_ACTIVE_LOW BIT(2)
56#define VSYNC_ACTIVE_LOW BIT(1)
57#define DATAEN_ACTIVE_LOW BIT(0)
58
59#define DSI_DPI_LP_CMD_TIM 0x18
60#define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16)
61#define INVACT_LPCMD_TIME(p) ((p) & 0xff)
62
63#define DSI_DBI_VCID 0x1c
64#define DSI_DBI_CFG 0x20
65#define DSI_DBI_PARTITIONING_EN 0x24
66#define DSI_DBI_CMDSIZE 0x28
67
68#define DSI_PCKHDL_CFG 0x2c
69#define CRC_RX_EN BIT(4)
70#define ECC_RX_EN BIT(3)
71#define BTA_EN BIT(2)
72#define EOTP_RX_EN BIT(1)
73#define EOTP_TX_EN BIT(0)
74
75#define DSI_GEN_VCID 0x30
76
77#define DSI_MODE_CFG 0x34
78#define ENABLE_VIDEO_MODE 0
79#define ENABLE_CMD_MODE BIT(0)
80
81#define DSI_VID_MODE_CFG 0x38
82#define ENABLE_LOW_POWER (0x3f << 8)
83#define ENABLE_LOW_POWER_MASK (0x3f << 8)
84#define VID_MODE_TYPE_NON_BURST_SYNC_PULSES 0x0
85#define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS 0x1
86#define VID_MODE_TYPE_BURST 0x2
87#define VID_MODE_TYPE_MASK 0x3
88
89#define DSI_VID_PKT_SIZE 0x3c
90#define VID_PKT_SIZE(p) ((p) & 0x3fff)
91
92#define DSI_VID_NUM_CHUNKS 0x40
93#define VID_NUM_CHUNKS(c) ((c) & 0x1fff)
94
95#define DSI_VID_NULL_SIZE 0x44
96#define VID_NULL_SIZE(b) ((b) & 0x1fff)
97
98#define DSI_VID_HSA_TIME 0x48
99#define DSI_VID_HBP_TIME 0x4c
100#define DSI_VID_HLINE_TIME 0x50
101#define DSI_VID_VSA_LINES 0x54
102#define DSI_VID_VBP_LINES 0x58
103#define DSI_VID_VFP_LINES 0x5c
104#define DSI_VID_VACTIVE_LINES 0x60
105#define DSI_EDPI_CMD_SIZE 0x64
106
107#define DSI_CMD_MODE_CFG 0x68
108#define MAX_RD_PKT_SIZE_LP BIT(24)
109#define DCS_LW_TX_LP BIT(19)
110#define DCS_SR_0P_TX_LP BIT(18)
111#define DCS_SW_1P_TX_LP BIT(17)
112#define DCS_SW_0P_TX_LP BIT(16)
113#define GEN_LW_TX_LP BIT(14)
114#define GEN_SR_2P_TX_LP BIT(13)
115#define GEN_SR_1P_TX_LP BIT(12)
116#define GEN_SR_0P_TX_LP BIT(11)
117#define GEN_SW_2P_TX_LP BIT(10)
118#define GEN_SW_1P_TX_LP BIT(9)
119#define GEN_SW_0P_TX_LP BIT(8)
120#define ACK_RQST_EN BIT(1)
121#define TEAR_FX_EN BIT(0)
122
123#define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \
124 DCS_LW_TX_LP | \
125 DCS_SR_0P_TX_LP | \
126 DCS_SW_1P_TX_LP | \
127 DCS_SW_0P_TX_LP | \
128 GEN_LW_TX_LP | \
129 GEN_SR_2P_TX_LP | \
130 GEN_SR_1P_TX_LP | \
131 GEN_SR_0P_TX_LP | \
132 GEN_SW_2P_TX_LP | \
133 GEN_SW_1P_TX_LP | \
134 GEN_SW_0P_TX_LP)
135
136#define DSI_GEN_HDR 0x6c
137#define DSI_GEN_PLD_DATA 0x70
138
139#define DSI_CMD_PKT_STATUS 0x74
140#define GEN_RD_CMD_BUSY BIT(6)
141#define GEN_PLD_R_FULL BIT(5)
142#define GEN_PLD_R_EMPTY BIT(4)
143#define GEN_PLD_W_FULL BIT(3)
144#define GEN_PLD_W_EMPTY BIT(2)
145#define GEN_CMD_FULL BIT(1)
146#define GEN_CMD_EMPTY BIT(0)
147
148#define DSI_TO_CNT_CFG 0x78
149#define HSTX_TO_CNT(p) (((p) & 0xffff) << 16)
150#define LPRX_TO_CNT(p) ((p) & 0xffff)
151
152#define DSI_HS_RD_TO_CNT 0x7c
153#define DSI_LP_RD_TO_CNT 0x80
154#define DSI_HS_WR_TO_CNT 0x84
155#define DSI_LP_WR_TO_CNT 0x88
156#define DSI_BTA_TO_CNT 0x8c
157
158#define DSI_LPCLK_CTRL 0x94
159#define AUTO_CLKLANE_CTRL BIT(1)
160#define PHY_TXREQUESTCLKHS BIT(0)
161
162#define DSI_PHY_TMR_LPCLK_CFG 0x98
163#define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16)
164#define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff)
165
166#define DSI_PHY_TMR_CFG 0x9c
167#define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24)
168#define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16)
169#define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff)
170#define PHY_HS2LP_TIME_V131(lbcc) (((lbcc) & 0x3ff) << 16)
171#define PHY_LP2HS_TIME_V131(lbcc) ((lbcc) & 0x3ff)
172
173#define DSI_PHY_RSTZ 0xa0
174#define PHY_DISFORCEPLL 0
175#define PHY_ENFORCEPLL BIT(3)
176#define PHY_DISABLECLK 0
177#define PHY_ENABLECLK BIT(2)
178#define PHY_RSTZ 0
179#define PHY_UNRSTZ BIT(1)
180#define PHY_SHUTDOWNZ 0
181#define PHY_UNSHUTDOWNZ BIT(0)
182
183#define DSI_PHY_IF_CFG 0xa4
184#define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8)
185#define N_LANES(n) (((n) - 1) & 0x3)
186
187#define DSI_PHY_ULPS_CTRL 0xa8
188#define DSI_PHY_TX_TRIGGERS 0xac
189
190#define DSI_PHY_STATUS 0xb0
191#define PHY_STOP_STATE_CLK_LANE BIT(2)
192#define PHY_LOCK BIT(0)
193
194#define DSI_PHY_TST_CTRL0 0xb4
195#define PHY_TESTCLK BIT(1)
196#define PHY_UNTESTCLK 0
197#define PHY_TESTCLR BIT(0)
198#define PHY_UNTESTCLR 0
199
200#define DSI_PHY_TST_CTRL1 0xb8
201#define PHY_TESTEN BIT(16)
202#define PHY_UNTESTEN 0
203#define PHY_TESTDOUT(n) (((n) & 0xff) << 8)
204#define PHY_TESTDIN(n) ((n) & 0xff)
205
206#define DSI_INT_ST0 0xbc
207#define DSI_INT_ST1 0xc0
208#define DSI_INT_MSK0 0xc4
209#define DSI_INT_MSK1 0xc8
210
211#define DSI_PHY_TMR_RD_CFG 0xf4
212#define MAX_RD_TIME_V131(lbcc) ((lbcc) & 0x7fff)
213
214#define PHY_STATUS_TIMEOUT_US 10000
215#define CMD_PKT_STATUS_TIMEOUT_US 20000
216
217#define MSEC_PER_SEC 1000
218
219struct dw_mipi_dsi {
220 struct mipi_dsi_host dsi_host;
221 struct mipi_dsi_device *device;
222 void __iomem *base;
223 unsigned int lane_mbps; /* per lane */
224 u32 channel;
225 unsigned int max_data_lanes;
226 const struct mipi_dsi_phy_ops *phy_ops;
227};
228
229static int dsi_mode_vrefresh(struct display_timing *timings)
230{
231 int refresh = 0;
232 unsigned int calc_val;
233 u32 htotal = timings->hactive.typ + timings->hfront_porch.typ +
234 timings->hback_porch.typ + timings->hsync_len.typ;
235 u32 vtotal = timings->vactive.typ + timings->vfront_porch.typ +
236 timings->vback_porch.typ + timings->vsync_len.typ;
237
238 if (htotal > 0 && vtotal > 0) {
239 calc_val = timings->pixelclock.typ;
240 calc_val /= htotal;
241 refresh = (calc_val + vtotal / 2) / vtotal;
242 }
243
244 return refresh;
245}
246
247/*
248 * The controller should generate 2 frames before
249 * preparing the peripheral.
250 */
251static void dw_mipi_dsi_wait_for_two_frames(struct display_timing *timings)
252{
253 int refresh, two_frames;
254
255 refresh = dsi_mode_vrefresh(timings);
256 two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
257 mdelay(two_frames);
258}
259
260static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
261{
262 return container_of(host, struct dw_mipi_dsi, dsi_host);
263}
264
265static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
266{
267 writel(val, dsi->base + reg);
268}
269
270static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
271{
272 return readl(dsi->base + reg);
273}
274
275static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
276 struct mipi_dsi_device *device)
277{
278 struct dw_mipi_dsi *dsi = host_to_dsi(host);
279
280 if (device->lanes > dsi->max_data_lanes) {
281 dev_err(device->dev,
282 "the number of data lanes(%u) is too many\n",
283 device->lanes);
284 return -EINVAL;
285 }
286
287 dsi->channel = device->channel;
288
289 return 0;
290}
291
292static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
293 const struct mipi_dsi_msg *msg)
294{
295 bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
296 u32 val = 0;
297
298 if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
299 val |= ACK_RQST_EN;
300 if (lpm)
301 val |= CMD_MODE_ALL_LP;
302
303 dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
304 dsi_write(dsi, DSI_CMD_MODE_CFG, val);
305}
306
307static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
308{
309 int ret;
310 u32 val, mask;
311
312 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
313 val, !(val & GEN_CMD_FULL),
314 CMD_PKT_STATUS_TIMEOUT_US);
315 if (ret) {
Sean Anderson4723fd52020-09-15 10:45:20 -0400316 dev_err(dsi->dsi_host.dev,
317 "failed to get available command FIFO\n");
Yannick Fertréd4f7ea82019-10-07 15:29:06 +0200318 return ret;
319 }
320
321 dsi_write(dsi, DSI_GEN_HDR, hdr_val);
322
323 mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
324 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
325 val, (val & mask) == mask,
326 CMD_PKT_STATUS_TIMEOUT_US);
327 if (ret) {
Sean Anderson4723fd52020-09-15 10:45:20 -0400328 dev_err(dsi->dsi_host.dev, "failed to write command FIFO\n");
Yannick Fertréd4f7ea82019-10-07 15:29:06 +0200329 return ret;
330 }
331
332 return 0;
333}
334
335static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
336 const struct mipi_dsi_packet *packet)
337{
338 const u8 *tx_buf = packet->payload;
339 int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret;
340 __le32 word;
341 u32 val;
342
343 while (len) {
344 if (len < pld_data_bytes) {
345 word = 0;
346 memcpy(&word, tx_buf, len);
347 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
348 len = 0;
349 } else {
350 memcpy(&word, tx_buf, pld_data_bytes);
351 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
352 tx_buf += pld_data_bytes;
353 len -= pld_data_bytes;
354 }
355
356 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
357 val, !(val & GEN_PLD_W_FULL),
358 CMD_PKT_STATUS_TIMEOUT_US);
359 if (ret) {
Sean Anderson4723fd52020-09-15 10:45:20 -0400360 dev_err(dsi->dsi_host.dev,
Yannick Fertréd4f7ea82019-10-07 15:29:06 +0200361 "failed to get available write payload FIFO\n");
362 return ret;
363 }
364 }
365
366 word = 0;
367 memcpy(&word, packet->header, sizeof(packet->header));
368 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, le32_to_cpu(word));
369}
370
371static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
372 const struct mipi_dsi_msg *msg)
373{
374 int i, j, ret, len = msg->rx_len;
375 u8 *buf = msg->rx_buf;
376 u32 val;
377
378 /* Wait end of the read operation */
379 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
380 val, !(val & GEN_RD_CMD_BUSY),
381 CMD_PKT_STATUS_TIMEOUT_US);
382 if (ret) {
Sean Anderson4723fd52020-09-15 10:45:20 -0400383 dev_err(dsi->dsi_host.dev, "Timeout during read operation\n");
Yannick Fertréd4f7ea82019-10-07 15:29:06 +0200384 return ret;
385 }
386
387 for (i = 0; i < len; i += 4) {
388 /* Read fifo must not be empty before all bytes are read */
389 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
390 val, !(val & GEN_PLD_R_EMPTY),
391 CMD_PKT_STATUS_TIMEOUT_US);
392 if (ret) {
Sean Anderson4723fd52020-09-15 10:45:20 -0400393 dev_err(dsi->dsi_host.dev,
394 "Read payload FIFO is empty\n");
Yannick Fertréd4f7ea82019-10-07 15:29:06 +0200395 return ret;
396 }
397
398 val = dsi_read(dsi, DSI_GEN_PLD_DATA);
399 for (j = 0; j < 4 && j + i < len; j++)
400 buf[i + j] = val >> (8 * j);
401 }
402
403 return ret;
404}
405
406static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
407 const struct mipi_dsi_msg *msg)
408{
409 struct dw_mipi_dsi *dsi = host_to_dsi(host);
410 struct mipi_dsi_packet packet;
411 int ret, nb_bytes;
412
413 ret = mipi_dsi_create_packet(&packet, msg);
414 if (ret) {
Sean Anderson4723fd52020-09-15 10:45:20 -0400415 dev_err(host->dev, "failed to create packet: %d\n", ret);
Yannick Fertréd4f7ea82019-10-07 15:29:06 +0200416 return ret;
417 }
418
419 dw_mipi_message_config(dsi, msg);
420
421 ret = dw_mipi_dsi_write(dsi, &packet);
422 if (ret)
423 return ret;
424
425 if (msg->rx_buf && msg->rx_len) {
426 ret = dw_mipi_dsi_read(dsi, msg);
427 if (ret)
428 return ret;
429 nb_bytes = msg->rx_len;
430 } else {
431 nb_bytes = packet.size;
432 }
433
434 return nb_bytes;
435}
436
437static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
438 .attach = dw_mipi_dsi_host_attach,
439 .transfer = dw_mipi_dsi_host_transfer,
440};
441
442static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
443{
444 struct mipi_dsi_device *device = dsi->device;
445 u32 val;
446
447 /*
448 * TODO dw drv improvements
449 * enabling low power is panel-dependent, we should use the
450 * panel configuration here...
451 */
452 val = ENABLE_LOW_POWER;
453
454 if (device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
455 val |= VID_MODE_TYPE_BURST;
456 else if (device->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
457 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
458 else
459 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
460
461 dsi_write(dsi, DSI_VID_MODE_CFG, val);
462}
463
464static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
465 unsigned long mode_flags)
466{
467 const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
468
469 dsi_write(dsi, DSI_PWR_UP, RESET);
470
471 if (mode_flags & MIPI_DSI_MODE_VIDEO) {
472 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
473 dw_mipi_dsi_video_mode_config(dsi);
474 dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
475 } else {
476 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
477 }
478
479 if (phy_ops->post_set_mode)
480 phy_ops->post_set_mode(dsi->device, mode_flags);
481
482 dsi_write(dsi, DSI_PWR_UP, POWERUP);
483}
484
485static void dw_mipi_dsi_init_pll(struct dw_mipi_dsi *dsi)
486{
Neil Armstrong01c98572020-10-02 11:16:09 +0200487 const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
488 unsigned int esc_rate;
489 u32 esc_clk_division;
490
Yannick Fertréd4f7ea82019-10-07 15:29:06 +0200491 /*
492 * The maximum permitted escape clock is 20MHz and it is derived from
Neil Armstrong01c98572020-10-02 11:16:09 +0200493 * lanebyteclk, which is running at "lane_mbps / 8".
Yannick Fertréd4f7ea82019-10-07 15:29:06 +0200494 */
Neil Armstrong01c98572020-10-02 11:16:09 +0200495 if (phy_ops->get_esc_clk_rate)
496 phy_ops->get_esc_clk_rate(dsi->device, &esc_rate);
497 else
498 esc_rate = 20; /* Default to 20MHz */
499
500 /*
501 * We want:
502 *
503 * (lane_mbps >> 3) / esc_clk_division < X
504 * which is:
505 * (lane_mbps >> 3) / X > esc_clk_division
506 */
507 esc_clk_division = (dsi->lane_mbps >> 3) / esc_rate + 1;
Yannick Fertréd4f7ea82019-10-07 15:29:06 +0200508
509 dsi_write(dsi, DSI_PWR_UP, RESET);
510
511 /*
512 * TODO dw drv improvements
513 * timeout clock division should be computed with the
514 * high speed transmission counter timeout and byte lane...
515 */
516 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
517 TX_ESC_CLK_DIVISION(esc_clk_division));
518}
519
520static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
521 struct display_timing *timings)
522{
523 struct mipi_dsi_device *device = dsi->device;
524 u32 val = 0, color = 0;
525
526 switch (device->format) {
527 case MIPI_DSI_FMT_RGB888:
528 color = DPI_COLOR_CODING_24BIT;
529 break;
530 case MIPI_DSI_FMT_RGB666:
531 color = DPI_COLOR_CODING_18BIT_2 | LOOSELY18_EN;
532 break;
533 case MIPI_DSI_FMT_RGB666_PACKED:
534 color = DPI_COLOR_CODING_18BIT_1;
535 break;
536 case MIPI_DSI_FMT_RGB565:
537 color = DPI_COLOR_CODING_16BIT_1;
538 break;
539 }
540
541 if (device->mode_flags & DISPLAY_FLAGS_VSYNC_HIGH)
542 val |= VSYNC_ACTIVE_LOW;
543 if (device->mode_flags & DISPLAY_FLAGS_HSYNC_HIGH)
544 val |= HSYNC_ACTIVE_LOW;
545
546 dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));
547 dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
548 dsi_write(dsi, DSI_DPI_CFG_POL, val);
549 /*
550 * TODO dw drv improvements
551 * largest packet sizes during hfp or during vsa/vpb/vfp
552 * should be computed according to byte lane, lane number and only
553 * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
554 */
555 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
556 | INVACT_LPCMD_TIME(4));
557}
558
559static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
560{
561 dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
562}
563
564static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
565 struct display_timing *timings)
566{
567 /*
568 * TODO dw drv improvements
569 * only burst mode is supported here. For non-burst video modes,
570 * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC &
571 * DSI_VNPCR.NPSIZE... especially because this driver supports
572 * non-burst video modes, see dw_mipi_dsi_video_mode_config()...
573 */
574 dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(timings->hactive.typ));
575}
576
577static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
578{
579 const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
580
581 /*
582 * TODO dw drv improvements
583 * compute high speed transmission counter timeout according
584 * to the timeout clock division (TO_CLK_DIVISION) and byte lane...
585 */
586 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
587 /*
588 * TODO dw drv improvements
589 * the Bus-Turn-Around Timeout Counter should be computed
590 * according to byte lane...
591 */
592 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
593 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
594
595 if (phy_ops->post_set_mode)
596 phy_ops->post_set_mode(dsi->device, 0);
597}
598
599/* Get lane byte clock cycles. */
600static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
601 struct display_timing *timings,
602 u32 hcomponent)
603{
604 u32 frac, lbcc;
605
606 lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
607
608 frac = lbcc % (timings->pixelclock.typ / 1000);
609 lbcc = lbcc / (timings->pixelclock.typ / 1000);
610 if (frac)
611 lbcc++;
612
613 return lbcc;
614}
615
616static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
617 struct display_timing *timings)
618{
619 u32 htotal, hsa, hbp, lbcc;
620
621 htotal = timings->hactive.typ + timings->hfront_porch.typ +
622 timings->hback_porch.typ + timings->hsync_len.typ;
623
John Keeping72092722022-09-07 12:06:32 +0100624 hsa = timings->hsync_len.typ;
625 hbp = timings->hback_porch.typ;
Yannick Fertréd4f7ea82019-10-07 15:29:06 +0200626
627 /*
628 * TODO dw drv improvements
629 * computations below may be improved...
630 */
631 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, timings, htotal);
632 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
633
634 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, timings, hsa);
635 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
636
637 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, timings, hbp);
638 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
639}
640
641static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
642 struct display_timing *timings)
643{
644 u32 vactive, vsa, vfp, vbp;
645
646 vactive = timings->vactive.typ;
John Keeping72092722022-09-07 12:06:32 +0100647 vsa = timings->vsync_len.typ;
Yannick Fertréd4f7ea82019-10-07 15:29:06 +0200648 vfp = timings->vfront_porch.typ;
John Keeping72092722022-09-07 12:06:32 +0100649 vbp = timings->vback_porch.typ;
Yannick Fertréd4f7ea82019-10-07 15:29:06 +0200650
651 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
652 dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
653 dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
654 dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
655}
656
657static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
658{
Neil Armstrongb53c1222020-10-02 11:16:08 +0200659 const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
660 struct mipi_dsi_phy_timing timing = {0x40, 0x40, 0x40, 0x40};
Yannick Fertréd4f7ea82019-10-07 15:29:06 +0200661 u32 hw_version;
662
Neil Armstrongb53c1222020-10-02 11:16:08 +0200663 if (phy_ops->get_timing)
664 phy_ops->get_timing(dsi->device, dsi->lane_mbps, &timing);
665
Yannick Fertréd4f7ea82019-10-07 15:29:06 +0200666 /*
667 * TODO dw drv improvements
668 * data & clock lane timers should be computed according to panel
669 * blankings and to the automatic clock lane control mode...
670 * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with
671 * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
672 */
673
674 hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
675
676 if (hw_version >= HWVER_131) {
Neil Armstrongb53c1222020-10-02 11:16:08 +0200677 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME_V131(timing.data_hs2lp) |
678 PHY_LP2HS_TIME_V131(timing.data_lp2hs));
Yannick Fertréd4f7ea82019-10-07 15:29:06 +0200679 dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));
680 } else {
Neil Armstrongb53c1222020-10-02 11:16:08 +0200681 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(timing.data_hs2lp) |
682 PHY_LP2HS_TIME(timing.data_lp2hs) | MAX_RD_TIME(10000));
Yannick Fertréd4f7ea82019-10-07 15:29:06 +0200683 }
684
Neil Armstrongb53c1222020-10-02 11:16:08 +0200685 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(timing.clk_hs2lp)
686 | PHY_CLKLP2HS_TIME(timing.clk_lp2hs));
Yannick Fertréd4f7ea82019-10-07 15:29:06 +0200687}
688
689static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
690{
691 struct mipi_dsi_device *device = dsi->device;
692
693 /*
694 * TODO dw drv improvements
695 * stop wait time should be the maximum between host dsi
696 * and panel stop wait times
697 */
698 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
699 N_LANES(device->lanes));
700}
701
702static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
703{
704 /* Clear PHY state */
705 dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
706 | PHY_RSTZ | PHY_SHUTDOWNZ);
707 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
708 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
709 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
710}
711
712static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
713{
714 u32 val;
715 int ret;
716
717 dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
718 PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
719
720 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,
721 val & PHY_LOCK, PHY_STATUS_TIMEOUT_US);
722 if (ret)
Yannick Fertrec45f82b2021-03-04 13:14:36 +0100723 dev_dbg(dsi->dsi_host.dev,
724 "failed to wait phy lock state\n");
Yannick Fertréd4f7ea82019-10-07 15:29:06 +0200725
726 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
727 val, val & PHY_STOP_STATE_CLK_LANE,
728 PHY_STATUS_TIMEOUT_US);
729 if (ret)
Yannick Fertrec45f82b2021-03-04 13:14:36 +0100730 dev_dbg(dsi->dsi_host.dev,
731 "failed to wait phy clk lane stop state\n");
Yannick Fertréd4f7ea82019-10-07 15:29:06 +0200732}
733
734static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
735{
736 dsi_read(dsi, DSI_INT_ST0);
737 dsi_read(dsi, DSI_INT_ST1);
738 dsi_write(dsi, DSI_INT_MSK0, 0);
739 dsi_write(dsi, DSI_INT_MSK1, 0);
740}
741
742static void dw_mipi_dsi_bridge_set(struct dw_mipi_dsi *dsi,
743 struct display_timing *timings)
744{
745 const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
746 struct mipi_dsi_device *device = dsi->device;
747 int ret;
748
749 ret = phy_ops->get_lane_mbps(dsi->device, timings, device->lanes,
750 device->format, &dsi->lane_mbps);
751 if (ret)
Sean Anderson4723fd52020-09-15 10:45:20 -0400752 dev_warn(dsi->dsi_host.dev, "Phy get_lane_mbps() failed\n");
Yannick Fertréd4f7ea82019-10-07 15:29:06 +0200753
754 dw_mipi_dsi_init_pll(dsi);
755 dw_mipi_dsi_dpi_config(dsi, timings);
756 dw_mipi_dsi_packet_handler_config(dsi);
757 dw_mipi_dsi_video_mode_config(dsi);
758 dw_mipi_dsi_video_packet_config(dsi, timings);
759 dw_mipi_dsi_command_mode_config(dsi);
760 dw_mipi_dsi_line_timer_config(dsi, timings);
761 dw_mipi_dsi_vertical_timing_config(dsi, timings);
762
763 dw_mipi_dsi_dphy_init(dsi);
764 dw_mipi_dsi_dphy_timing_config(dsi);
765 dw_mipi_dsi_dphy_interface_config(dsi);
766
767 dw_mipi_dsi_clear_err(dsi);
768
769 ret = phy_ops->init(dsi->device);
770 if (ret)
Sean Anderson4723fd52020-09-15 10:45:20 -0400771 dev_warn(dsi->dsi_host.dev, "Phy init() failed\n");
Yannick Fertréd4f7ea82019-10-07 15:29:06 +0200772
773 dw_mipi_dsi_dphy_enable(dsi);
774
775 dw_mipi_dsi_wait_for_two_frames(timings);
776
777 /* Switch to cmd mode for panel-bridge pre_enable & panel prepare */
778 dw_mipi_dsi_set_mode(dsi, 0);
779}
780
781static int dw_mipi_dsi_init(struct udevice *dev,
782 struct mipi_dsi_device *device,
783 struct display_timing *timings,
784 unsigned int max_data_lanes,
785 const struct mipi_dsi_phy_ops *phy_ops)
786{
787 struct dw_mipi_dsi *dsi = dev_get_priv(dev);
788 struct clk clk;
789 int ret;
790
791 if (!phy_ops->init || !phy_ops->get_lane_mbps) {
792 dev_err(device->dev, "Phy not properly configured\n");
793 return -ENODEV;
794 }
795
796 dsi->phy_ops = phy_ops;
797 dsi->max_data_lanes = max_data_lanes;
798 dsi->device = device;
Yannick Fertre612f7692021-03-04 13:14:35 +0100799 dsi->dsi_host.dev = (struct device *)dev;
Yannick Fertréd4f7ea82019-10-07 15:29:06 +0200800 dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
801 device->host = &dsi->dsi_host;
802
803 dsi->base = (void *)dev_read_addr(device->dev);
804 if ((fdt_addr_t)dsi->base == FDT_ADDR_T_NONE) {
805 dev_err(device->dev, "dsi dt register address error\n");
806 return -EINVAL;
807 }
808
Chris Morgan6fa83832023-03-24 13:53:07 -0500809 /*
810 * The Rockchip based devices don't have px_clk, so simply move
811 * on.
812 */
813 if (IS_ENABLED(CONFIG_DISPLAY_ROCKCHIP_DW_MIPI)) {
814 dw_mipi_dsi_bridge_set(dsi, timings);
815 return 0;
816 }
817
Yannick Fertréd4f7ea82019-10-07 15:29:06 +0200818 ret = clk_get_by_name(device->dev, "px_clk", &clk);
819 if (ret) {
820 dev_err(device->dev, "peripheral clock get error %d\n", ret);
821 return ret;
822 }
823
824 /* get the pixel clock set by the clock framework */
825 timings->pixelclock.typ = clk_get_rate(&clk);
826
827 dw_mipi_dsi_bridge_set(dsi, timings);
828
829 return 0;
830}
831
832static int dw_mipi_dsi_enable(struct udevice *dev)
833{
834 struct dw_mipi_dsi *dsi = dev_get_priv(dev);
835
836 /* Switch to video mode for panel-bridge enable & panel enable */
837 dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO);
838
839 return 0;
840}
841
842struct dsi_host_ops dw_mipi_dsi_ops = {
843 .init = dw_mipi_dsi_init,
844 .enable = dw_mipi_dsi_enable,
845};
846
847static int dw_mipi_dsi_probe(struct udevice *dev)
848{
849 return 0;
850}
851
Yannick Fertréd4f7ea82019-10-07 15:29:06 +0200852U_BOOT_DRIVER(dw_mipi_dsi) = {
853 .name = "dw_mipi_dsi",
854 .id = UCLASS_DSI_HOST,
Yannick Fertréd4f7ea82019-10-07 15:29:06 +0200855 .probe = dw_mipi_dsi_probe,
856 .ops = &dw_mipi_dsi_ops,
Simon Glass41575d82020-12-03 16:55:17 -0700857 .priv_auto = sizeof(struct dw_mipi_dsi),
Yannick Fertréd4f7ea82019-10-07 15:29:06 +0200858};
859
860MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
861MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
862MODULE_AUTHOR("Yannick Fertré <yannick.fertre@st.com>");
863MODULE_DESCRIPTION("DW MIPI DSI host controller driver");
864MODULE_LICENSE("GPL");
865MODULE_ALIAS("platform:dw-mipi-dsi");