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Stefan Roese6983fe22008-03-11 16:52:24 +01001/*
2 * (C) Copyright 2008
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese6983fe22008-03-11 16:52:24 +01006 */
7
8/************************************************************************
9 * canyonlands.h - configuration for Canyonlands (460EX)
10 ***********************************************************************/
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
Simon Glass65660412015-02-07 11:51:37 -070014#include <linux/kconfig.h>
15
Stefan Roese6983fe22008-03-11 16:52:24 +010016/*-----------------------------------------------------------------------
17 * High Level Configuration Options
18 *----------------------------------------------------------------------*/
Adam Grahamf09f09d2008-10-08 10:12:53 -070019/*
20 * This config file is used for Canyonlands (460EX) Glacier (460GT)
21 * and Arches dual (460GT)
22 */
23#ifdef CONFIG_CANYONLANDS
Simon Glass0bca2842015-02-07 11:51:36 -070024#define CONFIG_460EX /* Specific PPC460EX */
Stefan Roese490f2042008-06-06 15:55:03 +020025#define CONFIG_HOSTNAME canyonlands
Adam Grahamf09f09d2008-10-08 10:12:53 -070026#else
Simon Glass0bca2842015-02-07 11:51:36 -070027#define CONFIG_460GT /* Specific PPC460GT */
Adam Grahamf09f09d2008-10-08 10:12:53 -070028#ifdef CONFIG_GLACIER
29#define CONFIG_HOSTNAME glacier
30#else
31#define CONFIG_HOSTNAME arches
32#define CONFIG_USE_NETDEV eth1
33#define CONFIG_BD_NUM_CPUS 2
Stefan Roese4c9e8552008-03-19 16:20:49 +010034#endif
Adam Grahamf09f09d2008-10-08 10:12:53 -070035#endif
36
Simon Glass0bca2842015-02-07 11:51:36 -070037#define CONFIG_440
Stefan Roese6983fe22008-03-11 16:52:24 +010038
Wolfgang Denk2ae18242010-10-06 09:05:45 +020039#ifndef CONFIG_SYS_TEXT_BASE
40#define CONFIG_SYS_TEXT_BASE 0xFFF80000
41#endif
42
Stefan Roese490f2042008-06-06 15:55:03 +020043/*
44 * Include common defines/options for all AMCC eval boards
45 */
46#include "amcc-common.h"
47
Stefan Roese6983fe22008-03-11 16:52:24 +010048#define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */
49
Simon Glass0bca2842015-02-07 11:51:36 -070050#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */
51#define CONFIG_MISC_INIT_R /* Call misc_init_r */
52#define CONFIG_BOARD_TYPES /* support board types */
Stefan Roese6983fe22008-03-11 16:52:24 +010053
54/*-----------------------------------------------------------------------
55 * Base addresses -- Note these are effective addresses where the
56 * actual resources get mapped (not physical addresses)
57 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020058#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
59#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
60#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
Stefan Roese6983fe22008-03-11 16:52:24 +010061
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020062#define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
63#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */
64#define CONFIG_SYS_PCIE_BASE 0xc4000000 /* PCIe UTL regs */
Stefan Roese6983fe22008-03-11 16:52:24 +010065
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000
67#define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000
68#define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000
69#define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000
Stefan Roese6983fe22008-03-11 16:52:24 +010070
Rupjyoti Sarmah17a68442010-07-07 18:14:48 +053071/*
72 * BCSR bits as defined in the Canyonlands board user manual.
73 */
74#define BCSR_USBCTRL_OTG_RST 0x32
75#define BCSR_USBCTRL_HOST_RST 0x01
76#define BCSR_SELECT_PCIE 0x10
77
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_PCIE0_UTLBASE 0xc08010000ULL /* 36bit physical addr */
Stefan Roese6983fe22008-03-11 16:52:24 +010079
80/* base address of inbound PCIe window */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#define CONFIG_SYS_PCIE_INBOUND_BASE 0x000000000ULL /* 36bit physical addr */
Stefan Roese6983fe22008-03-11 16:52:24 +010082
83/* EBC stuff */
Adam Grahamf09f09d2008-10-08 10:12:53 -070084#if !defined(CONFIG_ARCHES)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CONFIG_SYS_BCSR_BASE 0xE1000000
Adam Grahamf09f09d2008-10-08 10:12:53 -070086#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* later mapped to this addr */
87#define CONFIG_SYS_FLASH_SIZE (64 << 20)
88#else
89#define CONFIG_SYS_FPGA_BASE 0xE1000000
90#define CONFIG_SYS_CPLD_ADDR (CONFIG_SYS_FPGA_BASE + 0x00080000)
91#define CONFIG_SYS_CPLD_DATA (CONFIG_SYS_FPGA_BASE + 0x00080002)
92#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* later mapped to this addr */
93#define CONFIG_SYS_FLASH_SIZE (32 << 20)
94#endif
95
96#define CONFIG_SYS_NAND_ADDR 0xE0000000
97#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space: 0xFF000000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4
99#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xCC000000
Adam Grahamf09f09d2008-10-08 10:12:53 -0700100#define CONFIG_SYS_FLASH_BASE_PHYS (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) | \
101 (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
Stefan Roese6983fe22008-03-11 16:52:24 +0100102
Dave Mitchellddf45cc2008-11-20 14:09:50 -0600103#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */
Wolfgang Denkbf560802010-09-10 23:04:05 +0200105#define CONFIG_SYS_SRAM_SIZE (256 << 10)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000
Stefan Roese6983fe22008-03-11 16:52:24 +0100107
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_AHB_BASE 0xE2000000 /* internal AHB peripherals */
Stefan Roese41712b42008-03-05 12:31:53 +0100109
Stefan Roese6983fe22008-03-11 16:52:24 +0100110/*-----------------------------------------------------------------------
111 * Initial RAM & stack pointer (placed in OCM)
112 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200114#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200115#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Stefan Roese6983fe22008-03-11 16:52:24 +0100117
118/*-----------------------------------------------------------------------
119 * Serial Port
120 *----------------------------------------------------------------------*/
Stefan Roese550650d2010-09-20 16:05:31 +0200121#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Stefan Roese6983fe22008-03-11 16:52:24 +0100122
Stefan Roese6983fe22008-03-11 16:52:24 +0100123/*-----------------------------------------------------------------------
124 * Environment
125 *----------------------------------------------------------------------*/
126/*
127 * Define here the location of the environment variables (FLASH).
128 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200129#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Felix Radensky26d37f02009-06-22 15:30:42 +0300130#define CONFIG_SYS_NOR_CS 0 /* NOR chip connected to CSx */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */
Stefan Roese6983fe22008-03-11 16:52:24 +0100132
133/*-----------------------------------------------------------------------
134 * FLASH related
135 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200137#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Simon Glass0bca2842015-02-07 11:51:36 -0700138#define CONFIG_SYS_FLASH_CFI_AMD_RESET /* Use AMD (Spansion) reset cmd */
Stefan Roese6983fe22008-03-11 16:52:24 +0100139
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
141#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
142#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
Stefan Roese6983fe22008-03-11 16:52:24 +0100143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
145#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Stefan Roese6983fe22008-03-11 16:52:24 +0100146
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
148#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Stefan Roese6983fe22008-03-11 16:52:24 +0100149
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200150#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200151#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200153#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
Stefan Roese6983fe22008-03-11 16:52:24 +0100154
155/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200156#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
157#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200158#endif /* CONFIG_ENV_IS_IN_FLASH */
Stefan Roese6983fe22008-03-11 16:52:24 +0100159
160/*-----------------------------------------------------------------------
161 * NAND-FLASH related
162 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_MAX_NAND_DEVICE 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
165#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
Stefan Roese6983fe22008-03-11 16:52:24 +0100166
167/*------------------------------------------------------------------------------
168 * DDR SDRAM
169 *----------------------------------------------------------------------------*/
Adam Grahamf09f09d2008-10-08 10:12:53 -0700170#if !defined(CONFIG_ARCHES)
Stefan Roese71665eb2008-03-03 17:27:02 +0100171/*
172 * NAND booting U-Boot version uses a fixed initialization, since the whole
173 * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
174 * code.
175 */
Simon Glass0bca2842015-02-07 11:51:36 -0700176#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
Stefan Roese6983fe22008-03-11 16:52:24 +0100177#define SPD_EEPROM_ADDRESS {0x50, 0x51} /* SPD i2c spd addresses*/
Simon Glass0bca2842015-02-07 11:51:36 -0700178#define CONFIG_DDR_ECC /* with ECC support */
Stefan Roese6983fe22008-03-11 16:52:24 +0100179#define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */
Adam Grahamf09f09d2008-10-08 10:12:53 -0700180
181#else /* defined(CONFIG_ARCHES) */
182
183#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
184
185#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
186#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
187#undef CONFIG_PPC4xx_DDR_METHOD_A
188
189/* DDR1/2 SDRAM Device Control Register Data Values */
190/* Memory Queue */
191#define CONFIG_SYS_SDRAM_R0BAS 0x0000f000
192#define CONFIG_SYS_SDRAM_R1BAS 0x00000000
193#define CONFIG_SYS_SDRAM_R2BAS 0x00000000
194#define CONFIG_SYS_SDRAM_R3BAS 0x00000000
195#define CONFIG_SYS_SDRAM_PLBADDULL 0x00000000
196#define CONFIG_SYS_SDRAM_PLBADDUHB 0x00000008
197#define CONFIG_SYS_SDRAM_CONF1LL 0x00001080
198#define CONFIG_SYS_SDRAM_CONF1HB 0x00001080
199#define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000
200
201/* SDRAM Controller */
202#define CONFIG_SYS_SDRAM0_MB0CF 0x00000701
203#define CONFIG_SYS_SDRAM0_MB1CF 0x00000000
204#define CONFIG_SYS_SDRAM0_MB2CF 0x00000000
205#define CONFIG_SYS_SDRAM0_MB3CF 0x00000000
206#define CONFIG_SYS_SDRAM0_MCOPT1 0x05322000
207#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
208#define CONFIG_SYS_SDRAM0_MODT0 0x01000000
209#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
210#define CONFIG_SYS_SDRAM0_MODT2 0x00000000
211#define CONFIG_SYS_SDRAM0_MODT3 0x00000000
212#define CONFIG_SYS_SDRAM0_CODT 0x00800021
213#define CONFIG_SYS_SDRAM0_RTR 0x06180000
214#define CONFIG_SYS_SDRAM0_INITPLR0 0xb5380000
215#define CONFIG_SYS_SDRAM0_INITPLR1 0x82100400
216#define CONFIG_SYS_SDRAM0_INITPLR2 0x80820000
217#define CONFIG_SYS_SDRAM0_INITPLR3 0x80830000
218#define CONFIG_SYS_SDRAM0_INITPLR4 0x80810040
219#define CONFIG_SYS_SDRAM0_INITPLR5 0x80800532
220#define CONFIG_SYS_SDRAM0_INITPLR6 0x82100400
221#define CONFIG_SYS_SDRAM0_INITPLR7 0x8a080000
222#define CONFIG_SYS_SDRAM0_INITPLR8 0x8a080000
223#define CONFIG_SYS_SDRAM0_INITPLR9 0x8a080000
224#define CONFIG_SYS_SDRAM0_INITPLR10 0x8a080000
225#define CONFIG_SYS_SDRAM0_INITPLR11 0x80000432
226#define CONFIG_SYS_SDRAM0_INITPLR12 0x808103c0
227#define CONFIG_SYS_SDRAM0_INITPLR13 0x80810040
228#define CONFIG_SYS_SDRAM0_INITPLR14 0x00000000
229#define CONFIG_SYS_SDRAM0_INITPLR15 0x00000000
230#define CONFIG_SYS_SDRAM0_RQDC 0x80000038
231#define CONFIG_SYS_SDRAM0_RFDC 0x00000257
232#define CONFIG_SYS_SDRAM0_RDCC 0x40000000
233#define CONFIG_SYS_SDRAM0_DLCR 0x03000091
234#define CONFIG_SYS_SDRAM0_CLKTR 0x40000000
235#define CONFIG_SYS_SDRAM0_WRDTR 0x82000823
236#define CONFIG_SYS_SDRAM0_SDTR1 0x80201000
237#define CONFIG_SYS_SDRAM0_SDTR2 0x42204243
238#define CONFIG_SYS_SDRAM0_SDTR3 0x090c0d1a
239#define CONFIG_SYS_SDRAM0_MMODE 0x00000432
240#define CONFIG_SYS_SDRAM0_MEMODE 0x00000004
241#endif /* !defined(CONFIG_ARCHES) */
Adam Grahamf09f09d2008-10-08 10:12:53 -0700242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_MBYTES_SDRAM 512 /* 512MB */
Stefan Roese6983fe22008-03-11 16:52:24 +0100244
245/*-----------------------------------------------------------------------
246 * I2C
247 *----------------------------------------------------------------------*/
Dirk Eibach880540d2013-04-25 02:40:01 +0000248#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
Stefan Roese6983fe22008-03-11 16:52:24 +0100249
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
251#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
252#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
253#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Stefan Roese6983fe22008-03-11 16:52:24 +0100254
Stefan Roese87c0b722009-07-20 06:57:27 +0200255/* I2C bootstrap EEPROM */
Stefan Roese514bab62009-08-17 16:57:53 +0200256#if defined(CONFIG_ARCHES)
257#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54
258#else
Stefan Roese87c0b722009-07-20 06:57:27 +0200259#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
Stefan Roese514bab62009-08-17 16:57:53 +0200260#endif
Stefan Roese87c0b722009-07-20 06:57:27 +0200261#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
262#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
263
Stefan Roese6983fe22008-03-11 16:52:24 +0100264/* I2C SYSMON (LM75, AD7414 is almost compatible) */
Simon Glass0bca2842015-02-07 11:51:36 -0700265#define CONFIG_DTT_LM75 /* ON Semi's LM75 */
266#define CONFIG_DTT_AD7414 /* use AD7414 */
Stefan Roese6983fe22008-03-11 16:52:24 +0100267#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_DTT_MAX_TEMP 70
269#define CONFIG_SYS_DTT_LOW_TEMP -30
270#define CONFIG_SYS_DTT_HYSTERESIS 3
Stefan Roese6983fe22008-03-11 16:52:24 +0100271
Adam Grahamf09f09d2008-10-08 10:12:53 -0700272#if defined(CONFIG_ARCHES)
273#define CONFIG_SYS_I2C_DTT_ADDR 0x4a /* AD7414 I2C address */
274#endif
275
276#if !defined(CONFIG_ARCHES)
Stefan Roese6983fe22008-03-11 16:52:24 +0100277/* RTC configuration */
Simon Glass0bca2842015-02-07 11:51:36 -0700278#define CONFIG_RTC_M41T62
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Adam Grahamf09f09d2008-10-08 10:12:53 -0700280#endif
Stefan Roese6983fe22008-03-11 16:52:24 +0100281
282/*-----------------------------------------------------------------------
283 * Ethernet
284 *----------------------------------------------------------------------*/
Simon Glass0bca2842015-02-07 11:51:36 -0700285#define CONFIG_IBM_EMAC4_V4
Adam Grahamf09f09d2008-10-08 10:12:53 -0700286
Stefan Roese4c9e8552008-03-19 16:20:49 +0100287#define CONFIG_HAS_ETH0
288#define CONFIG_HAS_ETH1
Adam Grahamf09f09d2008-10-08 10:12:53 -0700289
290#if !defined(CONFIG_ARCHES)
291#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
292#define CONFIG_PHY1_ADDR 1
Stefan Roese4c9e8552008-03-19 16:20:49 +0100293/* Only Glacier (460GT) has 4 EMAC interfaces */
294#ifdef CONFIG_460GT
295#define CONFIG_PHY2_ADDR 2
296#define CONFIG_PHY3_ADDR 3
297#define CONFIG_HAS_ETH2
298#define CONFIG_HAS_ETH3
299#endif
Stefan Roese6983fe22008-03-11 16:52:24 +0100300
Adam Grahamf09f09d2008-10-08 10:12:53 -0700301#else /* defined(CONFIG_ARCHES) */
302
303#define CONFIG_FIXED_PHY 0xFFFFFFFF
304#define CONFIG_PHY_ADDR CONFIG_FIXED_PHY
305#define CONFIG_PHY1_ADDR 0
306#define CONFIG_PHY2_ADDR 1
307#define CONFIG_HAS_ETH2
308
309#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
310 {devnum, speed, duplex}
311#define CONFIG_SYS_FIXED_PHY_PORTS \
312 CONFIG_SYS_FIXED_PHY_PORT(0, 1000, FULL)
313
314#define CONFIG_M88E1112_PHY
315
316/*
317 * For the GPCS_PHYx_ADDR PHY address, choose some PHY address not
318 * used by CONFIG_PHYx_ADDR
319 */
320#define CONFIG_GPCS_PHY_ADDR 0xA
321#define CONFIG_GPCS_PHY1_ADDR 0xB
322#define CONFIG_GPCS_PHY2_ADDR 0xC
323#endif /* !defined(CONFIG_ARCHES) */
324
Simon Glass0bca2842015-02-07 11:51:36 -0700325#define CONFIG_PHY_RESET /* reset phy upon startup */
326#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
327#define CONFIG_PHY_DYNAMIC_ANEG
Stefan Roese6983fe22008-03-11 16:52:24 +0100328
Stefan Roese41712b42008-03-05 12:31:53 +0100329/*-----------------------------------------------------------------------
330 * USB-OHCI
331 *----------------------------------------------------------------------*/
Stefan Roese4c9e8552008-03-19 16:20:49 +0100332/* Only Canyonlands (460EX) has USB */
333#ifdef CONFIG_460EX
Stefan Roese41712b42008-03-05 12:31:53 +0100334#define CONFIG_USB_OHCI_NEW
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#undef CONFIG_SYS_OHCI_BE_CONTROLLER /* 460EX has little endian descriptors */
336#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS /* 460EX has little endian register */
337#define CONFIG_SYS_OHCI_USE_NPS /* force NoPowerSwitching mode */
338#define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_AHB_BASE | 0xd0000)
339#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
340#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
Rupjyoti Sarmah17a68442010-07-07 18:14:48 +0530341#define CONFIG_SYS_USB_OHCI_BOARD_INIT
Stefan Roese4c9e8552008-03-19 16:20:49 +0100342#endif
Stefan Roese41712b42008-03-05 12:31:53 +0100343
Stefan Roese490f2042008-06-06 15:55:03 +0200344/*
345 * Default environment variables
346 */
Adam Grahamf09f09d2008-10-08 10:12:53 -0700347#if !defined(CONFIG_ARCHES)
348#define CONFIG_EXTRA_ENV_SETTINGS \
Stefan Roese490f2042008-06-06 15:55:03 +0200349 CONFIG_AMCC_DEF_ENV \
350 CONFIG_AMCC_DEF_ENV_POWERPC \
351 CONFIG_AMCC_DEF_ENV_NOR_UPD \
Stefan Roese6983fe22008-03-11 16:52:24 +0100352 "kernel_addr=fc000000\0" \
Stefan Roese5d40d442008-04-22 14:14:20 +0200353 "fdt_addr=fc1e0000\0" \
Stefan Roese6983fe22008-03-11 16:52:24 +0100354 "ramdisk_addr=fc200000\0" \
Stefan Roese6983fe22008-03-11 16:52:24 +0100355 "pciconfighost=1\0" \
356 "pcie_mode=RP:RP\0" \
357 ""
Adam Grahamf09f09d2008-10-08 10:12:53 -0700358#else /* defined(CONFIG_ARCHES) */
359#define CONFIG_EXTRA_ENV_SETTINGS \
360 CONFIG_AMCC_DEF_ENV \
361 CONFIG_AMCC_DEF_ENV_POWERPC \
362 CONFIG_AMCC_DEF_ENV_NOR_UPD \
363 "kernel_addr=fe000000\0" \
364 "fdt_addr=fe1e0000\0" \
365 "ramdisk_addr=fe200000\0" \
366 "pciconfighost=1\0" \
367 "pcie_mode=RP:RP\0" \
368 "ethprime=ppc_4xx_eth1\0" \
369 ""
370#endif /* !defined(CONFIG_ARCHES) */
Stefan Roese6983fe22008-03-11 16:52:24 +0100371
372/*
Stefan Roese490f2042008-06-06 15:55:03 +0200373 * Commands additional to the ones defined in amcc-common.h
Stefan Roese6983fe22008-03-11 16:52:24 +0100374 */
Stefan Roese87c0b722009-07-20 06:57:27 +0200375#define CONFIG_CMD_CHIP_CONFIG
Adam Grahamf09f09d2008-10-08 10:12:53 -0700376#if defined(CONFIG_ARCHES)
377#define CONFIG_CMD_DTT
378#define CONFIG_CMD_PCI
379#define CONFIG_CMD_SDRAM
380#elif defined(CONFIG_CANYONLANDS)
381#define CONFIG_CMD_DATE
382#define CONFIG_CMD_DTT
Adam Grahamf09f09d2008-10-08 10:12:53 -0700383#define CONFIG_CMD_NAND
384#define CONFIG_CMD_PCI
Kazuaki Ichinohee405afa2009-06-12 18:10:12 +0900385#define CONFIG_CMD_SATA
Adam Grahamf09f09d2008-10-08 10:12:53 -0700386#define CONFIG_CMD_SDRAM
Adam Grahamf09f09d2008-10-08 10:12:53 -0700387#elif defined(CONFIG_GLACIER)
Stefan Roese6983fe22008-03-11 16:52:24 +0100388#define CONFIG_CMD_DATE
Stefan Roese6983fe22008-03-11 16:52:24 +0100389#define CONFIG_CMD_DTT
Stefan Roese6983fe22008-03-11 16:52:24 +0100390#define CONFIG_CMD_NAND
Stefan Roese6983fe22008-03-11 16:52:24 +0100391#define CONFIG_CMD_PCI
Stefan Roese6983fe22008-03-11 16:52:24 +0100392#define CONFIG_CMD_SDRAM
Adam Grahamf09f09d2008-10-08 10:12:53 -0700393#else
394#error "board type not defined"
Stefan Roese4c9e8552008-03-19 16:20:49 +0100395#endif
Stefan Roese41712b42008-03-05 12:31:53 +0100396
397/* Partitions */
Stefan Roese6983fe22008-03-11 16:52:24 +0100398
399/*-----------------------------------------------------------------------
Stefan Roese6983fe22008-03-11 16:52:24 +0100400 * PCI stuff
401 *----------------------------------------------------------------------*/
402/* General PCI */
Gabor Juhos842033e2013-05-30 07:06:12 +0000403#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Stefan Roese6983fe22008-03-11 16:52:24 +0100404#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
405#define CONFIG_PCI_CONFIG_HOST_BRIDGE
406
407/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200408#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
409#undef CONFIG_SYS_PCI_MASTER_INIT
Stefan Roese6983fe22008-03-11 16:52:24 +0100410
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
412#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
Stefan Roese6983fe22008-03-11 16:52:24 +0100413
Adam Grahamf09f09d2008-10-08 10:12:53 -0700414#ifdef CONFIG_460GT
415#if defined(CONFIG_ARCHES)
416/*-----------------------------------------------------------------------
417 * RapidIO I/O and Registers
418 *----------------------------------------------------------------------*/
419#define CONFIG_RAPIDIO
420#define CONFIG_SYS_460GT_SRIO_ERRATA_1
421
422#define SRGPL0_REG_BAR 0x0000000DAA000000ull /* 16MB */
423#define SRGPL0_CFG_BAR 0x0000000DAB000000ull /* 16MB */
424#define SRGPL0_MNT_BAR 0x0000000DAC000000ull /* 16MB */
425#define SRGPL0_MSG_BAR 0x0000000DAD000000ull /* 16MB */
426#define SRGPL0_OUT_BAR 0x0000000DB0000000ull /* 256MB */
427
428#define CONFIG_SYS_SRGPL0_REG_BAR 0xAA000000 /* 16MB */
429#define CONFIG_SYS_SRGPL0_CFG_BAR 0xAB000000 /* 16MB */
430#define CONFIG_SYS_SRGPL0_MNT_BAR 0xAC000000 /* 16MB */
431#define CONFIG_SYS_SRGPL0_MSG_BAR 0xAD000000 /* 16MB */
432
433#define CONFIG_SYS_I2ODMA_BASE 0xCF000000
434#define CONFIG_SYS_I2ODMA_PHYS_ADDR 0x0000000400100000ull
435
436#define CONFIG_PPC4XX_RAPIDIO_PROMISCUOUS_MODE
437#undef CONFIG_PPC4XX_RAPIDIO_DEBUG
438#undef CONFIG_PPC4XX_RAPIDIO_IN_BAR_USE_OCM
439#define CONFIG_PPC4XX_RAPIDIO_USE_HB_PLB
440#undef CONFIG_PPC4XX_RAPIDIO_LOOPBACK
441#endif /* CONFIG_ARCHES */
442#endif /* CONFIG_460GT */
443
Kazuaki Ichinohee405afa2009-06-12 18:10:12 +0900444/*
445 * SATA driver setup
446 */
447#ifdef CONFIG_CMD_SATA
448#define CONFIG_SATA_DWC
449#define CONFIG_LIBATA
450#define SATA_BASE_ADDR 0xe20d1000 /* PPC460EX SATA Base Address */
451#define SATA_DMA_REG_ADDR 0xe20d0800 /* PPC460EX SATA Base Address */
452#define CONFIG_SYS_SATA_MAX_DEVICE 1 /* SATA MAX DEVICE */
453/* Convert sectorsize to wordsize */
454#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
455#endif
456
Stefan Roese6983fe22008-03-11 16:52:24 +0100457/*-----------------------------------------------------------------------
458 * External Bus Controller (EBC) Setup
459 *----------------------------------------------------------------------*/
460
461/*
462 * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
463 * boot EBC mapping only supports a maximum of 16MBytes
464 * (4.ff00.0000 - 4.ffff.ffff).
465 * To solve this problem, the FLASH has to get remapped to another
466 * EBC address which accepts bigger regions:
467 *
468 * 0xfc00.0000 -> 4.cc00.0000
Adam Grahamf09f09d2008-10-08 10:12:53 -0700469 *
470 * Arches has 32MBytes of NOR FLASH (Spansion 29GL256), it will be
471 * remapped to:
472 *
473 * 0xfe00.0000 -> 4.ce00.0000
Stefan Roese6983fe22008-03-11 16:52:24 +0100474 */
475
476/* Memory Bank 0 (NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200477#define CONFIG_SYS_EBC_PB0AP 0x10055e00
478#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
Stefan Roese6983fe22008-03-11 16:52:24 +0100479
Adam Grahamf09f09d2008-10-08 10:12:53 -0700480#if !defined(CONFIG_ARCHES)
Stefan Roese6983fe22008-03-11 16:52:24 +0100481/* Memory Bank 3 (NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200482#define CONFIG_SYS_EBC_PB3AP 0x018003c0
483#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
Stefan Roese71665eb2008-03-03 17:27:02 +0100484#endif
485
Adam Grahamf09f09d2008-10-08 10:12:53 -0700486#if !defined(CONFIG_ARCHES)
Stefan Roese71665eb2008-03-03 17:27:02 +0100487/* Memory Bank 2 (CPLD) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200488#define CONFIG_SYS_EBC_PB2AP 0x00804240
489#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_BCSR_BASE | 0x18000) /* BAS=CPLD,BS=1M,BU=RW,BW=32bit */
Stefan Roese6983fe22008-03-11 16:52:24 +0100490
Adam Grahamf09f09d2008-10-08 10:12:53 -0700491#else /* defined(CONFIG_ARCHES) */
492
493/* Memory Bank 1 (FPGA) initialization */
494#define CONFIG_SYS_EBC_PB1AP 0x7f8ffe80
495#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FPGA_BASE | 0x3a000) /* BAS=FPGA,BS=2MB,BU=R/W,BW=16bit*/
496#endif /* !defined(CONFIG_ARCHES) */
497
Stefan Roese916ed942009-10-29 18:37:45 +0100498#define CONFIG_SYS_EBC_CFG 0xbfc00000
Stefan Roese6983fe22008-03-11 16:52:24 +0100499
500/*
Stefan Roese3befd852008-10-25 06:45:31 +0200501 * Arches doesn't use PerCS3 but GPIO43, so let's configure the GPIO
502 * pin multiplexing correctly
503 */
504#if defined(CONFIG_ARCHES)
505#define GPIO43_USE GPIO_SEL /* On Arches this pin is used as GPIO */
506#else
507#define GPIO43_USE GPIO_ALT1 /* On Glacier this pin is used as ALT1 -> PerCS3 */
508#endif
509
510/*
Stefan Roese6983fe22008-03-11 16:52:24 +0100511 * PPC4xx GPIO Configuration
512 */
Stefan Roese4c9e8552008-03-19 16:20:49 +0100513#ifdef CONFIG_460EX
514/* 460EX: Use USB configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200515#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
Stefan Roese6983fe22008-03-11 16:52:24 +0100516{ \
517/* GPIO Core 0 */ \
Stefan Roese41712b42008-03-05 12:31:53 +0100518{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
519{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
520{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
521{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
522{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
523{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
524{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
525{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
526{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
527{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
528{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
529{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
530{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
531{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
532{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
533{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
534{GPIO0_BASE, GPIO_IN , GPIO_SEL, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \
535{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \
536{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \
537{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \
538{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \
539{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \
Stefan Roese6983fe22008-03-11 16:52:24 +0100540{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \
541{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \
542{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \
543{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \
544{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \
545{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \
546{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \
547{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \
548{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \
549{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \
550}, \
551{ \
552/* GPIO Core 1 */ \
553{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \
554{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \
555{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
556{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
557{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \
558{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \
559{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
560{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
561{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \
562{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \
563{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \
564{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \
565{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \
566{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
567{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
568{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
569{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
570{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
571{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
572{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
573{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
574{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
575{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
576{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
577{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
578{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
579{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
580{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
581{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
582{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
583{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
584{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
585} \
586}
Stefan Roese4c9e8552008-03-19 16:20:49 +0100587#else
588/* 460GT: Use EMAC2+3 configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200589#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
Stefan Roese4c9e8552008-03-19 16:20:49 +0100590{ \
591/* GPIO Core 0 */ \
592{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
593{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
594{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
595{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
596{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
597{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
598{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
599{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
600{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
601{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
602{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
603{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
604{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
605{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
606{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
607{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
608{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \
609{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \
610{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \
611{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \
612{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \
613{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \
614{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \
615{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \
616{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \
617{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \
618{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \
619{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \
620{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \
621{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \
622{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \
623{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \
624}, \
625{ \
626/* GPIO Core 1 */ \
627{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \
628{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \
629{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
630{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
631{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \
632{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \
633{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
634{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
635{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \
636{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \
637{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \
Stefan Roese3befd852008-10-25 06:45:31 +0200638{GPIO1_BASE, GPIO_OUT, GPIO43_USE, GPIO_OUT_0},/* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \
Stefan Roese4c9e8552008-03-19 16:20:49 +0100639{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \
640{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
641{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
642{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
643{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
644{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
645{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
646{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
647{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
648{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
649{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
650{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
651{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
652{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
653{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
654{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
655{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
656{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
657{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
658{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
659} \
660}
661#endif
Stefan Roese6983fe22008-03-11 16:52:24 +0100662
Stefan Roese6983fe22008-03-11 16:52:24 +0100663#endif /* __CONFIG_H */