Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Kever Yang | 79c8306 | 2016-07-18 17:00:58 +0800 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2016 Fuzhou Rockchip Electronics Co., Ltd |
| 4 | * |
| 5 | * Rockchip SD Host Controller Interface |
Kever Yang | 79c8306 | 2016-07-18 17:00:58 +0800 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <common.h> |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 9 | #include <clk.h> |
Kever Yang | 79c8306 | 2016-07-18 17:00:58 +0800 | [diff] [blame] | 10 | #include <dm.h> |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 11 | #include <dm/ofnode.h> |
Kever Yang | c286821 | 2017-02-13 17:38:57 +0800 | [diff] [blame] | 12 | #include <dt-structs.h> |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 13 | #include <linux/delay.h> |
Simon Glass | 61b29b8 | 2020-02-03 07:36:15 -0700 | [diff] [blame] | 14 | #include <linux/err.h> |
Masahiro Yamada | b08c8c4 | 2018-03-05 01:20:11 +0900 | [diff] [blame] | 15 | #include <linux/libfdt.h> |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 16 | #include <linux/iopoll.h> |
Kever Yang | 79c8306 | 2016-07-18 17:00:58 +0800 | [diff] [blame] | 17 | #include <malloc.h> |
Kever Yang | c286821 | 2017-02-13 17:38:57 +0800 | [diff] [blame] | 18 | #include <mapmem.h> |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 19 | #include "mmc_private.h" |
Kever Yang | 79c8306 | 2016-07-18 17:00:58 +0800 | [diff] [blame] | 20 | #include <sdhci.h> |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 21 | #include <syscon.h> |
| 22 | #include <asm/arch-rockchip/clock.h> |
| 23 | #include <asm/arch-rockchip/hardware.h> |
Kever Yang | 79c8306 | 2016-07-18 17:00:58 +0800 | [diff] [blame] | 24 | |
Alper Nebi Yasak | c48021d | 2022-03-15 20:46:28 +0300 | [diff] [blame] | 25 | /* DWCMSHC specific Mode Select value */ |
| 26 | #define DWCMSHC_CTRL_HS400 0x7 |
Kever Yang | 79c8306 | 2016-07-18 17:00:58 +0800 | [diff] [blame] | 27 | /* 400KHz is max freq for card ID etc. Use that as min */ |
| 28 | #define EMMC_MIN_FREQ 400000 |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 29 | #define KHz (1000) |
| 30 | #define MHz (1000 * KHz) |
| 31 | #define SDHCI_TUNING_LOOP_COUNT 40 |
| 32 | |
| 33 | #define PHYCTRL_CALDONE_MASK 0x1 |
| 34 | #define PHYCTRL_CALDONE_SHIFT 0x6 |
| 35 | #define PHYCTRL_CALDONE_DONE 0x1 |
| 36 | #define PHYCTRL_DLLRDY_MASK 0x1 |
| 37 | #define PHYCTRL_DLLRDY_SHIFT 0x5 |
| 38 | #define PHYCTRL_DLLRDY_DONE 0x1 |
| 39 | #define PHYCTRL_FREQSEL_200M 0x0 |
| 40 | #define PHYCTRL_FREQSEL_50M 0x1 |
| 41 | #define PHYCTRL_FREQSEL_100M 0x2 |
| 42 | #define PHYCTRL_FREQSEL_150M 0x3 |
| 43 | #define PHYCTRL_DLL_LOCK_WO_TMOUT(x) \ |
| 44 | ((((x) >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK) ==\ |
| 45 | PHYCTRL_DLLRDY_DONE) |
Kever Yang | 79c8306 | 2016-07-18 17:00:58 +0800 | [diff] [blame] | 46 | |
Alper Nebi Yasak | c35af78 | 2022-03-15 20:46:27 +0300 | [diff] [blame] | 47 | #define ARASAN_VENDOR_REGISTER 0x78 |
| 48 | #define ARASAN_VENDOR_ENHANCED_STROBE BIT(0) |
| 49 | |
Alper Nebi Yasak | c48021d | 2022-03-15 20:46:28 +0300 | [diff] [blame] | 50 | /* DWC IP vendor area 1 pointer */ |
| 51 | #define DWCMSHC_P_VENDOR_AREA1 0xe8 |
| 52 | #define DWCMSHC_AREA1_MASK GENMASK(11, 0) |
| 53 | /* Offset inside the vendor area 1 */ |
| 54 | #define DWCMSHC_EMMC_CONTROL 0x2c |
| 55 | #define DWCMSHC_CARD_IS_EMMC BIT(0) |
| 56 | #define DWCMSHC_ENHANCED_STROBE BIT(8) |
| 57 | |
Yifeng Zhao | a63a57e | 2021-06-29 16:24:42 +0800 | [diff] [blame] | 58 | /* Rockchip specific Registers */ |
| 59 | #define DWCMSHC_EMMC_DLL_CTRL 0x800 |
| 60 | #define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1) |
| 61 | #define DWCMSHC_EMMC_DLL_RXCLK 0x804 |
| 62 | #define DWCMSHC_EMMC_DLL_TXCLK 0x808 |
| 63 | #define DWCMSHC_EMMC_DLL_STRBIN 0x80c |
Vasily Khoruzhick | 2321a99 | 2023-03-08 17:28:30 -0800 | [diff] [blame] | 64 | #define DECMSHC_EMMC_DLL_CMDOUT 0x810 |
Yifeng Zhao | a63a57e | 2021-06-29 16:24:42 +0800 | [diff] [blame] | 65 | #define DWCMSHC_EMMC_DLL_STATUS0 0x840 |
| 66 | #define DWCMSHC_EMMC_DLL_STATUS1 0x844 |
| 67 | #define DWCMSHC_EMMC_DLL_START BIT(0) |
| 68 | #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29 |
| 69 | #define DWCMSHC_EMMC_DLL_START_POINT 16 |
| 70 | #define DWCMSHC_EMMC_DLL_START_DEFAULT 5 |
| 71 | #define DWCMSHC_EMMC_DLL_INC_VALUE 2 |
| 72 | #define DWCMSHC_EMMC_DLL_INC 8 |
Vasily Khoruzhick | 2321a99 | 2023-03-08 17:28:30 -0800 | [diff] [blame] | 73 | #define DWCMSHC_EMMC_DLL_BYPASS BIT(24) |
Yifeng Zhao | a63a57e | 2021-06-29 16:24:42 +0800 | [diff] [blame] | 74 | #define DWCMSHC_EMMC_DLL_DLYENA BIT(27) |
Alper Nebi Yasak | c48021d | 2022-03-15 20:46:28 +0300 | [diff] [blame] | 75 | #define DLL_TXCLK_TAPNUM_DEFAULT 0xA |
| 76 | |
| 77 | #define DLL_STRBIN_TAPNUM_DEFAULT 0x8 |
| 78 | #define DLL_STRBIN_TAPNUM_FROM_SW BIT(24) |
| 79 | #define DLL_STRBIN_DELAY_NUM_SEL BIT(26) |
| 80 | #define DLL_STRBIN_DELAY_NUM_OFFSET 16 |
| 81 | #define DLL_STRBIN_DELAY_NUM_DEFAULT 0x16 |
| 82 | |
Yifeng Zhao | a63a57e | 2021-06-29 16:24:42 +0800 | [diff] [blame] | 83 | #define DLL_TXCLK_TAPNUM_FROM_SW BIT(24) |
| 84 | #define DWCMSHC_EMMC_DLL_LOCKED BIT(8) |
| 85 | #define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9) |
| 86 | #define DLL_RXCLK_NO_INVERTER 1 |
| 87 | #define DLL_RXCLK_INVERTER 0 |
Vasily Khoruzhick | 2321a99 | 2023-03-08 17:28:30 -0800 | [diff] [blame] | 88 | #define DLL_RXCLK_ORI_GATE BIT(31) |
Yifeng Zhao | a63a57e | 2021-06-29 16:24:42 +0800 | [diff] [blame] | 89 | #define DWCMSHC_ENHANCED_STROBE BIT(8) |
| 90 | #define DLL_LOCK_WO_TMOUT(x) \ |
| 91 | ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \ |
| 92 | (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0)) |
| 93 | #define ROCKCHIP_MAX_CLKS 3 |
| 94 | |
Kever Yang | 79c8306 | 2016-07-18 17:00:58 +0800 | [diff] [blame] | 95 | struct rockchip_sdhc_plat { |
| 96 | struct mmc_config cfg; |
| 97 | struct mmc mmc; |
| 98 | }; |
| 99 | |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 100 | struct rockchip_emmc_phy { |
| 101 | u32 emmcphy_con[7]; |
| 102 | u32 reserved; |
| 103 | u32 emmcphy_status; |
Kever Yang | 79c8306 | 2016-07-18 17:00:58 +0800 | [diff] [blame] | 104 | }; |
| 105 | |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 106 | struct rockchip_sdhc { |
| 107 | struct sdhci_host host; |
| 108 | struct udevice *dev; |
| 109 | void *base; |
| 110 | struct rockchip_emmc_phy *phy; |
| 111 | struct clk emmc_clk; |
| 112 | }; |
| 113 | |
| 114 | struct sdhci_data { |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 115 | int (*get_phy)(struct udevice *dev); |
Alper Nebi Yasak | ee5a284 | 2022-01-29 01:42:37 +0300 | [diff] [blame] | 116 | |
| 117 | /** |
| 118 | * set_control_reg() - Set SDHCI control registers |
| 119 | * |
| 120 | * This is the set_control_reg() SDHCI operation that should be |
| 121 | * used for the hardware this driver data is associated with. |
| 122 | * Normally, this is used to set up control registers for |
| 123 | * voltage level and UHS speed mode. |
| 124 | * |
| 125 | * @host: SDHCI host structure |
| 126 | */ |
| 127 | void (*set_control_reg)(struct sdhci_host *host); |
| 128 | |
| 129 | /** |
| 130 | * set_ios_post() - Host specific hook after set_ios() calls |
| 131 | * |
| 132 | * This is the set_ios_post() SDHCI operation that should be |
| 133 | * used for the hardware this driver data is associated with. |
| 134 | * Normally, this is a hook that is called after sdhci_set_ios() |
| 135 | * that does any necessary host-specific configuration. |
| 136 | * |
| 137 | * @host: SDHCI host structure |
| 138 | * Return: 0 if successful, -ve on error |
| 139 | */ |
| 140 | int (*set_ios_post)(struct sdhci_host *host); |
Alper Nebi Yasak | c35af78 | 2022-03-15 20:46:27 +0300 | [diff] [blame] | 141 | |
Jonas Karlman | 7e74522 | 2023-04-18 16:46:29 +0000 | [diff] [blame] | 142 | void (*set_clock)(struct sdhci_host *host, u32 div); |
| 143 | int (*config_dll)(struct sdhci_host *host, u32 clock, bool enable); |
| 144 | |
Alper Nebi Yasak | c35af78 | 2022-03-15 20:46:27 +0300 | [diff] [blame] | 145 | /** |
| 146 | * set_enhanced_strobe() - Set HS400 Enhanced Strobe config |
| 147 | * |
| 148 | * This is the set_enhanced_strobe() SDHCI operation that should |
| 149 | * be used for the hardware this driver data is associated with. |
| 150 | * Normally, this is used to set any host-specific configuration |
| 151 | * necessary for HS400 ES. |
| 152 | * |
| 153 | * @host: SDHCI host structure |
| 154 | * Return: 0 if successful, -ve on error |
| 155 | */ |
| 156 | int (*set_enhanced_strobe)(struct sdhci_host *host); |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 157 | }; |
| 158 | |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 159 | static void rk3399_emmc_phy_power_on(struct rockchip_emmc_phy *phy, u32 clock) |
| 160 | { |
| 161 | u32 caldone, dllrdy, freqsel; |
| 162 | |
| 163 | writel(RK_CLRSETBITS(7 << 4, 0), &phy->emmcphy_con[6]); |
| 164 | writel(RK_CLRSETBITS(1 << 11, 1 << 11), &phy->emmcphy_con[0]); |
| 165 | writel(RK_CLRSETBITS(0xf << 7, 6 << 7), &phy->emmcphy_con[0]); |
| 166 | |
| 167 | /* |
| 168 | * According to the user manual, calpad calibration |
| 169 | * cycle takes more than 2us without the minimal recommended |
| 170 | * value, so we may need a little margin here |
| 171 | */ |
| 172 | udelay(3); |
| 173 | writel(RK_CLRSETBITS(1, 1), &phy->emmcphy_con[6]); |
| 174 | |
| 175 | /* |
| 176 | * According to the user manual, it asks driver to |
| 177 | * wait 5us for calpad busy trimming. But it seems that |
| 178 | * 5us of caldone isn't enough for all cases. |
| 179 | */ |
| 180 | udelay(500); |
| 181 | caldone = readl(&phy->emmcphy_status); |
| 182 | caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK; |
| 183 | if (caldone != PHYCTRL_CALDONE_DONE) { |
| 184 | printf("%s: caldone timeout.\n", __func__); |
| 185 | return; |
| 186 | } |
| 187 | |
| 188 | /* Set the frequency of the DLL operation */ |
| 189 | if (clock < 75 * MHz) |
| 190 | freqsel = PHYCTRL_FREQSEL_50M; |
| 191 | else if (clock < 125 * MHz) |
| 192 | freqsel = PHYCTRL_FREQSEL_100M; |
| 193 | else if (clock < 175 * MHz) |
| 194 | freqsel = PHYCTRL_FREQSEL_150M; |
| 195 | else |
| 196 | freqsel = PHYCTRL_FREQSEL_200M; |
| 197 | |
| 198 | /* Set the frequency of the DLL operation */ |
| 199 | writel(RK_CLRSETBITS(3 << 12, freqsel << 12), &phy->emmcphy_con[0]); |
| 200 | writel(RK_CLRSETBITS(1 << 1, 1 << 1), &phy->emmcphy_con[6]); |
| 201 | |
Yifeng Zhao | 022f552 | 2021-10-15 16:41:27 +0800 | [diff] [blame] | 202 | /* REN Enable on STRB Line for HS400 */ |
| 203 | writel(RK_CLRSETBITS(0, 1 << 9), &phy->emmcphy_con[2]); |
| 204 | |
Ariel D'Alessandro | d7db0e6 | 2022-04-12 10:31:35 -0300 | [diff] [blame] | 205 | read_poll_timeout(readl, dllrdy, PHYCTRL_DLL_LOCK_WO_TMOUT(dllrdy), 1, |
| 206 | 5000, &phy->emmcphy_status); |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 207 | } |
| 208 | |
| 209 | static void rk3399_emmc_phy_power_off(struct rockchip_emmc_phy *phy) |
| 210 | { |
| 211 | writel(RK_CLRSETBITS(1, 0), &phy->emmcphy_con[6]); |
| 212 | writel(RK_CLRSETBITS(1 << 1, 0), &phy->emmcphy_con[6]); |
| 213 | } |
| 214 | |
| 215 | static int rk3399_emmc_get_phy(struct udevice *dev) |
| 216 | { |
| 217 | struct rockchip_sdhc *priv = dev_get_priv(dev); |
| 218 | ofnode phy_node; |
| 219 | void *grf_base; |
| 220 | u32 grf_phy_offset, phandle; |
| 221 | |
| 222 | phandle = dev_read_u32_default(dev, "phys", 0); |
| 223 | phy_node = ofnode_get_by_phandle(phandle); |
| 224 | if (!ofnode_valid(phy_node)) { |
| 225 | debug("Not found emmc phy device\n"); |
| 226 | return -ENODEV; |
| 227 | } |
| 228 | |
| 229 | grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); |
Haolin Li | fdda790 | 2022-03-22 05:58:02 -0700 | [diff] [blame] | 230 | if (IS_ERR_OR_NULL(grf_base)) { |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 231 | printf("%s Get syscon grf failed", __func__); |
| 232 | return -ENODEV; |
| 233 | } |
| 234 | grf_phy_offset = ofnode_read_u32_default(phy_node, "reg", 0); |
| 235 | |
| 236 | priv->phy = (struct rockchip_emmc_phy *)(grf_base + grf_phy_offset); |
| 237 | |
| 238 | return 0; |
| 239 | } |
| 240 | |
Alper Nebi Yasak | c35af78 | 2022-03-15 20:46:27 +0300 | [diff] [blame] | 241 | static int rk3399_sdhci_set_enhanced_strobe(struct sdhci_host *host) |
| 242 | { |
| 243 | struct mmc *mmc = host->mmc; |
| 244 | u32 vendor; |
| 245 | |
| 246 | vendor = sdhci_readl(host, ARASAN_VENDOR_REGISTER); |
| 247 | if (mmc->selected_mode == MMC_HS_400_ES) |
| 248 | vendor |= ARASAN_VENDOR_ENHANCED_STROBE; |
| 249 | else |
| 250 | vendor &= ~ARASAN_VENDOR_ENHANCED_STROBE; |
| 251 | sdhci_writel(host, vendor, ARASAN_VENDOR_REGISTER); |
| 252 | |
| 253 | return 0; |
| 254 | } |
| 255 | |
Alper Nebi Yasak | ee5a284 | 2022-01-29 01:42:37 +0300 | [diff] [blame] | 256 | static void rk3399_sdhci_set_control_reg(struct sdhci_host *host) |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 257 | { |
| 258 | struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); |
Alper Nebi Yasak | ee5a284 | 2022-01-29 01:42:37 +0300 | [diff] [blame] | 259 | struct mmc *mmc = host->mmc; |
| 260 | uint clock = mmc->tran_speed; |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 261 | int cycle_phy = host->clock != clock && clock > EMMC_MIN_FREQ; |
| 262 | |
| 263 | if (cycle_phy) |
| 264 | rk3399_emmc_phy_power_off(priv->phy); |
| 265 | |
Alper Nebi Yasak | ee5a284 | 2022-01-29 01:42:37 +0300 | [diff] [blame] | 266 | sdhci_set_control_reg(host); |
Alper Nebi Yasak | c35af78 | 2022-03-15 20:46:27 +0300 | [diff] [blame] | 267 | |
| 268 | /* |
| 269 | * Reinitializing the device tries to set it to lower-speed modes |
| 270 | * first, which fails if the Enhanced Strobe bit is set, making |
| 271 | * the device impossible to use. Set the correct value here to |
| 272 | * let reinitialization attempts succeed. |
| 273 | */ |
| 274 | if (CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)) |
| 275 | rk3399_sdhci_set_enhanced_strobe(host); |
Alper Nebi Yasak | ee5a284 | 2022-01-29 01:42:37 +0300 | [diff] [blame] | 276 | }; |
| 277 | |
| 278 | static int rk3399_sdhci_set_ios_post(struct sdhci_host *host) |
| 279 | { |
| 280 | struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); |
| 281 | struct mmc *mmc = host->mmc; |
| 282 | uint clock = mmc->tran_speed; |
| 283 | int cycle_phy = host->clock != clock && clock > EMMC_MIN_FREQ; |
| 284 | |
| 285 | if (!clock) |
| 286 | clock = mmc->clock; |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 287 | |
| 288 | if (cycle_phy) |
| 289 | rk3399_emmc_phy_power_on(priv->phy, clock); |
| 290 | |
| 291 | return 0; |
| 292 | } |
| 293 | |
Jonas Karlman | b8a63c8 | 2023-04-20 15:55:15 +0000 | [diff] [blame] | 294 | static void rk3568_sdhci_set_clock(struct sdhci_host *host, u32 div) |
Yifeng Zhao | a63a57e | 2021-06-29 16:24:42 +0800 | [diff] [blame] | 295 | { |
| 296 | struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); |
Jonas Karlman | b8a63c8 | 2023-04-20 15:55:15 +0000 | [diff] [blame] | 297 | struct mmc *mmc = host->mmc; |
| 298 | ulong rate; |
| 299 | |
| 300 | rate = clk_set_rate(&priv->emmc_clk, mmc->clock); |
| 301 | if (IS_ERR_VALUE(rate)) |
| 302 | printf("%s: Set clock rate failed: %ld\n", __func__, (long)rate); |
| 303 | } |
| 304 | |
| 305 | static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enable) |
| 306 | { |
Yifeng Zhao | a63a57e | 2021-06-29 16:24:42 +0800 | [diff] [blame] | 307 | int val, ret; |
| 308 | u32 extra; |
| 309 | |
Jonas Karlman | b8a63c8 | 2023-04-20 15:55:15 +0000 | [diff] [blame] | 310 | if (!enable) |
| 311 | return 0; |
Yifeng Zhao | a63a57e | 2021-06-29 16:24:42 +0800 | [diff] [blame] | 312 | |
| 313 | if (clock >= 100 * MHz) { |
| 314 | /* reset DLL */ |
| 315 | sdhci_writel(host, DWCMSHC_EMMC_DLL_CTRL_RESET, DWCMSHC_EMMC_DLL_CTRL); |
| 316 | udelay(1); |
| 317 | sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); |
| 318 | |
| 319 | /* Init DLL settings */ |
| 320 | extra = DWCMSHC_EMMC_DLL_START_DEFAULT << DWCMSHC_EMMC_DLL_START_POINT | |
| 321 | DWCMSHC_EMMC_DLL_INC_VALUE << DWCMSHC_EMMC_DLL_INC | |
| 322 | DWCMSHC_EMMC_DLL_START; |
| 323 | sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL); |
| 324 | |
Ariel D'Alessandro | d7db0e6 | 2022-04-12 10:31:35 -0300 | [diff] [blame] | 325 | ret = read_poll_timeout(readl, val, DLL_LOCK_WO_TMOUT(val), 1, |
| 326 | 500, |
| 327 | host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0); |
Yifeng Zhao | a63a57e | 2021-06-29 16:24:42 +0800 | [diff] [blame] | 328 | if (ret) |
| 329 | return ret; |
| 330 | |
| 331 | extra = DWCMSHC_EMMC_DLL_DLYENA | |
| 332 | DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; |
| 333 | sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); |
| 334 | |
| 335 | extra = DWCMSHC_EMMC_DLL_DLYENA | |
| 336 | DLL_TXCLK_TAPNUM_DEFAULT | |
| 337 | DLL_TXCLK_TAPNUM_FROM_SW; |
| 338 | sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK); |
| 339 | |
| 340 | extra = DWCMSHC_EMMC_DLL_DLYENA | |
Alper Nebi Yasak | c48021d | 2022-03-15 20:46:28 +0300 | [diff] [blame] | 341 | DLL_STRBIN_TAPNUM_DEFAULT | |
| 342 | DLL_STRBIN_TAPNUM_FROM_SW; |
Yifeng Zhao | a63a57e | 2021-06-29 16:24:42 +0800 | [diff] [blame] | 343 | sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); |
| 344 | } else { |
Vasily Khoruzhick | 2321a99 | 2023-03-08 17:28:30 -0800 | [diff] [blame] | 345 | /* |
| 346 | * Disable DLL and reset both of sample and drive clock. |
| 347 | * The bypass bit and start bit need to be set if DLL is not locked. |
| 348 | */ |
| 349 | sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, |
| 350 | DWCMSHC_EMMC_DLL_CTRL); |
| 351 | sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK); |
| 352 | sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT); |
Yifeng Zhao | a63a57e | 2021-06-29 16:24:42 +0800 | [diff] [blame] | 353 | sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); |
Alper Nebi Yasak | c48021d | 2022-03-15 20:46:28 +0300 | [diff] [blame] | 354 | /* |
| 355 | * Before switching to hs400es mode, the driver will enable |
| 356 | * enhanced strobe first. PHY needs to configure the parameters |
| 357 | * of enhanced strobe first. |
| 358 | */ |
| 359 | extra = DWCMSHC_EMMC_DLL_DLYENA | |
| 360 | DLL_STRBIN_DELAY_NUM_SEL | |
| 361 | DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET; |
| 362 | sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); |
Yifeng Zhao | a63a57e | 2021-06-29 16:24:42 +0800 | [diff] [blame] | 363 | } |
| 364 | |
| 365 | return 0; |
| 366 | } |
| 367 | |
| 368 | static int rk3568_emmc_get_phy(struct udevice *dev) |
| 369 | { |
| 370 | return 0; |
| 371 | } |
| 372 | |
Alper Nebi Yasak | c48021d | 2022-03-15 20:46:28 +0300 | [diff] [blame] | 373 | static int rk3568_sdhci_set_enhanced_strobe(struct sdhci_host *host) |
| 374 | { |
Alper Nebi Yasak | c48021d | 2022-03-15 20:46:28 +0300 | [diff] [blame] | 375 | return 0; |
| 376 | } |
| 377 | |
Alper Nebi Yasak | ee5a284 | 2022-01-29 01:42:37 +0300 | [diff] [blame] | 378 | static int rk3568_sdhci_set_ios_post(struct sdhci_host *host) |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 379 | { |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 380 | struct mmc *mmc = host->mmc; |
Alper Nebi Yasak | c48021d | 2022-03-15 20:46:28 +0300 | [diff] [blame] | 381 | u32 reg, vendor_reg; |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 382 | |
Jonas Karlman | 6de4438 | 2023-04-18 16:46:33 +0000 | [diff] [blame^] | 383 | reg = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 384 | reg &= ~SDHCI_CTRL_UHS_MASK; |
Alper Nebi Yasak | c48021d | 2022-03-15 20:46:28 +0300 | [diff] [blame] | 385 | |
Jonas Karlman | 6de4438 | 2023-04-18 16:46:33 +0000 | [diff] [blame^] | 386 | switch (mmc->selected_mode) { |
| 387 | case UHS_SDR25: |
| 388 | case MMC_HS: |
| 389 | case MMC_HS_52: |
| 390 | reg |= SDHCI_CTRL_UHS_SDR25; |
| 391 | break; |
| 392 | case UHS_SDR50: |
| 393 | reg |= SDHCI_CTRL_UHS_SDR50; |
| 394 | break; |
| 395 | case UHS_DDR50: |
| 396 | case MMC_DDR_52: |
| 397 | reg |= SDHCI_CTRL_UHS_DDR50; |
| 398 | break; |
| 399 | case UHS_SDR104: |
| 400 | case MMC_HS_200: |
| 401 | reg |= SDHCI_CTRL_UHS_SDR104; |
| 402 | break; |
| 403 | case MMC_HS_400: |
| 404 | case MMC_HS_400_ES: |
| 405 | reg |= DWCMSHC_CTRL_HS400; |
| 406 | break; |
| 407 | default: |
| 408 | reg |= SDHCI_CTRL_UHS_SDR12; |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 409 | } |
| 410 | |
Jonas Karlman | 6de4438 | 2023-04-18 16:46:33 +0000 | [diff] [blame^] | 411 | sdhci_writew(host, reg, SDHCI_HOST_CONTROL2); |
| 412 | |
| 413 | vendor_reg = (sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK) |
| 414 | + DWCMSHC_EMMC_CONTROL; |
| 415 | reg = sdhci_readw(host, vendor_reg); |
| 416 | |
| 417 | if (IS_MMC(mmc)) |
| 418 | reg |= DWCMSHC_CARD_IS_EMMC; |
| 419 | else |
| 420 | reg &= ~DWCMSHC_CARD_IS_EMMC; |
| 421 | |
| 422 | if (mmc->selected_mode == MMC_HS_400_ES) |
| 423 | reg |= DWCMSHC_ENHANCED_STROBE; |
| 424 | else |
| 425 | reg &= ~DWCMSHC_ENHANCED_STROBE; |
| 426 | |
| 427 | sdhci_writew(host, reg, vendor_reg); |
| 428 | |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 429 | return 0; |
| 430 | } |
| 431 | |
Alper Nebi Yasak | ee5a284 | 2022-01-29 01:42:37 +0300 | [diff] [blame] | 432 | static void rockchip_sdhci_set_control_reg(struct sdhci_host *host) |
| 433 | { |
| 434 | struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); |
| 435 | struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev); |
| 436 | |
| 437 | if (data->set_control_reg) |
| 438 | data->set_control_reg(host); |
| 439 | } |
| 440 | |
| 441 | static int rockchip_sdhci_set_ios_post(struct sdhci_host *host) |
| 442 | { |
| 443 | struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); |
| 444 | struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev); |
| 445 | |
| 446 | if (data->set_ios_post) |
| 447 | return data->set_ios_post(host); |
| 448 | |
| 449 | return 0; |
| 450 | } |
| 451 | |
Jonas Karlman | 7e74522 | 2023-04-18 16:46:29 +0000 | [diff] [blame] | 452 | static void rockchip_sdhci_set_clock(struct sdhci_host *host, u32 div) |
| 453 | { |
| 454 | struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); |
| 455 | struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev); |
| 456 | |
| 457 | if (data->set_clock) |
| 458 | data->set_clock(host, div); |
| 459 | } |
| 460 | |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 461 | static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) |
| 462 | { |
Jonas Karlman | b8c394b | 2023-04-18 16:46:26 +0000 | [diff] [blame] | 463 | struct rockchip_sdhc *priv = dev_get_priv(mmc->dev); |
| 464 | struct sdhci_host *host = &priv->host; |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 465 | char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT; |
| 466 | struct mmc_cmd cmd; |
| 467 | u32 ctrl, blk_size; |
Jonas Karlman | ba9f5e5 | 2023-04-18 16:46:31 +0000 | [diff] [blame] | 468 | int ret; |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 469 | |
| 470 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 471 | ctrl |= SDHCI_CTRL_EXEC_TUNING; |
| 472 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
| 473 | |
| 474 | sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 475 | |
| 476 | blk_size = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 64); |
Jonas Karlman | ba9f5e5 | 2023-04-18 16:46:31 +0000 | [diff] [blame] | 477 | if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200 && mmc->bus_width == 8) |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 478 | blk_size = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 128); |
| 479 | sdhci_writew(host, blk_size, SDHCI_BLOCK_SIZE); |
| 480 | sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); |
| 481 | |
| 482 | cmd.cmdidx = opcode; |
| 483 | cmd.resp_type = MMC_RSP_R1; |
| 484 | cmd.cmdarg = 0; |
| 485 | |
| 486 | do { |
Jonas Karlman | ba9f5e5 | 2023-04-18 16:46:31 +0000 | [diff] [blame] | 487 | ret = mmc_send_cmd(mmc, &cmd, NULL); |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 488 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
Jonas Karlman | ba9f5e5 | 2023-04-18 16:46:31 +0000 | [diff] [blame] | 489 | if (ret || tuning_loop_counter-- == 0) |
| 490 | break; |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 491 | } while (ctrl & SDHCI_CTRL_EXEC_TUNING); |
| 492 | |
Jonas Karlman | ba9f5e5 | 2023-04-18 16:46:31 +0000 | [diff] [blame] | 493 | if (ret || tuning_loop_counter < 0 || !(ctrl & SDHCI_CTRL_TUNED_CLK)) { |
| 494 | if (!ret) |
| 495 | ret = -EIO; |
| 496 | printf("%s: Tuning failed: %d\n", __func__, ret); |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 497 | |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 498 | ctrl &= ~SDHCI_CTRL_TUNED_CLK; |
Jonas Karlman | ba9f5e5 | 2023-04-18 16:46:31 +0000 | [diff] [blame] | 499 | ctrl &= ~SDHCI_CTRL_EXEC_TUNING; |
| 500 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 501 | } |
| 502 | |
| 503 | /* Enable only interrupts served by the SD controller */ |
| 504 | sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, SDHCI_INT_ENABLE); |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 505 | |
| 506 | return ret; |
| 507 | } |
| 508 | |
Jonas Karlman | 7e74522 | 2023-04-18 16:46:29 +0000 | [diff] [blame] | 509 | static int rockchip_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enable) |
| 510 | { |
| 511 | struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); |
| 512 | struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev); |
| 513 | |
| 514 | if (data->config_dll) |
| 515 | return data->config_dll(host, clock, enable); |
| 516 | |
| 517 | return 0; |
| 518 | } |
| 519 | |
Alper Nebi Yasak | c35af78 | 2022-03-15 20:46:27 +0300 | [diff] [blame] | 520 | static int rockchip_sdhci_set_enhanced_strobe(struct sdhci_host *host) |
| 521 | { |
| 522 | struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); |
| 523 | struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev); |
| 524 | |
| 525 | if (data->set_enhanced_strobe) |
| 526 | return data->set_enhanced_strobe(host); |
| 527 | |
| 528 | return -ENOTSUPP; |
| 529 | } |
| 530 | |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 531 | static struct sdhci_ops rockchip_sdhci_ops = { |
Alper Nebi Yasak | ee5a284 | 2022-01-29 01:42:37 +0300 | [diff] [blame] | 532 | .set_control_reg = rockchip_sdhci_set_control_reg, |
Jonas Karlman | 7e74522 | 2023-04-18 16:46:29 +0000 | [diff] [blame] | 533 | .set_ios_post = rockchip_sdhci_set_ios_post, |
| 534 | .set_clock = rockchip_sdhci_set_clock, |
| 535 | .platform_execute_tuning = rockchip_sdhci_execute_tuning, |
| 536 | .config_dll = rockchip_sdhci_config_dll, |
Alper Nebi Yasak | c35af78 | 2022-03-15 20:46:27 +0300 | [diff] [blame] | 537 | .set_enhanced_strobe = rockchip_sdhci_set_enhanced_strobe, |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 538 | }; |
| 539 | |
| 540 | static int rockchip_sdhci_probe(struct udevice *dev) |
| 541 | { |
| 542 | struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(dev); |
Kever Yang | 79c8306 | 2016-07-18 17:00:58 +0800 | [diff] [blame] | 543 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); |
Simon Glass | c69cda2 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 544 | struct rockchip_sdhc_plat *plat = dev_get_plat(dev); |
Jonas Karlman | b8c394b | 2023-04-18 16:46:26 +0000 | [diff] [blame] | 545 | struct rockchip_sdhc *priv = dev_get_priv(dev); |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 546 | struct mmc_config *cfg = &plat->cfg; |
Jonas Karlman | b8c394b | 2023-04-18 16:46:26 +0000 | [diff] [blame] | 547 | struct sdhci_host *host = &priv->host; |
Kever Yang | 39fbb56 | 2016-12-28 11:32:35 +0800 | [diff] [blame] | 548 | struct clk clk; |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 549 | int ret; |
Kever Yang | 39fbb56 | 2016-12-28 11:32:35 +0800 | [diff] [blame] | 550 | |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 551 | host->max_clk = cfg->f_max; |
Kever Yang | 39fbb56 | 2016-12-28 11:32:35 +0800 | [diff] [blame] | 552 | ret = clk_get_by_index(dev, 0, &clk); |
| 553 | if (!ret) { |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 554 | ret = clk_set_rate(&clk, host->max_clk); |
Kever Yang | 39fbb56 | 2016-12-28 11:32:35 +0800 | [diff] [blame] | 555 | if (IS_ERR_VALUE(ret)) |
| 556 | printf("%s clk set rate fail!\n", __func__); |
| 557 | } else { |
| 558 | printf("%s fail to get clk\n", __func__); |
| 559 | } |
Kever Yang | 79c8306 | 2016-07-18 17:00:58 +0800 | [diff] [blame] | 560 | |
Jonas Karlman | b8c394b | 2023-04-18 16:46:26 +0000 | [diff] [blame] | 561 | priv->emmc_clk = clk; |
| 562 | priv->dev = dev; |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 563 | |
| 564 | if (data->get_phy) { |
| 565 | ret = data->get_phy(dev); |
| 566 | if (ret) |
| 567 | return ret; |
| 568 | } |
| 569 | |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 570 | host->ops = &rockchip_sdhci_ops; |
Kever Yang | 79c8306 | 2016-07-18 17:00:58 +0800 | [diff] [blame] | 571 | host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD; |
| 572 | |
Kever Yang | 79c8306 | 2016-07-18 17:00:58 +0800 | [diff] [blame] | 573 | host->mmc = &plat->mmc; |
Jonas Karlman | b8c394b | 2023-04-18 16:46:26 +0000 | [diff] [blame] | 574 | host->mmc->priv = &priv->host; |
Kever Yang | 79c8306 | 2016-07-18 17:00:58 +0800 | [diff] [blame] | 575 | host->mmc->dev = dev; |
| 576 | upriv->mmc = host->mmc; |
| 577 | |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 578 | ret = sdhci_setup_cfg(cfg, host, cfg->f_max, EMMC_MIN_FREQ); |
Kever Yang | 4dcdc5c | 2019-07-19 18:01:11 +0800 | [diff] [blame] | 579 | if (ret) |
| 580 | return ret; |
| 581 | |
Kever Yang | 79c8306 | 2016-07-18 17:00:58 +0800 | [diff] [blame] | 582 | return sdhci_probe(dev); |
| 583 | } |
| 584 | |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 585 | static int rockchip_sdhci_of_to_plat(struct udevice *dev) |
Kever Yang | 79c8306 | 2016-07-18 17:00:58 +0800 | [diff] [blame] | 586 | { |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 587 | struct rockchip_sdhc_plat *plat = dev_get_plat(dev); |
Jonas Karlman | b8c394b | 2023-04-18 16:46:26 +0000 | [diff] [blame] | 588 | struct rockchip_sdhc *priv = dev_get_priv(dev); |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 589 | struct mmc_config *cfg = &plat->cfg; |
Jonas Karlman | b8c394b | 2023-04-18 16:46:26 +0000 | [diff] [blame] | 590 | struct sdhci_host *host = &priv->host; |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 591 | int ret; |
Kever Yang | 79c8306 | 2016-07-18 17:00:58 +0800 | [diff] [blame] | 592 | |
| 593 | host->name = dev->name; |
Philipp Tomsich | 327b2b3 | 2017-09-11 22:04:21 +0200 | [diff] [blame] | 594 | host->ioaddr = dev_read_addr_ptr(dev); |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 595 | |
| 596 | ret = mmc_of_parse(dev, cfg); |
| 597 | if (ret) |
| 598 | return ret; |
Kever Yang | 79c8306 | 2016-07-18 17:00:58 +0800 | [diff] [blame] | 599 | |
| 600 | return 0; |
| 601 | } |
| 602 | |
| 603 | static int rockchip_sdhci_bind(struct udevice *dev) |
| 604 | { |
Simon Glass | c69cda2 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 605 | struct rockchip_sdhc_plat *plat = dev_get_plat(dev); |
Kever Yang | 79c8306 | 2016-07-18 17:00:58 +0800 | [diff] [blame] | 606 | |
Masahiro Yamada | 24f5aec | 2016-09-06 22:17:32 +0900 | [diff] [blame] | 607 | return sdhci_bind(dev, &plat->mmc, &plat->cfg); |
Kever Yang | 79c8306 | 2016-07-18 17:00:58 +0800 | [diff] [blame] | 608 | } |
| 609 | |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 610 | static const struct sdhci_data rk3399_data = { |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 611 | .get_phy = rk3399_emmc_get_phy, |
Alper Nebi Yasak | ee5a284 | 2022-01-29 01:42:37 +0300 | [diff] [blame] | 612 | .set_control_reg = rk3399_sdhci_set_control_reg, |
| 613 | .set_ios_post = rk3399_sdhci_set_ios_post, |
Alper Nebi Yasak | c35af78 | 2022-03-15 20:46:27 +0300 | [diff] [blame] | 614 | .set_enhanced_strobe = rk3399_sdhci_set_enhanced_strobe, |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 615 | }; |
| 616 | |
Yifeng Zhao | a63a57e | 2021-06-29 16:24:42 +0800 | [diff] [blame] | 617 | static const struct sdhci_data rk3568_data = { |
Yifeng Zhao | a63a57e | 2021-06-29 16:24:42 +0800 | [diff] [blame] | 618 | .get_phy = rk3568_emmc_get_phy, |
Alper Nebi Yasak | ee5a284 | 2022-01-29 01:42:37 +0300 | [diff] [blame] | 619 | .set_ios_post = rk3568_sdhci_set_ios_post, |
Jonas Karlman | b8a63c8 | 2023-04-20 15:55:15 +0000 | [diff] [blame] | 620 | .set_clock = rk3568_sdhci_set_clock, |
| 621 | .config_dll = rk3568_sdhci_config_dll, |
Alper Nebi Yasak | c48021d | 2022-03-15 20:46:28 +0300 | [diff] [blame] | 622 | .set_enhanced_strobe = rk3568_sdhci_set_enhanced_strobe, |
Yifeng Zhao | a63a57e | 2021-06-29 16:24:42 +0800 | [diff] [blame] | 623 | }; |
| 624 | |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 625 | static const struct udevice_id sdhci_ids[] = { |
| 626 | { |
| 627 | .compatible = "arasan,sdhci-5.1", |
| 628 | .data = (ulong)&rk3399_data, |
| 629 | }, |
Yifeng Zhao | a63a57e | 2021-06-29 16:24:42 +0800 | [diff] [blame] | 630 | { |
| 631 | .compatible = "rockchip,rk3568-dwcmshc", |
| 632 | .data = (ulong)&rk3568_data, |
| 633 | }, |
Kever Yang | 79c8306 | 2016-07-18 17:00:58 +0800 | [diff] [blame] | 634 | { } |
| 635 | }; |
| 636 | |
| 637 | U_BOOT_DRIVER(arasan_sdhci_drv) = { |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 638 | .name = "rockchip_sdhci_5_1", |
Kever Yang | 79c8306 | 2016-07-18 17:00:58 +0800 | [diff] [blame] | 639 | .id = UCLASS_MMC, |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 640 | .of_match = sdhci_ids, |
| 641 | .of_to_plat = rockchip_sdhci_of_to_plat, |
Kever Yang | 79c8306 | 2016-07-18 17:00:58 +0800 | [diff] [blame] | 642 | .ops = &sdhci_ops, |
| 643 | .bind = rockchip_sdhci_bind, |
Yifeng Zhao | ac80414 | 2021-06-29 16:24:41 +0800 | [diff] [blame] | 644 | .probe = rockchip_sdhci_probe, |
Simon Glass | 41575d8 | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 645 | .priv_auto = sizeof(struct rockchip_sdhc), |
Simon Glass | caa4daa | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 646 | .plat_auto = sizeof(struct rockchip_sdhc_plat), |
Kever Yang | 79c8306 | 2016-07-18 17:00:58 +0800 | [diff] [blame] | 647 | }; |