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Kumar Gala86902b82006-01-12 19:51:38 -06001/*
2 * See file CREDITS for list of people who contributed to this
3 * project.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 *
20 */
21
22#include <asm/mmu.h>
23#include <common.h>
24#include <asm/global_data.h>
25#include <pci.h>
26#include <asm/mpc8349_pci.h>
27#include <i2c.h>
28
Wolfgang Denkd87080b2006-03-31 18:32:53 +020029DECLARE_GLOBAL_DATA_PTR;
30
Kumar Gala86902b82006-01-12 19:51:38 -060031#ifdef CONFIG_PCI
32
33/* System RAM mapped to PCI space */
34#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
35#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
36
37#ifndef CONFIG_PCI_PNP
Kumar Gala8fe9bf62006-04-20 13:45:32 -050038static struct pci_config_table pci_mpc8349emds_config_table[] = {
Kumar Gala86902b82006-01-12 19:51:38 -060039 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
40 PCI_IDSEL_NUMBER, PCI_ANY_ID,
41 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
42 PCI_ENET0_MEMADDR,
43 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
44 }
45 },
46 {}
47};
48#endif
49
50static struct pci_controller pci_hose[] = {
51 {
52#ifndef CONFIG_PCI_PNP
Kumar Gala8fe9bf62006-04-20 13:45:32 -050053 config_table:pci_mpc8349emds_config_table,
Kumar Gala86902b82006-01-12 19:51:38 -060054#endif
55 },
56 {
57#ifndef CONFIG_PCI_PNP
Kumar Gala8fe9bf62006-04-20 13:45:32 -050058 config_table:pci_mpc8349emds_config_table,
Kumar Gala86902b82006-01-12 19:51:38 -060059#endif
60 }
61};
62
63/**************************************************************************
64 *
65 * pib_init() -- initialize the PCA9555PW IO expander on the PIB board
66 *
67 */
68void
69pib_init(void)
70{
Ben Warren183da6d2006-09-12 10:15:53 -040071 u8 val8, orig_i2c_bus;
Kumar Gala86902b82006-01-12 19:51:38 -060072 /*
73 * Assign PIB PMC slot to desired PCI bus
74 */
Ben Warren183da6d2006-09-12 10:15:53 -040075 /* Switch temporarily to I2C bus #2 */
76 orig_i2c_bus = i2c_get_bus_num();
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010077 i2c_set_bus_num(1);
Kumar Gala86902b82006-01-12 19:51:38 -060078
79 val8 = 0;
80 i2c_write(0x23, 0x6, 1, &val8, 1);
81 i2c_write(0x23, 0x7, 1, &val8, 1);
82 val8 = 0xff;
83 i2c_write(0x23, 0x2, 1, &val8, 1);
84 i2c_write(0x23, 0x3, 1, &val8, 1);
85
86 val8 = 0;
87 i2c_write(0x26, 0x6, 1, &val8, 1);
88 val8 = 0x34;
89 i2c_write(0x26, 0x7, 1, &val8, 1);
90#if defined(PCI_64BIT)
91 val8 = 0xf4; /* PMC2:PCI1/64-bit */
92#elif defined(PCI_ALL_PCI1)
93 val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */
94#elif defined(PCI_ONE_PCI1)
95 val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */
96#else
97 val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */
98#endif
99 i2c_write(0x26, 0x2, 1, &val8, 1);
100 val8 = 0xff;
101 i2c_write(0x26, 0x3, 1, &val8, 1);
102 val8 = 0;
103 i2c_write(0x27, 0x6, 1, &val8, 1);
104 i2c_write(0x27, 0x7, 1, &val8, 1);
105 val8 = 0xff;
106 i2c_write(0x27, 0x2, 1, &val8, 1);
107 val8 = 0xef;
108 i2c_write(0x27, 0x3, 1, &val8, 1);
109 asm("eieio");
110
111#if defined(PCI_64BIT)
112 printf("PCI1: 64-bit on PMC2\n");
113#elif defined(PCI_ALL_PCI1)
114 printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n");
115#elif defined(PCI_ONE_PCI1)
116 printf("PCI1: 32-bit on PMC1\n");
117 printf("PCI2: 32-bit on PMC2, PMC3\n");
118#else
119 printf("PCI1: 32-bit on PMC1, PMC2\n");
120 printf("PCI2: 32-bit on PMC3\n");
121#endif
Ben Warren183da6d2006-09-12 10:15:53 -0400122 /* Reset to original I2C bus */
Timur Tabibe5e6182006-11-03 19:15:00 -0600123 i2c_set_bus_num(orig_i2c_bus);
Kumar Gala86902b82006-01-12 19:51:38 -0600124}
125
126/**************************************************************************
127 * pci_init_board()
128 *
129 * NOTICE: PCI2 is not currently supported
130 *
131 */
132void
133pci_init_board(void)
134{
Kumar Gala86902b82006-01-12 19:51:38 -0600135 volatile immap_t * immr;
Timur Tabi2ad6b512006-10-31 18:44:42 -0600136 volatile clk83xx_t * clk;
137 volatile law83xx_t * pci_law;
138 volatile pot83xx_t * pci_pot;
139 volatile pcictrl83xx_t * pci_ctrl;
140 volatile pciconf83xx_t * pci_conf;
Kumar Gala86902b82006-01-12 19:51:38 -0600141 u16 reg16;
142 u32 reg32;
143 u32 dev;
144 struct pci_controller * hose;
145
Timur Tabid239d742006-11-03 12:00:28 -0600146 immr = (immap_t *)CFG_IMMR;
Timur Tabi2ad6b512006-10-31 18:44:42 -0600147 clk = (clk83xx_t *)&immr->clk;
Kumar Gala86902b82006-01-12 19:51:38 -0600148 pci_law = immr->sysconf.pcilaw;
149 pci_pot = immr->ios.pot;
150 pci_ctrl = immr->pci_ctrl;
151 pci_conf = immr->pci_conf;
152
153 hose = &pci_hose[0];
154
155 pib_init();
156
157 /*
158 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
159 */
160
161 reg32 = clk->occr;
162 udelay(2000);
163 clk->occr = 0xff000000;
164 udelay(2000);
165
166 /*
167 * Release PCI RST Output signal
168 */
169 pci_ctrl[0].gcr = 0;
170 udelay(2000);
171 pci_ctrl[0].gcr = 1;
172
173#ifdef CONFIG_MPC83XX_PCI2
174 pci_ctrl[1].gcr = 0;
175 udelay(2000);
176 pci_ctrl[1].gcr = 1;
177#endif
178
179 /* We need to wait at least a 1sec based on PCI specs */
180 {
181 int i;
182
183 for (i = 0; i < 1000; ++i)
184 udelay (1000);
185 }
186
187 /*
188 * Configure PCI Local Access Windows
189 */
190 pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
191 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
192
193 pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500194 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
Kumar Gala86902b82006-01-12 19:51:38 -0600195
196 /*
197 * Configure PCI Outbound Translation Windows
198 */
199
200 /* PCI1 mem space - prefetch */
201 pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
202 pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
203 pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
204
205 /* PCI1 IO space */
206 pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
207 pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
208 pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
209
210 /* PCI1 mmio - non-prefetch mem space */
211 pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
212 pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
213 pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
214
215 /*
216 * Configure PCI Inbound Translation Windows
217 */
218
219 /* we need RAM mapped to PCI space for the devices to
220 * access main memory */
221 pci_ctrl[0].pitar1 = 0x0;
222 pci_ctrl[0].pibar1 = 0x0;
223 pci_ctrl[0].piebar1 = 0x0;
224 pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
225
226 hose->first_busno = 0;
227 hose->last_busno = 0xff;
228
229 /* PCI memory prefetch space */
230 pci_set_region(hose->regions + 0,
231 CFG_PCI1_MEM_BASE,
232 CFG_PCI1_MEM_PHYS,
233 CFG_PCI1_MEM_SIZE,
234 PCI_REGION_MEM|PCI_REGION_PREFETCH);
235
236 /* PCI memory space */
237 pci_set_region(hose->regions + 1,
238 CFG_PCI1_MMIO_BASE,
239 CFG_PCI1_MMIO_PHYS,
240 CFG_PCI1_MMIO_SIZE,
241 PCI_REGION_MEM);
242
243 /* PCI IO space */
244 pci_set_region(hose->regions + 2,
245 CFG_PCI1_IO_BASE,
246 CFG_PCI1_IO_PHYS,
247 CFG_PCI1_IO_SIZE,
248 PCI_REGION_IO);
249
250 /* System memory space */
251 pci_set_region(hose->regions + 3,
252 CONFIG_PCI_SYS_MEM_BUS,
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100253 CONFIG_PCI_SYS_MEM_PHYS,
254 gd->ram_size,
255 PCI_REGION_MEM | PCI_REGION_MEMORY);
Kumar Gala86902b82006-01-12 19:51:38 -0600256
257 hose->region_count = 4;
258
259 pci_setup_indirect(hose,
Timur Tabid239d742006-11-03 12:00:28 -0600260 (CFG_IMMR+0x8300),
261 (CFG_IMMR+0x8304));
Kumar Gala86902b82006-01-12 19:51:38 -0600262
263 pci_register_hose(hose);
264
265 /*
266 * Write to Command register
267 */
268 reg16 = 0xff;
269 dev = PCI_BDF(hose->first_busno, 0, 0);
270 pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
271 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
272 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
273
274 /*
275 * Clear non-reserved bits in status register.
276 */
277 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
278 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
279 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
280
281#ifdef CONFIG_PCI_SCAN_SHOW
282 printf("PCI: Bus Dev VenId DevId Class Int\n");
283#endif
284 /*
285 * Hose scan.
286 */
287 hose->last_busno = pci_hose_scan(hose);
288
289#ifdef CONFIG_MPC83XX_PCI2
290 hose = &pci_hose[1];
291
292 /*
293 * Configure PCI Outbound Translation Windows
294 */
295
296 /* PCI2 mem space - prefetch */
297 pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
298 pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
299 pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
300
301 /* PCI2 IO space */
302 pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
303 pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
304 pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
305
306 /* PCI2 mmio - non-prefetch mem space */
307 pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
308 pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
309 pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK);
310
311 /*
312 * Configure PCI Inbound Translation Windows
313 */
314
315 /* we need RAM mapped to PCI space for the devices to
316 * access main memory */
317 pci_ctrl[1].pitar1 = 0x0;
318 pci_ctrl[1].pibar1 = 0x0;
319 pci_ctrl[1].piebar1 = 0x0;
320 pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
321
322 hose->first_busno = pci_hose[0].last_busno + 1;
323 hose->last_busno = 0xff;
324
325 /* PCI memory prefetch space */
326 pci_set_region(hose->regions + 0,
327 CFG_PCI2_MEM_BASE,
328 CFG_PCI2_MEM_PHYS,
329 CFG_PCI2_MEM_SIZE,
330 PCI_REGION_MEM|PCI_REGION_PREFETCH);
331
332 /* PCI memory space */
333 pci_set_region(hose->regions + 1,
334 CFG_PCI2_MMIO_BASE,
335 CFG_PCI2_MMIO_PHYS,
336 CFG_PCI2_MMIO_SIZE,
337 PCI_REGION_MEM);
338
339 /* PCI IO space */
340 pci_set_region(hose->regions + 2,
341 CFG_PCI2_IO_BASE,
342 CFG_PCI2_IO_PHYS,
343 CFG_PCI2_IO_SIZE,
344 PCI_REGION_IO);
345
346 /* System memory space */
347 pci_set_region(hose->regions + 3,
348 CONFIG_PCI_SYS_MEM_BUS,
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100349 CONFIG_PCI_SYS_MEM_PHYS,
350 gd->ram_size,
351 PCI_REGION_MEM | PCI_REGION_MEMORY);
Kumar Gala86902b82006-01-12 19:51:38 -0600352
353 hose->region_count = 4;
354
355 pci_setup_indirect(hose,
Timur Tabid239d742006-11-03 12:00:28 -0600356 (CFG_IMMR+0x8380),
357 (CFG_IMMR+0x8384));
Kumar Gala86902b82006-01-12 19:51:38 -0600358
359 pci_register_hose(hose);
360
361 /*
362 * Write to Command register
363 */
364 reg16 = 0xff;
365 dev = PCI_BDF(hose->first_busno, 0, 0);
366 pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
367 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
368 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
369
370 /*
371 * Clear non-reserved bits in status register.
372 */
373 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
374 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
375 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
376
377 /*
378 * Hose scan.
379 */
380 hose->last_busno = pci_hose_scan(hose);
381#endif
382
383}
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500384
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600385#ifdef CONFIG_OF_FLAT_TREE
386void
387ft_pci_setup(void *blob, bd_t *bd)
388{
389 u32 *p;
390 int len;
391
392 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
393 if (p != NULL) {
394 p[0] = pci_hose[0].first_busno;
395 p[1] = pci_hose[0].last_busno;
396 }
397
398#ifdef CONFIG_MPC83XX_PCI2
399 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len);
400 if (p != NULL) {
401 p[0] = pci_hose[1].first_busno;
402 p[1] = pci_hose[1].last_busno;
403 }
404#endif
405}
406#endif /* CONFIG_OF_FLAT_TREE */
Kumar Gala86902b82006-01-12 19:51:38 -0600407#endif /* CONFIG_PCI */