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wdenkf5c5ef42005-04-05 16:26:47 +00001/*
Stefan Roesed96f41e2005-11-30 13:06:40 +01002 * (C) Copyright 2005
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
wdenkf5c5ef42005-04-05 16:26:47 +00005 * Copyright 2004 Freescale Semiconductor.
6 * (C) Copyright 2002,2003, Motorola Inc.
7 * Xianghua Xiao, (X.Xiao@motorola.com)
8 *
9 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
wdenkf5c5ef42005-04-05 16:26:47 +000030#include <common.h>
31#include <pci.h>
32#include <asm/processor.h>
33#include <asm/immap_85xx.h>
34#include <ioports.h>
35#include <spd.h>
Stefan Roesed96f41e2005-11-30 13:06:40 +010036#include <flash.h>
wdenkf5c5ef42005-04-05 16:26:47 +000037
Wolfgang Denkd87080b2006-03-31 18:32:53 +020038DECLARE_GLOBAL_DATA_PTR;
39
Stefan Roesed96f41e2005-11-30 13:06:40 +010040extern flash_info_t flash_info[]; /* FLASH chips info */
wdenkf5c5ef42005-04-05 16:26:47 +000041
42void local_bus_init (void);
43long int fixed_sdram (void);
Stefan Roesef18e8742006-03-01 17:00:49 +010044ulong flash_get_size (ulong base, int banknum);
Wolfgang Denk966083e2006-07-21 15:24:56 +020045
Wolfgang Denkbd3143f2006-07-19 14:49:35 +020046#ifdef CONFIG_PS2MULT
47void ps2mult_early_init(void);
48#endif
wdenkf5c5ef42005-04-05 16:26:47 +000049
Stefan Roesed96f41e2005-11-30 13:06:40 +010050#ifdef CONFIG_CPM2
wdenkf5c5ef42005-04-05 16:26:47 +000051/*
52 * I/O Port configuration table
53 *
54 * if conf is 1, then that port pin will be configured at boot time
55 * according to the five values podr/pdir/ppar/psor/pdat for that entry
56 */
57
58const iop_conf_t iop_conf_tab[4][32] = {
59
60 /* Port A configuration */
61 { /* conf ppar psor pdir podr pdat */
Stefan Roesed96f41e2005-11-30 13:06:40 +010062 /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
63 /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
64 /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
65 /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
66 /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
67 /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
wdenkf5c5ef42005-04-05 16:26:47 +000068 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
69 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
70 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
71 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
Stefan Roesed96f41e2005-11-30 13:06:40 +010072 /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
73 /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
74 /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
75 /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
76 /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
77 /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
78 /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
79 /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
wdenkf5c5ef42005-04-05 16:26:47 +000080 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
81 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
82 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
83 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
84 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
85 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
86 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
87 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
88 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
89 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
90 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
91 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
92 /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* FREERUN */
93 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
94 },
95
96 /* Port B configuration */
97 { /* conf ppar psor pdir podr pdat */
Stefan Roesed96f41e2005-11-30 13:06:40 +010098 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
99 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
100 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
101 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
102 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
103 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
104 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
105 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
106 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
107 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
108 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
109 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
110 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
111 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
wdenkf5c5ef42005-04-05 16:26:47 +0000112 /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
113 /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
114 /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
115 /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
116 /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:COL */
117 /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
118 /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
119 /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
120 /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
121 /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
122 /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
123 /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
124 /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
125 /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
126 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
127 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
128 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
129 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
130 },
131
132 /* Port C */
133 { /* conf ppar psor pdir podr pdat */
134 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
135 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
136 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
137 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
138 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
139 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
140 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
141 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
142 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
143 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100144 /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
145 /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
146 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
wdenkf5c5ef42005-04-05 16:26:47 +0000147 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
148 /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* PC17 */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100149 /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
wdenkf5c5ef42005-04-05 16:26:47 +0000150 /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
151 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
152 /* PC13 */ { 0, 1, 0, 0, 0, 0 }, /* PC13 */
153 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
154 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
155 /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */
156 /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */
157 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
158 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
159 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
160 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
161 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
162 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
163 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
164 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
165 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
166 },
167
168 /* Port D */
169 { /* conf ppar psor pdir podr pdat */
170 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
171 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
172 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
173 /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* PD28 */
174 /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* PD27 */
175 /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* PD26 */
176 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
177 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
178 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
179 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
180 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
181 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
182 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
183 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
184 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
185 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
186 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
187 /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
188 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
189 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
190 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
191 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
192 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
193 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
194 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
195 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
196 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
197 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
198 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
199 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
200 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
201 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
202 }
203};
Stefan Roesed96f41e2005-11-30 13:06:40 +0100204#endif /* CONFIG_CPM2 */
wdenkf5c5ef42005-04-05 16:26:47 +0000205
Stefan Roesed96f41e2005-11-30 13:06:40 +0100206#define CASL_STRING1 "casl=xx"
207#define CASL_STRING2 "casl="
wdenkf5c5ef42005-04-05 16:26:47 +0000208
Stefan Roesed96f41e2005-11-30 13:06:40 +0100209static const int casl_table[] = { 20, 25, 30 };
210#define N_CASL (sizeof(casl_table) / sizeof(casl_table[0]))
211
212int cas_latency(void)
wdenkf5c5ef42005-04-05 16:26:47 +0000213{
Stefan Roesed96f41e2005-11-30 13:06:40 +0100214 char *s = getenv("serial#");
215 int casl;
216 int val;
217 int i;
218
219 casl = CONFIG_DDR_DEFAULT_CL;
220
221 if (s != NULL) {
222 if (strncmp(s + strlen(s) - strlen(CASL_STRING1), CASL_STRING2,
223 strlen(CASL_STRING2)) == 0) {
224 val = simple_strtoul(s + strlen(s) - 2, NULL, 10);
225
226 for (i=0; i<N_CASL; ++i) {
227 if (val == casl_table[i]) {
228 return val;
229 }
230 }
231 }
232 }
233
234 return casl;
wdenkf5c5ef42005-04-05 16:26:47 +0000235}
236
237int checkboard (void)
238{
Stefan Roesed96f41e2005-11-30 13:06:40 +0100239 char *s = getenv("serial#");
240
241 printf("Board: %s", CONFIG_BOARDNAME);
242 if (s != NULL) {
243 puts(", serial# ");
244 puts(s);
245 }
246 putc('\n');
wdenkf5c5ef42005-04-05 16:26:47 +0000247
248#ifdef CONFIG_PCI
249 printf ("PCI1: 32 bit, %d MHz (compiled)\n",
250 CONFIG_SYS_CLK_FREQ / 1000000);
251#else
252 printf ("PCI1: disabled\n");
253#endif
Stefan Roesed96f41e2005-11-30 13:06:40 +0100254
wdenkf5c5ef42005-04-05 16:26:47 +0000255 /*
256 * Initialize local bus.
257 */
258 local_bus_init ();
259
260 return 0;
261}
262
Stefan Roesed96f41e2005-11-30 13:06:40 +0100263int misc_init_r (void)
wdenkf5c5ef42005-04-05 16:26:47 +0000264{
Stefan Roesed96f41e2005-11-30 13:06:40 +0100265 volatile immap_t *immap = (immap_t *)CFG_IMMR;
266 volatile ccsr_lbc_t *memctl = &immap->im_lbc;
wdenkf5c5ef42005-04-05 16:26:47 +0000267
Stefan Roesed96f41e2005-11-30 13:06:40 +0100268 /*
269 * Adjust flash start and offset to detected values
270 */
271 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
272 gd->bd->bi_flashoffset = 0;
Stefan Roese9d2a8732005-08-31 12:55:50 +0200273
Stefan Roesed96f41e2005-11-30 13:06:40 +0100274 /*
275 * Check if boot FLASH isn't max size
276 */
277 if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) {
278 memctl->or0 = gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff);
279 memctl->br0 = gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff);
wdenkf5c5ef42005-04-05 16:26:47 +0000280
281 /*
Stefan Roesed96f41e2005-11-30 13:06:40 +0100282 * Re-check to get correct base address
wdenkf5c5ef42005-04-05 16:26:47 +0000283 */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100284 flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
wdenkf5c5ef42005-04-05 16:26:47 +0000285 }
wdenkf5c5ef42005-04-05 16:26:47 +0000286
wdenkf5c5ef42005-04-05 16:26:47 +0000287 /*
Stefan Roesed96f41e2005-11-30 13:06:40 +0100288 * Check if only one FLASH bank is available
wdenkf5c5ef42005-04-05 16:26:47 +0000289 */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100290 if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) {
291 memctl->or1 = 0;
292 memctl->br1 = 0;
wdenkf5c5ef42005-04-05 16:26:47 +0000293
Stefan Roesed96f41e2005-11-30 13:06:40 +0100294 /*
295 * Re-do flash protection upon new addresses
296 */
297 flash_protect (FLAG_PROTECT_CLEAR,
298 gd->bd->bi_flashstart, 0xffffffff,
299 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
300
301 /* Monitor protection ON by default */
302 flash_protect (FLAG_PROTECT_SET,
Stefan Roese79b4cda2006-02-28 15:29:58 +0100303 CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
Stefan Roesed96f41e2005-11-30 13:06:40 +0100304 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
305
306 /* Environment protection ON by default */
307 flash_protect (FLAG_PROTECT_SET,
308 CFG_ENV_ADDR,
309 CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
310 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
311
312 /* Redundant environment protection ON by default */
313 flash_protect (FLAG_PROTECT_SET,
314 CFG_ENV_ADDR_REDUND,
315 CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
316 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
317 }
318
319 return 0;
wdenkf5c5ef42005-04-05 16:26:47 +0000320}
321
wdenkf5c5ef42005-04-05 16:26:47 +0000322/*
323 * Initialize Local Bus
324 */
wdenkf5c5ef42005-04-05 16:26:47 +0000325void local_bus_init (void)
326{
327 volatile immap_t *immap = (immap_t *) CFG_IMMR;
328 volatile ccsr_gur_t *gur = &immap->im_gur;
329 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
330
331 uint clkdiv;
332 uint lbc_hz;
333 sys_info_t sysinfo;
334
335 /*
336 * Errata LBC11.
337 * Fix Local Bus clock glitch when DLL is enabled.
338 *
339 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
340 * If localbus freq is > 133Mhz, DLL can be safely enabled.
341 * Between 66 and 133, the DLL is enabled with an override workaround.
342 */
343
344 get_sys_info (&sysinfo);
345 clkdiv = lbc->lcrr & 0x0f;
346 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
347
348 if (lbc_hz < 66) {
349 lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
350 lbc->ltedr = 0xa4c80000; /* DK: !!! */
351
352 } else if (lbc_hz >= 133) {
353 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
354
355 } else {
356 /*
357 * On REV1 boards, need to change CLKDIV before enable DLL.
358 * Default CLKDIV is 8, change it to 4 temporarily.
359 */
360 uint pvr = get_pvr ();
361 uint temp_lbcdll = 0;
362
363 if (pvr == PVR_85xx_REV1) {
364 /* FIXME: Justify the high bit here. */
365 lbc->lcrr = 0x10000004;
366 }
367
368 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
369 udelay (200);
370
371 /*
372 * Sample LBC DLL ctrl reg, upshift it to set the
373 * override bits.
374 */
375 temp_lbcdll = gur->lbcdllcr;
376 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
377 asm ("sync;isync;msync");
378 }
379}
380
wdenkf5c5ef42005-04-05 16:26:47 +0000381#if defined(CONFIG_PCI)
382/*
383 * Initialize PCI Devices, report devices found.
384 */
385
386#ifndef CONFIG_PCI_PNP
387static struct pci_config_table pci_mpc85xxads_config_table[] = {
388 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
389 PCI_IDSEL_NUMBER, PCI_ANY_ID,
390 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
391 PCI_ENET0_MEMADDR,
392 PCI_COMMAND_MEMORY |
393 PCI_COMMAND_MASTER}},
394 {}
395};
396#endif
397
398
399static struct pci_controller hose = {
400#ifndef CONFIG_PCI_PNP
401 config_table:pci_mpc85xxads_config_table,
402#endif
403};
404
405#endif /* CONFIG_PCI */
406
407
408void pci_init_board (void)
409{
410#ifdef CONFIG_PCI
wdenkf5c5ef42005-04-05 16:26:47 +0000411 pci_mpc85xx_init (&hose);
412#endif /* CONFIG_PCI */
413}
Wolfgang Denkbc8bb6d2006-06-16 16:40:54 +0200414
415#ifdef CONFIG_BOARD_EARLY_INIT_R
416int board_early_init_r (void)
417{
418#ifdef CONFIG_PS2MULT
419 ps2mult_early_init();
420#endif /* CONFIG_PS2MULT */
421 return (0);
422}
423#endif /* CONFIG_BOARD_EARLY_INIT_R */