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wdenk80885a92004-02-26 23:46:20 +00001/***********************************************************************
2 *
3 * Copyright (C) 2004 by FS Forth-Systeme GmbH.
4 * All rights reserved.
5 *
6 * $Id: ns9750_sys.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
7 * @Author: Markus Pietrek
8 * @Descr: Definitions for SYS Control Module
9 * @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 4
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 *
26 ***********************************************************************/
27
28#ifndef FS_NS9750_SYS_H
29#define FS_NS9750_SYS_H
30
31#define NS9750_SYS_MODULE_BASE (0xA0900000)
32
33#define get_sys_reg_addr(c) \
34 ((volatile unsigned int *)(NS9750_SYS_MODULE_BASE+(unsigned int) (c)))
35
36/* the register addresses */
37
38#define NS9750_SYS_AHB_GEN (0x0000)
39#define NS9750_SYS_BRC_BASE (0x0004)
40#define NS9750_SYS_AHB_TIMEOUT (0x0014)
Wolfgang Denk53677ef2008-05-20 16:00:29 +020041#define NS9750_SYS_AHB_ERROR1 (0x0018)
42#define NS9750_SYS_AHB_ERROR2 (0x001C)
43#define NS9750_SYS_AHB_MON (0x0020)
wdenk80885a92004-02-26 23:46:20 +000044#define NS9750_SYS_TIMER_COUNT_BASE (0x0044)
45#define NS9750_SYS_TIMER_READ_BASE (0x0084)
46#define NS9750_SYS_INT_VEC_ADR_BASE (0x00C4)
47#define NS9750_SYS_INT_CFG_BASE (0x0144)
48#define NS9750_SYS_ISRADDR (0x0164)
49#define NS9750_SYS_INT_STAT_ACTIVE (0x0168)
50#define NS9750_SYS_INT_STAT_RAW (0x016C)
51#define NS9750_SYS_TIMER_INT_STAT (0x0170)
52#define NS9750_SYS_SW_WDOG_CFG (0x0174)
53#define NS9750_SYS_SW_WDOG_TIMER (0x0178)
54#define NS9750_SYS_CLOCK (0x017C)
55#define NS9750_SYS_RESET (0x0180)
56#define NS9750_SYS_MISC (0x0184)
57#define NS9750_SYS_PLL (0x0188)
58#define NS9750_SYS_ACT_INT_STAT (0x018C)
59#define NS9750_SYS_TIMER_CTRL_BASE (0x0190)
60#define NS9750_SYS_CS_DYN_BASE_BASE (0x01D0)
61#define NS9750_SYS_CS_DYN_MASK_BASE (0x01D4)
62#define NS9750_SYS_CS_STATIC_BASE_BASE (0x01F0)
63#define NS9750_SYS_CS_STATIC_MASK_BASE (0x01F4)
64#define NS9750_SYS_GEN_ID (0x0210)
65#define NS9750_SYS_EXT_INT_CTRL_BASE (0x0214)
66
67/* the vectored register addresses */
68
69#define NS9750_SYS_TIMER_COUNT(c) (NS9750_SYS_TIMER_COUNT_BASE + (c))
70#define NS9750_SYS_TIMER_READ(c) (NS9750_SYS_TIMER_READ_BASE + (c))
71#define NS9750_SYS_INT_VEC_ADR(c) (NS9750_SYS_INT_VEC_ADR_BASE + (c))
72#define NS9750_SYS_TIMER_CTRL(c) (NS9750_SYS_TIMER_CTRL_BASE + (c))
73/* CS_DYN start with 4 */
74#define NS9750_SYS_CS_DYN_BASE(c) (NS9750_SYS_CS_DYN_BASE_BASE + ((c)-4)*2)
75#define NS9750_SYS_CS_DYN_MASK(c) (NS9750_SYS_CS_DYN_MASK_BASE + ((c)-4)*2)
76/* CS_STATIC start with 0 */
77#define NS9750_SYS_CS_STATIC_BASE(c) (NS9750_SYS_CS_STATIC_BASE_BASE + (c)*2)
78#define NS9750_SYS_CS_STATIC_MASK(c) (NS9750_SYS_CS_STATIC_MASK_BASE + (c)*2)
79#define NS9750_SYS_EXT_INT_CTRL(c) (NS9750_SYS_EXT_INT_CTRL + (c))
80
81/* register bit fields */
82
83#define NS9750_SYS_AHB_GEN_EXMAM (0x00000001)
84
85/* need to be n*8bit to BRC channel */
86#define NS9750_SYS_BRC_CEB (0x00000080)
87#define NS9750_SYS_BRC_BRF_MA (0x00000030)
88#define NS9750_SYS_BRC_BRF_100 (0x00000000)
89#define NS9750_SYS_BRC_BRF_75 (0x00000010)
90#define NS9750_SYS_BRC_BRF_50 (0x00000020)
91#define NS9750_SYS_BRC_BRF_25 (0x00000030)
92
93#define NS9750_SYS_AHB_TIMEOUT_BAT_MA (0xFFFF0000)
94#define NS9750_SYS_AHB_TIMEOUT_BMT_MA (0x0000FFFF)
95
96#define NS9750_SYS_AHB_ERROR2_ABL (0x00040000)
97#define NS9750_SYS_AHB_ERROR2_AER (0x00020000)
98#define NS9750_SYS_AHB_ERROR2_ABM (0x00010000)
99#define NS9750_SYS_AHB_ERROR2_ABA (0x00008000)
100#define NS9750_SYS_AHB_ERROR2_HWRT (0x00004000)
101#define NS9750_SYS_AHB_ERROR2_HMID_MA (0x00003C00)
102#define NS9750_SYS_AHB_ERROR2_HTPC_MA (0x000003C0)
103#define NS9750_SYS_AHB_ERROR2_HSZ_MA (0x00000038)
104#define NS9750_SYS_AHB_ERROR2_RR_MA (0x00000007)
105
106#define NS9750_SYS_AHB_MON_EIC (0x00800000)
107#define NS9750_SYS_AHB_MON_MBII (0x00400000)
108#define NS9750_SYS_AHB_MON_MBL_MA (0x003FFFC0)
109#define NS9750_SYS_AHB_MON_MBLDC (0x00000020)
110#define NS9750_SYS_AHB_MON_SERDC (0x00000010)
111#define NS9750_SYS_AHB_MON_BMTC_MA (0x0000000C)
112#define NS9750_SYS_AHB_MON_BMTC_RECORD (0x00000000)
113#define NS9750_SYS_AHB_MON_BMTC_GEN_IRQ (0x00000004)
114#define NS9750_SYS_AHB_MON_BMTC_GEN_RES (0x00000008)
115#define NS9750_SYS_AHB_MON_BATC_MA (0x00000003)
116#define NS9750_SYS_AHB_MON_BATC_RECORD (0x00000000)
117#define NS9750_SYS_AHB_MON_BATC_GEN_IRQ (0x00000001)
118#define NS9750_SYS_AHB_MON_BATC_GEN_RES (0x00000002)
119
120/* need to be n*8bit to Int Level */
121
122#define NS9750_SYS_INT_CFG_IE (0x00000080)
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200123#define NS9750_SYS_INT_CFG_IT (0x00000020)
wdenk80885a92004-02-26 23:46:20 +0000124#define NS9750_SYS_INT_CFG_IAD_MA (0x0000001F)
125
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200126#define NS9750_SYS_TIMER_INT_STAT_MA (0x0000FFFF)
wdenk80885a92004-02-26 23:46:20 +0000127
128#define NS9750_SYS_SW_WDOG_CFG_SWWE (0x00000080)
129#define NS9750_SYS_SW_WDOG_CFG_SWWI (0x00000020)
130#define NS9750_SYS_SW_WDOG_CFG_SWWIC (0x00000010)
131#define NS9750_SYS_SW_WDOG_CFG_SWTCS_MA (0x00000007)
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200132#define NS9750_SYS_SW_WDOG_CFG_SWTCS_2 (0x00000000)
133#define NS9750_SYS_SW_WDOG_CFG_SWTCS_4 (0x00000001)
134#define NS9750_SYS_SW_WDOG_CFG_SWTCS_8 (0x00000002)
wdenk80885a92004-02-26 23:46:20 +0000135#define NS9750_SYS_SW_WDOG_CFG_SWTCS_16 (0x00000003)
136#define NS9750_SYS_SW_WDOG_CFG_SWTCS_32 (0x00000004)
137#define NS9750_SYS_SW_WDOG_CFG_SWTCS_64 (0x00000005)
138
139#define NS9750_SYS_CLOCK_LPCS_MA (0x00000380)
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200140#define NS9750_SYS_CLOCK_LPCS_1 (0x00000000)
141#define NS9750_SYS_CLOCK_LPCS_2 (0x00000080)
142#define NS9750_SYS_CLOCK_LPCS_4 (0x00000100)
143#define NS9750_SYS_CLOCK_LPCS_8 (0x00000180)
wdenk80885a92004-02-26 23:46:20 +0000144#define NS9750_SYS_CLOCK_LPCS_EXT (0x00000200)
145#define NS9750_SYS_CLOCK_BBC (0x00000040)
146#define NS9750_SYS_CLOCK_LCC (0x00000020)
147#define NS9750_SYS_CLOCK_MCC (0x00000010)
148#define NS9750_SYS_CLOCK_PARBC (0x00000008)
149#define NS9750_SYS_CLOCK_PC (0x00000004)
150#define NS9750_SYS_CLOCK_MACC (0x00000001)
151
152#define NS9750_SYS_RESET_SR (0x80000000)
153#define NS9750_SYS_RESET_I2CW (0x00100000)
154#define NS9750_SYS_RESET_CSE (0x00080000)
155#define NS9750_SYS_RESET_SMWE (0x00040000)
156#define NS9750_SYS_RESET_EWE (0x00020000)
157#define NS9750_SYS_RESET_PI3WE (0x00010000)
158#define NS9750_SYS_RESET_BBT (0x00000040)
159#define NS9750_SYS_RESET_LCDC (0x00000020)
160#define NS9750_SYS_RESET_MEMC (0x00000010)
161#define NS9750_SYS_RESET_PCIAR (0x00000008)
162#define NS9750_SYS_RESET_PCIM (0x00000004)
163#define NS9750_SYS_RESET_MACM (0x00000001)
164
165#define NS9750_SYS_MISC_REV_MA (0xFF000000)
166#define NS9750_SYS_MISC_PCIA (0x00002000)
167#define NS9750_SYS_MISC_VDIS (0x00001000)
168#define NS9750_SYS_MISC_BMM (0x00000800)
169#define NS9750_SYS_MISC_CS1DB (0x00000400)
170#define NS9750_SYS_MISC_CS1DW_MA (0x00000300)
171#define NS9750_SYS_MISC_MCCM (0x00000080)
172#define NS9750_SYS_MISC_PMSS (0x00000040)
173#define NS9750_SYS_MISC_CS1P (0x00000020)
174#define NS9750_SYS_MISC_ENDM (0x00000008)
175#define NS9750_SYS_MISC_MBAR (0x00000004)
176#define NS9750_SYS_MISC_IRAM0 (0x00000001)
177
178#define NS9750_SYS_PLL_PLLBS (0x02000000)
179#define NS9750_SYS_PLL_PLLFS_MA (0x01800000)
180#define NS9750_SYS_PLL_PLLIS_MA (0x00600000)
181#define NS9750_SYS_PLL_PLLND_MA (0x001F0000)
182#define NS9750_SYS_PLL_PLLSW (0x00008000)
183#define NS9750_SYS_PLL_PLLBSSW (0x00000200)
184#define NS9750_SYS_PLL_FSEL_MA (0x00000180)
185#define NS9750_SYS_PLL_CPCC_MA (0x00000060)
186#define NS9750_SYS_PLL_NDSW_MA (0x0000001F)
187
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200188#define NS9750_SYS_ACT_INT_STAT_MA (0x0000FFFF)
wdenk80885a92004-02-26 23:46:20 +0000189
190#define NS9750_SYS_TIMER_CTRL_TEN (0x00008000)
191#define NS9750_SYS_TIMER_CTRL_INTC (0x00000200)
192#define NS9750_SYS_TIMER_CTRL_TLCS_MA (0x000001C0)
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200193#define NS9750_SYS_TIMER_CTRL_TLCS_1 (0x00000000)
194#define NS9750_SYS_TIMER_CTRL_TLCS_2 (0x00000040)
195#define NS9750_SYS_TIMER_CTRL_TLCS_4 (0x00000080)
196#define NS9750_SYS_TIMER_CTRL_TLCS_8 (0x000000C0)
wdenk80885a92004-02-26 23:46:20 +0000197#define NS9750_SYS_TIMER_CTRL_TLCS_16 (0x00000100)
198#define NS9750_SYS_TIMER_CTRL_TLCS_32 (0x00000140)
199#define NS9750_SYS_TIMER_CTRL_TLCS_64 (0x00000180)
200#define NS9750_SYS_TIMER_CTRL_TLCS_EXT (0x000001C0)
201#define NS9750_SYS_TIMER_CTRL_TM_MA (0x00000030)
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200202#define NS9750_SYS_TIMER_CTRL_TM_INT (0x00000000)
203#define NS9750_SYS_TIMER_CTRL_TM_LOW (0x00000010)
wdenk80885a92004-02-26 23:46:20 +0000204#define NS9750_SYS_TIMER_CTRL_TM_HIGH (0x00000020)
205#define NS9750_SYS_TIMER_CTRL_INTS (0x00000008)
206#define NS9750_SYS_TIMER_CTRL_UDS (0x00000004)
207#define NS9750_SYS_TIMER_CTRL_TSZ (0x00000002)
208#define NS9750_SYS_TIMER_CTRL_REN (0x00000001)
209
210#define NS9750_SYS_EXT_INT_CTRL_STS (0x00000008)
211#define NS9750_SYS_EXT_INT_CTRL_CLR (0x00000004)
212#define NS9750_SYS_EXT_INT_CTRL_PLTY (0x00000002)
213#define NS9750_SYS_EXT_INT_CTRL_LVEDG (0x00000001)
214
215#endif /* FS_NS9750_SYS_H */