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Fabio Estevam7dd65452012-09-24 08:09:33 +00001/*
2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20#include <common.h>
21#include <asm/io.h>
22#include <asm/arch/clock.h>
23#include <asm/arch/imx-regs.h>
24#include <asm/arch/iomux.h>
25#include <asm/arch/mx6x_pins.h>
26#include <asm/errno.h>
27#include <asm/gpio.h>
28#include <asm/imx-common/iomux-v3.h>
29#include <mmc.h>
30#include <fsl_esdhc.h>
Fabio Estevamfe5ebe92012-09-25 08:43:57 +000031#include <miiphy.h>
32#include <netdev.h>
Fabio Estevamdce67bd2012-10-02 11:20:12 +000033#include <asm/arch/sys_proto.h>
34
Fabio Estevam7dd65452012-09-24 08:09:33 +000035DECLARE_GLOBAL_DATA_PTR;
36
37#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
38 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
39 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
40
41#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
42 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
43 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
44
Fabio Estevamfe5ebe92012-09-25 08:43:57 +000045#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
46 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
47 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
48
Fabio Estevam7dd65452012-09-24 08:09:33 +000049int dram_init(void)
50{
51 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
52
53 return 0;
54}
55
Eric Nelson6e142322012-10-03 07:26:38 +000056iomux_v3_cfg_t const uart4_pads[] = {
Fabio Estevam7dd65452012-09-24 08:09:33 +000057 MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
58 MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
59};
60
Eric Nelson6e142322012-10-03 07:26:38 +000061iomux_v3_cfg_t const enet_pads[] = {
Fabio Estevamfe5ebe92012-09-25 08:43:57 +000062 MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
63 MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
64 MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
65 MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
66 MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
67 MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
68 MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
69 MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
70 MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
71 MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
72 MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
73 MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
74 MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
75 MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
76 MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
77};
78
79static void setup_iomux_enet(void)
80{
81 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
82}
83
Eric Nelson6e142322012-10-03 07:26:38 +000084iomux_v3_cfg_t const usdhc3_pads[] = {
Fabio Estevam7dd65452012-09-24 08:09:33 +000085 MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
86 MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
87 MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
88 MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
89 MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
90 MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
91 MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
92 MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
93 MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
94 MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
95 MX6Q_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
96 MX6Q_PAD_NANDF_CS2__GPIO_6_15 | MUX_PAD_CTRL(NO_PAD_CTRL),
97};
98
99static void setup_iomux_uart(void)
100{
101 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
102}
103
104#ifdef CONFIG_FSL_ESDHC
105struct fsl_esdhc_cfg usdhc_cfg[1] = {
106 {USDHC3_BASE_ADDR},
107};
108
109int board_mmc_getcd(struct mmc *mmc)
110{
111 gpio_direction_input(IMX_GPIO_NR(6, 15));
112 return !gpio_get_value(IMX_GPIO_NR(6, 15));
113}
114
115int board_mmc_init(bd_t *bis)
116{
117 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
118
Benoît Thébaudeaua2ac1b32012-10-01 08:36:25 +0000119 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
Fabio Estevam7dd65452012-09-24 08:09:33 +0000120 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
121}
122#endif
123
Fabio Estevamfe5ebe92012-09-25 08:43:57 +0000124int mx6_rgmii_rework(struct phy_device *phydev)
125{
126 unsigned short val;
127
128 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
129 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
130 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
131 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
132
133 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
134 val &= 0xffe3;
135 val |= 0x18;
136 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
137
138 /* introduce tx clock delay */
139 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
140 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
141 val |= 0x0100;
142 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
143
144 return 0;
145}
146
147int board_phy_config(struct phy_device *phydev)
148{
149 mx6_rgmii_rework(phydev);
150
151 if (phydev->drv->config)
152 phydev->drv->config(phydev);
153
154 return 0;
155}
156
157int board_eth_init(bd_t *bis)
158{
159 int ret;
160
161 setup_iomux_enet();
162
163 ret = cpu_eth_init(bis);
164 if (ret)
165 printf("FEC MXC: %s:failed\n", __func__);
166
167 return 0;
168}
169
Fabio Estevamdce67bd2012-10-02 11:20:12 +0000170#define BOARD_REV_B 0x200
171#define BOARD_REV_A 0x100
172
173static int mx6sabre_rev(void)
174{
175 /*
176 * Get Board ID information from OCOTP_GP1[15:8]
177 * i.MX6Q ARD RevA: 0x01
178 * i.MX6Q ARD RevB: 0x02
179 */
180 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
181 int reg = readl(&ocotp->gp1);
182 int ret;
183
184 switch (reg >> 8 & 0x0F) {
185 case 0x02:
186 ret = BOARD_REV_B;
187 break;
188 case 0x01:
189 default:
190 ret = BOARD_REV_A;
191 break;
192 }
193
194 return ret;
195}
196
Fabio Estevam7dd65452012-09-24 08:09:33 +0000197u32 get_board_rev(void)
198{
Fabio Estevamdce67bd2012-10-02 11:20:12 +0000199 int rev = mx6sabre_rev();
200
201 return (get_cpu_rev() & ~(0xF << 8)) | rev;
Fabio Estevam7dd65452012-09-24 08:09:33 +0000202}
203
204int board_early_init_f(void)
205{
206 setup_iomux_uart();
207
208 return 0;
209}
210
211int board_init(void)
212{
213 /* address of boot parameters */
214 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
215
216 return 0;
217}
218
219int checkboard(void)
220{
Fabio Estevamdce67bd2012-10-02 11:20:12 +0000221 int rev = mx6sabre_rev();
222 char *revname;
223
224 switch (rev) {
225 case BOARD_REV_B:
226 revname = "B";
227 break;
228 case BOARD_REV_A:
229 default:
230 revname = "A";
231 break;
232 }
233
234 printf("Board: MX6Q-Sabreauto rev%s\n", revname);
Fabio Estevam7dd65452012-09-24 08:09:33 +0000235
236 return 0;
237}