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Chunhe Lan0b2e13d2014-04-14 18:42:06 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/*
8 * T4240 RDB board configuration file
9 */
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080013#define CONFIG_FSL_SATA_V2
14#define CONFIG_PCIE4
15
16#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
17
18#ifdef CONFIG_RAMBOOT_PBL
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080019#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
Chunhe Lan373762c2015-03-20 17:08:54 +080020#ifndef CONFIG_SDCARD
21#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
22#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
23#else
Chunhe Lan373762c2015-03-20 17:08:54 +080024#define CONFIG_SPL_FLUSH_IMAGE
25#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Chunhe Lan373762c2015-03-20 17:08:54 +080026#define CONFIG_SYS_TEXT_BASE 0x00201000
27#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
28#define CONFIG_SPL_PAD_TO 0x40000
29#define CONFIG_SPL_MAX_SIZE 0x28000
30#define RESET_VECTOR_OFFSET 0x27FFC
31#define BOOT_PAGE_OFFSET 0x27000
32
33#ifdef CONFIG_SDCARD
34#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
Chunhe Lan373762c2015-03-20 17:08:54 +080035#define CONFIG_SPL_MMC_MINIMAL
36#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
37#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
38#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
39#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
40#ifndef CONFIG_SPL_BUILD
41#define CONFIG_SYS_MPC85XX_NO_RESETVEC
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080042#endif
Chunhe Lan373762c2015-03-20 17:08:54 +080043#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
Zhao Qiangec90ac72016-09-08 12:55:32 +080044#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
Chunhe Lan373762c2015-03-20 17:08:54 +080045#define CONFIG_SPL_MMC_BOOT
46#endif
47
48#ifdef CONFIG_SPL_BUILD
49#define CONFIG_SPL_SKIP_RELOCATE
50#define CONFIG_SPL_COMMON_INIT_DDR
51#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
Chunhe Lan373762c2015-03-20 17:08:54 +080052#endif
53
54#endif
55#endif /* CONFIG_RAMBOOT_PBL */
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080056
57#define CONFIG_DDR_ECC
58
59#define CONFIG_CMD_REGINFO
60
61/* High Level Configuration Options */
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080062#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
63#define CONFIG_MP /* support multiple processors */
64
65#ifndef CONFIG_SYS_TEXT_BASE
66#define CONFIG_SYS_TEXT_BASE 0xeff40000
67#endif
68
69#ifndef CONFIG_RESET_VECTOR_ADDRESS
70#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
71#endif
72
73#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
York Sun51370d52016-12-28 08:43:45 -080074#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -040075#define CONFIG_PCIE1 /* PCIE controller 1 */
76#define CONFIG_PCIE2 /* PCIE controller 2 */
77#define CONFIG_PCIE3 /* PCIE controller 3 */
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080078#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
79#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
80
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080081#define CONFIG_ENV_OVERWRITE
82
83/*
84 * These can be toggled for performance analysis, otherwise use default.
85 */
86#define CONFIG_SYS_CACHE_STASHING
87#define CONFIG_BTB /* toggle branch predition */
88#ifdef CONFIG_DDR_ECC
89#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
90#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
91#endif
92
93#define CONFIG_ENABLE_36BIT_PHYS
94
95#define CONFIG_ADDR_MAP
96#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
97
98#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
99#define CONFIG_SYS_MEMTEST_END 0x00400000
100#define CONFIG_SYS_ALT_MEMTEST
101#define CONFIG_PANIC_HANG /* do not reset board on panic */
102
103/*
104 * Config the L3 Cache as L3 SRAM
105 */
Chunhe Lan373762c2015-03-20 17:08:54 +0800106#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
107#define CONFIG_SYS_L3_SIZE (512 << 10)
108#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
109#ifdef CONFIG_RAMBOOT_PBL
110#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
111#endif
112#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
113#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
114#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
115#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800116
117#define CONFIG_SYS_DCSRBAR 0xf0000000
118#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
119
120/*
121 * DDR Setup
122 */
123#define CONFIG_VERY_BIG_RAM
124#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
125#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
126
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800127#define CONFIG_DIMM_SLOTS_PER_CTLR 1
128#define CONFIG_CHIP_SELECTS_PER_CTRL 4
129#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
130
131#define CONFIG_DDR_SPD
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800132
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800133/*
134 * IFC Definitions
135 */
136#define CONFIG_SYS_FLASH_BASE 0xe0000000
137#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
138
Chunhe Lan373762c2015-03-20 17:08:54 +0800139#ifdef CONFIG_SPL_BUILD
140#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
141#else
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800142#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Chunhe Lan373762c2015-03-20 17:08:54 +0800143#endif
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800144
145#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
146#define CONFIG_MISC_INIT_R
147
148#define CONFIG_HWCONFIG
149
150/* define to use L1 as initial stack */
151#define CONFIG_L1_INIT_RAM
152#define CONFIG_SYS_INIT_RAM_LOCK
153#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
154#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
York Sunb3142e22015-08-17 13:31:51 -0700155#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800156/* The assembler doesn't like typecast */
157#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
158 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
159 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
160#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
161
162#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
163 GENERATED_GBL_DATA_SIZE)
164#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
165
Chunhe Lan373762c2015-03-20 17:08:54 +0800166#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800167#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
168
169/* Serial Port - controlled on board with jumper J8
170 * open - index 2
171 * shorted - index 1
172 */
173#define CONFIG_CONS_INDEX 1
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800174#define CONFIG_SYS_NS16550_SERIAL
175#define CONFIG_SYS_NS16550_REG_SIZE 1
176#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
177
178#define CONFIG_SYS_BAUDRATE_TABLE \
179 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
180
181#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
182#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
183#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
184#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
185
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800186/* I2C */
187#define CONFIG_SYS_I2C
188#define CONFIG_SYS_I2C_FSL
189#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
190#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
191#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
192#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
193
194/*
195 * General PCI
196 * Memory space is mapped 1-1, but I/O space must start from 0.
197 */
198
199/* controller 1, direct to uli, tgtid 3, Base address 20000 */
200#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
201#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
202#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
203#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
204#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
205#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
206#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
207#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
208
209/* controller 2, Slot 2, tgtid 2, Base address 201000 */
210#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
211#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
212#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
213#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
214#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
215#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
216#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
217#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
218
219/* controller 3, Slot 1, tgtid 1, Base address 202000 */
220#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
221#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
222#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
223#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
224#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
225#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
226#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
227#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
228
229/* controller 4, Base address 203000 */
230#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
231#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
232#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
233#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
234#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
235#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
236
237#ifdef CONFIG_PCI
238#define CONFIG_PCI_INDIRECT_BRIDGE
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800239
240#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800241#endif /* CONFIG_PCI */
242
243/* SATA */
244#ifdef CONFIG_FSL_SATA_V2
245#define CONFIG_LIBATA
246#define CONFIG_FSL_SATA
247
248#define CONFIG_SYS_SATA_MAX_DEVICE 2
249#define CONFIG_SATA1
250#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
251#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
252#define CONFIG_SATA2
253#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
254#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
255
256#define CONFIG_LBA48
257#define CONFIG_CMD_SATA
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800258#endif
259
260#ifdef CONFIG_FMAN_ENET
261#define CONFIG_MII /* MII PHY management */
262#define CONFIG_ETHPRIME "FM1@DTSEC1"
263#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
264#endif
265
266/*
267 * Environment
268 */
269#define CONFIG_LOADS_ECHO /* echo on for serial download */
270#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
271
272/*
273 * Command line configuration.
274 */
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800275
276#ifdef CONFIG_PCI
277#define CONFIG_CMD_PCI
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800278#endif
279
280/*
281 * Miscellaneous configurable options
282 */
283#define CONFIG_SYS_LONGHELP /* undef to save memory */
284#define CONFIG_CMDLINE_EDITING /* Command-line editing */
285#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
286#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
287#ifdef CONFIG_CMD_KGDB
288#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
289#else
290#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
291#endif
292#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
293#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
294#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
295
296/*
297 * For booting Linux, the board info and command line data
298 * have to be in the first 64 MB of memory, since this is
299 * the maximum mapped by the Linux kernel during initialization.
300 */
301#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
302#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
303
304#ifdef CONFIG_CMD_KGDB
305#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
306#endif
307
308/*
309 * Environment Configuration
310 */
311#define CONFIG_ROOTPATH "/opt/nfsroot"
312#define CONFIG_BOOTFILE "uImage"
313#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
314
315/* default location for tftp and bootm */
316#define CONFIG_LOADADDR 1000000
317
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800318#define CONFIG_HVBOOT \
319 "setenv bootargs config-addr=0x60000000; " \
320 "bootm 0x01000000 - 0x00f00000"
321
Masahiro Yamadae856bdc2017-02-11 22:43:54 +0900322#ifndef CONFIG_MTD_NOR_FLASH
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800323#ifndef CONFIG_RAMBOOT_PBL
324#define CONFIG_ENV_IS_NOWHERE
325#endif
326#else
327#define CONFIG_FLASH_CFI_DRIVER
328#define CONFIG_SYS_FLASH_CFI
329#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
330#endif
331
332#if defined(CONFIG_SPIFLASH)
333#define CONFIG_SYS_EXTRA_ENV_RELOC
334#define CONFIG_ENV_IS_IN_SPI_FLASH
335#define CONFIG_ENV_SPI_BUS 0
336#define CONFIG_ENV_SPI_CS 0
337#define CONFIG_ENV_SPI_MAX_HZ 10000000
338#define CONFIG_ENV_SPI_MODE 0
339#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
340#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
341#define CONFIG_ENV_SECT_SIZE 0x10000
342#elif defined(CONFIG_SDCARD)
343#define CONFIG_SYS_EXTRA_ENV_RELOC
344#define CONFIG_ENV_IS_IN_MMC
345#define CONFIG_SYS_MMC_ENV_DEV 0
346#define CONFIG_ENV_SIZE 0x2000
Chunhe Lan373762c2015-03-20 17:08:54 +0800347#define CONFIG_ENV_OFFSET (512 * 0x800)
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800348#elif defined(CONFIG_NAND)
349#define CONFIG_SYS_EXTRA_ENV_RELOC
350#define CONFIG_ENV_IS_IN_NAND
351#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
352#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
353#elif defined(CONFIG_ENV_IS_NOWHERE)
354#define CONFIG_ENV_SIZE 0x2000
355#else
356#define CONFIG_ENV_IS_IN_FLASH
357#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
358#define CONFIG_ENV_SIZE 0x2000
359#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
360#endif
361
362#define CONFIG_SYS_CLK_FREQ 66666666
363#define CONFIG_DDR_CLK_FREQ 133333333
364
365#ifndef __ASSEMBLY__
366unsigned long get_board_sys_clk(void);
367unsigned long get_board_ddr_clk(void);
368#endif
369
370/*
371 * DDR Setup
372 */
373#define CONFIG_SYS_SPD_BUS_NUM 0
374#define SPD_EEPROM_ADDRESS1 0x52
375#define SPD_EEPROM_ADDRESS2 0x54
376#define SPD_EEPROM_ADDRESS3 0x56
377#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
378#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
379
380/*
381 * IFC Definitions
382 */
383#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
384#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
385 + 0x8000000) | \
386 CSPR_PORT_SIZE_16 | \
387 CSPR_MSEL_NOR | \
388 CSPR_V)
389#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
390#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
391 CSPR_PORT_SIZE_16 | \
392 CSPR_MSEL_NOR | \
393 CSPR_V)
394#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
395/* NOR Flash Timing Params */
396#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
397
398#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
399 FTIM0_NOR_TEADC(0x5) | \
400 FTIM0_NOR_TEAHC(0x5))
401#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
402 FTIM1_NOR_TRAD_NOR(0x1A) |\
403 FTIM1_NOR_TSEQRAD_NOR(0x13))
404#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
405 FTIM2_NOR_TCH(0x4) | \
406 FTIM2_NOR_TWPH(0x0E) | \
407 FTIM2_NOR_TWP(0x1c))
408#define CONFIG_SYS_NOR_FTIM3 0x0
409
410#define CONFIG_SYS_FLASH_QUIET_TEST
411#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
412
413#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
414#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
415#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
416#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
417
418#define CONFIG_SYS_FLASH_EMPTY_INFO
419#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
420 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
421
422/* NAND Flash on IFC */
423#define CONFIG_NAND_FSL_IFC
424#define CONFIG_SYS_NAND_MAX_ECCPOS 256
425#define CONFIG_SYS_NAND_MAX_OOBFREE 2
426#define CONFIG_SYS_NAND_BASE 0xff800000
427#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
428
429#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
430#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
431 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
432 | CSPR_MSEL_NAND /* MSEL = NAND */ \
433 | CSPR_V)
434#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
435
436#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
437 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
438 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
439 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
440 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
441 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
442 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
443
444#define CONFIG_SYS_NAND_ONFI_DETECTION
445
446/* ONFI NAND Flash mode0 Timing Params */
447#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
448 FTIM0_NAND_TWP(0x18) | \
449 FTIM0_NAND_TWCHT(0x07) | \
450 FTIM0_NAND_TWH(0x0a))
451#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
452 FTIM1_NAND_TWBE(0x39) | \
453 FTIM1_NAND_TRR(0x0e) | \
454 FTIM1_NAND_TRP(0x18))
455#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
456 FTIM2_NAND_TREH(0x0a) | \
457 FTIM2_NAND_TWHRE(0x1e))
458#define CONFIG_SYS_NAND_FTIM3 0x0
459
460#define CONFIG_SYS_NAND_DDR_LAW 11
461#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
462#define CONFIG_SYS_MAX_NAND_DEVICE 1
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800463#define CONFIG_CMD_NAND
464
465#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
466
467#if defined(CONFIG_NAND)
468#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
469#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
470#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
471#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
472#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
473#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
474#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
475#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
476#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
477#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
478#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
479#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
480#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
481#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
482#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
483#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
484#else
485#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
486#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
487#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
488#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
489#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
490#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
491#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
492#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
493#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
494#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
495#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
496#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
497#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
498#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
499#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
500#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
501#endif
502#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
503#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
504#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
505#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
506#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
507#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
508#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
509#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
510
Chunhe Lanab06b232014-09-12 14:47:09 +0800511/* CPLD on IFC */
512#define CONFIG_SYS_CPLD_BASE 0xffdf0000
513#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
514#define CONFIG_SYS_CSPR3_EXT (0xf)
515#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
516 | CSPR_PORT_SIZE_8 \
517 | CSPR_MSEL_GPCM \
518 | CSPR_V)
519
520#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
521#define CONFIG_SYS_CSOR3 0x0
522
523/* CPLD Timing parameters for IFC CS3 */
524#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
525 FTIM0_GPCM_TEADC(0x0e) | \
526 FTIM0_GPCM_TEAHC(0x0e))
527#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
528 FTIM1_GPCM_TRAD(0x1f))
529#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Chunhe Lan1b5c2b52014-10-20 16:03:15 +0800530 FTIM2_GPCM_TCH(0x8) | \
Chunhe Lanab06b232014-09-12 14:47:09 +0800531 FTIM2_GPCM_TWP(0x1f))
532#define CONFIG_SYS_CS3_FTIM3 0x0
533
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800534#if defined(CONFIG_RAMBOOT_PBL)
535#define CONFIG_SYS_RAMBOOT
536#endif
537
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800538/* I2C */
539#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
540#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
541#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
542#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
543
544#define I2C_MUX_CH_DEFAULT 0x8
545#define I2C_MUX_CH_VOL_MONITOR 0xa
546#define I2C_MUX_CH_VSC3316_FS 0xc
547#define I2C_MUX_CH_VSC3316_BS 0xd
548
549/* Voltage monitor on channel 2*/
550#define I2C_VOL_MONITOR_ADDR 0x40
551#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
552#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
553#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
554
Ying Zhang2f66a822016-01-22 12:15:13 +0800555#define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv"
556#ifndef CONFIG_SPL_BUILD
557#define CONFIG_VID
558#endif
559#define CONFIG_VOL_MONITOR_IR36021_SET
560#define CONFIG_VOL_MONITOR_IR36021_READ
561/* The lowest and highest voltage allowed for T4240RDB */
562#define VDD_MV_MIN 819
563#define VDD_MV_MAX 1212
564
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800565/*
566 * eSPI - Enhanced SPI
567 */
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800568#define CONFIG_SF_DEFAULT_SPEED 10000000
569#define CONFIG_SF_DEFAULT_MODE 0
570
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800571/* Qman/Bman */
572#ifndef CONFIG_NOBQFMAN
573#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
574#define CONFIG_SYS_BMAN_NUM_PORTALS 50
575#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
576#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
577#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500578#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
579#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
580#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
581#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
582#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
583 CONFIG_SYS_BMAN_CENA_SIZE)
584#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
585#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800586#define CONFIG_SYS_QMAN_NUM_PORTALS 50
587#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
588#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
589#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500590#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
591#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
592#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
593#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
594#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
595 CONFIG_SYS_QMAN_CENA_SIZE)
596#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
597#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800598
599#define CONFIG_SYS_DPAA_FMAN
600#define CONFIG_SYS_DPAA_PME
601#define CONFIG_SYS_PMAN
602#define CONFIG_SYS_DPAA_DCE
603#define CONFIG_SYS_DPAA_RMAN
604#define CONFIG_SYS_INTERLAKEN
605
606/* Default address of microcode for the Linux Fman driver */
607#if defined(CONFIG_SPIFLASH)
608/*
609 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
610 * env, so we got 0x110000.
611 */
612#define CONFIG_SYS_QE_FW_IN_SPIFLASH
613#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
614#elif defined(CONFIG_SDCARD)
615/*
616 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
Chunhe Lan373762c2015-03-20 17:08:54 +0800617 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
618 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800619 */
620#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
Chunhe Lan373762c2015-03-20 17:08:54 +0800621#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800622#elif defined(CONFIG_NAND)
623#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
624#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
625#else
626#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
627#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
628#endif
629#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
630#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
631#endif /* CONFIG_NOBQFMAN */
632
633#ifdef CONFIG_SYS_DPAA_FMAN
634#define CONFIG_FMAN_ENET
635#define CONFIG_PHYLIB_10G
636#define CONFIG_PHY_VITESSE
637#define CONFIG_PHY_CORTINA
Chunhe Lana8efe792015-03-24 15:10:41 +0800638#define CONFIG_SYS_CORTINA_FW_IN_NOR
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800639#define CONFIG_CORTINA_FW_ADDR 0xefe00000
640#define CONFIG_CORTINA_FW_LENGTH 0x40000
641#define CONFIG_PHY_TERANETICS
642#define SGMII_PHY_ADDR1 0x0
643#define SGMII_PHY_ADDR2 0x1
644#define SGMII_PHY_ADDR3 0x2
645#define SGMII_PHY_ADDR4 0x3
646#define SGMII_PHY_ADDR5 0x4
647#define SGMII_PHY_ADDR6 0x5
648#define SGMII_PHY_ADDR7 0x6
649#define SGMII_PHY_ADDR8 0x7
650#define FM1_10GEC1_PHY_ADDR 0x10
651#define FM1_10GEC2_PHY_ADDR 0x11
652#define FM2_10GEC1_PHY_ADDR 0x12
653#define FM2_10GEC2_PHY_ADDR 0x13
654#define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
655#define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
656#define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
657#define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
658#endif
659
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800660/* SATA */
661#ifdef CONFIG_FSL_SATA_V2
662#define CONFIG_LIBATA
663#define CONFIG_FSL_SATA
664
665#define CONFIG_SYS_SATA_MAX_DEVICE 2
666#define CONFIG_SATA1
667#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
668#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
669#define CONFIG_SATA2
670#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
671#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
672
673#define CONFIG_LBA48
674#define CONFIG_CMD_SATA
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800675#endif
676
677#ifdef CONFIG_FMAN_ENET
678#define CONFIG_MII /* MII PHY management */
679#define CONFIG_ETHPRIME "FM1@DTSEC1"
680#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
681#endif
682
683/*
684* USB
685*/
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800686#define CONFIG_USB_EHCI_FSL
687#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800688#define CONFIG_HAS_FSL_DR_USB
689
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800690#ifdef CONFIG_MMC
691#define CONFIG_FSL_ESDHC
692#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
693#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
Xiaobo Xie929dfdc2014-11-18 09:12:24 +0800694#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800695#endif
696
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800697
698#define __USB_PHY_TYPE utmi
699
700/*
701 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
702 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
703 * interleaving. It can be cacheline, page, bank, superbank.
704 * See doc/README.fsl-ddr for details.
705 */
York Sun26bc57d2016-11-21 13:35:41 -0800706#ifdef CONFIG_ARCH_T4240
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800707#define CTRL_INTLV_PREFERED 3way_4KB
Chunhe Lan1a344452014-05-07 10:56:18 +0800708#else
709#define CTRL_INTLV_PREFERED cacheline
710#endif
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800711
712#define CONFIG_EXTRA_ENV_SETTINGS \
713 "hwconfig=fsl_ddr:" \
714 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
715 "bank_intlv=auto;" \
716 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
717 "netdev=eth0\0" \
718 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
719 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
720 "tftpflash=tftpboot $loadaddr $uboot && " \
721 "protect off $ubootaddr +$filesize && " \
722 "erase $ubootaddr +$filesize && " \
723 "cp.b $loadaddr $ubootaddr $filesize && " \
724 "protect on $ubootaddr +$filesize && " \
725 "cmp.b $loadaddr $ubootaddr $filesize\0" \
726 "consoledev=ttyS0\0" \
727 "ramdiskaddr=2000000\0" \
728 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
Scott Woodb24a4f62016-07-19 17:52:06 -0500729 "fdtaddr=1e00000\0" \
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800730 "fdtfile=t4240rdb/t4240rdb.dtb\0" \
731 "bdev=sda3\0"
732
733#define CONFIG_HVBOOT \
734 "setenv bootargs config-addr=0x60000000; " \
735 "bootm 0x01000000 - 0x00f00000"
736
737#define CONFIG_LINUX \
738 "setenv bootargs root=/dev/ram rw " \
739 "console=$consoledev,$baudrate $othbootargs;" \
740 "setenv ramdiskaddr 0x02000000;" \
741 "setenv fdtaddr 0x00c00000;" \
742 "setenv loadaddr 0x1000000;" \
743 "bootm $loadaddr $ramdiskaddr $fdtaddr"
744
745#define CONFIG_HDBOOT \
746 "setenv bootargs root=/dev/$bdev rw " \
747 "console=$consoledev,$baudrate $othbootargs;" \
748 "tftp $loadaddr $bootfile;" \
749 "tftp $fdtaddr $fdtfile;" \
750 "bootm $loadaddr - $fdtaddr"
751
752#define CONFIG_NFSBOOTCOMMAND \
753 "setenv bootargs root=/dev/nfs rw " \
754 "nfsroot=$serverip:$rootpath " \
755 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
756 "console=$consoledev,$baudrate $othbootargs;" \
757 "tftp $loadaddr $bootfile;" \
758 "tftp $fdtaddr $fdtfile;" \
759 "bootm $loadaddr - $fdtaddr"
760
761#define CONFIG_RAMBOOTCOMMAND \
762 "setenv bootargs root=/dev/ram rw " \
763 "console=$consoledev,$baudrate $othbootargs;" \
764 "tftp $ramdiskaddr $ramdiskfile;" \
765 "tftp $loadaddr $bootfile;" \
766 "tftp $fdtaddr $fdtfile;" \
767 "bootm $loadaddr $ramdiskaddr $fdtaddr"
768
769#define CONFIG_BOOTCOMMAND CONFIG_LINUX
770
771#include <asm/fsl_secure_boot.h>
772
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800773#endif /* __CONFIG_H */