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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 6e38e2ea795e7e36abe8755f536747b76a29094f / . / arch / arm / dts / zynqmp-m-a2197-03-revA.dts
blob: db199c467b0d5f27407e397f711cb2da9d91cb8a [file] [log] [blame]
Michal Simek3d5c9062019-06-28 13:53:45 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx Versal a2197 RevA System Controller
4 *
5 * (C) Copyright 2019, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9/dts-v1/;
10
11#include "zynqmp.dtsi"
12#include "zynqmp-clk-ccf.dtsi"
13#include <dt-bindings/gpio/gpio.h>
14
15/ {
16 model = "Versal System Controller on a2197 Memory Char board RevA";
17 compatible = "xlnx,zynqmp-m-a2197-03-revA", "xlnx,zynqmp-a2197-revA",
18 "xlnx,zynqmp-a2197", "xlnx,zynqmp";
19
20 aliases {
21 ethernet0 = &gem0;
Michal Simek3d5c9062019-06-28 13:53:45 +0200[diff] [blame]22 i2c0 = &i2c0;
23 i2c1 = &i2c1;
24 mmc0 = &sdhci0;
25 mmc1 = &sdhci1;
Michal Simek531abcb2021-06-03 11:46:50 +0200[diff] [blame]26 nvmem0 = &eeprom;
Michal Simek3d5c9062019-06-28 13:53:45 +0200[diff] [blame]27 rtc0 = &rtc;
28 serial0 = &uart0;
29 serial1 = &uart1;
30 serial2 = &dcc;
31 usb0 = &usb0;
32 usb1 = &usb1;
33 spi0 = &qspi;
34 };
35
36 chosen {
37 bootargs = "earlycon";
38 stdout-path = "serial0:115200n8";
Michal Simek3d5c9062019-06-28 13:53:45 +0200[diff] [blame]39 };
40
41 memory@0 {
42 device_type = "memory";
43 reg = <0x0 0x0 0x0 0x80000000>; /* FIXME don't know how big memory is there */
44 };
45
46 ina226-vcc-aux {
47 compatible = "iio-hwmon";
48 io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;
49 };
50 ina226-vcc-ram {
51 compatible = "iio-hwmon";
52 io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
53 };
54 ina226-vcc1v1-lp4 {
55 compatible = "iio-hwmon";
56 io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
57 };
58 ina226-vcc1v2-lp4 {
59 compatible = "iio-hwmon";
60 io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;
61 };
62 ina226-vdd1-1v8-lp4 {
63 compatible = "iio-hwmon";
64 io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;
65 };
66};
67
68&qspi {
69 status = "okay";
70 is-dual = <1>;
71 flash@0 {
72 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
73 #address-cells = <1>;
74 #size-cells = <1>;
75 reg = <0x0>;
Amit Kumar Mahapatra6e38e2e2022-05-10 16:33:01 +0200[diff] [blame^]76 spi-tx-bus-width = <4>;
Michal Simek3d5c9062019-06-28 13:53:45 +0200[diff] [blame]77 spi-rx-bus-width = <4>;
78 spi-max-frequency = <108000000>;
79 };
80};
81
82&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */
83 status = "okay";
84 non-removable;
85 disable-wp;
86 bus-width = <8>;
Michal Simek01a6da12020-07-22 17:42:43 +0200[diff] [blame]87 xlnx,mio-bank = <0>; /* FIXME tap delay */
Michal Simek3d5c9062019-06-28 13:53:45 +0200[diff] [blame]88};
89
90&uart0 { /* uart0 MIO38-39 */
91 status = "okay";
Michal Simek3d5c9062019-06-28 13:53:45 +0200[diff] [blame]92};
93
94&uart1 { /* uart1 MIO40-41 */
95 status = "okay";
Michal Simek3d5c9062019-06-28 13:53:45 +0200[diff] [blame]96};
97
98&sdhci1 { /* sd1 MIO45-51 cd in place */
99 status = "disable";
100 no-1-8-v;
101 disable-wp;
Michal Simek01a6da12020-07-22 17:42:43 +0200[diff] [blame]102 xlnx,mio-bank = <1>;
Michal Simek3d5c9062019-06-28 13:53:45 +0200[diff] [blame]103};
104
105&gem0 {
106 status = "okay";
107 phy-handle = <&phy0>;
108 phy-mode = "sgmii";
109 phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
110 phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */
111 reg = <0>;
112 };
113};
114
115&gpio {
116 status = "okay";
117 gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */
118 "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */
119 "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
120 "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
121 "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
122 "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */
123 "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
124 "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
125 "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */
126 "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
127 "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
128 "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
129 "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */
130 "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */
131 "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
132 "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
133 "", "", "", "", "", /* 78 - 79 */
134 "", "", "", "", "", /* 80 - 84 */
135 "", "", "", "", "", /* 85 -89 */
136 "", "", "", "", "", /* 90 - 94 */
137 "", "", "", "", "", /* 95 - 99 */
138 "", "", "", "", "", /* 100 - 104 */
139 "", "", "", "", "", /* 105 - 109 */
140 "", "", "", "", "", /* 110 - 114 */
141 "", "", "", "", "", /* 115 - 119 */
142 "", "", "", "", "", /* 120 - 124 */
143 "", "", "", "", "", /* 125 - 129 */
144 "", "", "", "", "", /* 130 - 134 */
145 "", "", "", "", "", /* 135 - 139 */
146 "", "", "", "", "", /* 140 - 144 */
147 "", "", "", "", "", /* 145 - 149 */
148 "", "", "", "", "", /* 150 - 154 */
149 "", "", "", "", "", /* 155 - 159 */
150 "", "", "", "", "", /* 160 - 164 */
151 "", "", "", "", "", /* 165 - 169 */
152 "", "", "", ""; /* 170 - 174 */
153};
154
155&i2c0 { /* MIO 34-35 - can't stay here */
156 status = "okay";
157 clock-frequency = <400000>;
158 i2c-mux@74 { /* u46 */
159 compatible = "nxp,pca9548";
160 #address-cells = <1>;
161 #size-cells = <0>;
162 reg = <0x74>;
163 /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
164 i2c@0 { /* PMBUS must be enabled via SW21 */
165 #address-cells = <1>;
166 #size-cells = <0>;
167 reg = <0>;
168 reg_vcc1v2_lp4: tps544@15 { /* u97 */
169 compatible = "ti,tps544b25";
170 reg = <0x15>;
171 };
172 reg_vcc1v1_lp4: tps544@16 { /* u95 */
173 compatible = "ti,tps544b25";
174 reg = <0x16>;
175 };
176 reg_vdd1_1v8_lp4: tps544@17 { /* u99 */
177 compatible = "ti,tps544b25";
178 reg = <0x17>;
179 };
180 /* UTIL_PMBUS connection */
181 reg_vcc1v8: tps544@13 { /* u92 */
182 compatible = "ti,tps544b25";
183 reg = <0x13>;
184 };
185 reg_vcc3v3: tps544@14 { /* u93 */
186 compatible = "ti,tps544b25";
187 reg = <0x14>;
188 };
189 reg_vcc5v0: tps544@1e { /* u94 */
190 compatible = "ti,tps544b25";
191 reg = <0x1e>;
192 };
193 reg_vpp_2v5_ddr4: tps544@1x { /* u3007 */
194 compatible = "ti,tps544b25";
195 reg = <0x17>; /* FIXME wrong in schematics */
196 };
197 };
198 i2c@1 { /* PMBUS_INA226 */
199 #address-cells = <1>;
200 #size-cells = <0>;
201 reg = <1>;
202 vcc_aux: ina226@42 { /* u86 */
203 compatible = "ti,ina226";
204 #io-channel-cells = <1>;
205 label = "ina226-vcc-aux";
206 reg = <0x42>;
207 shunt-resistor = <5000>;
208 };
209 vcc_ram: ina226@43 { /* u81 */
210 compatible = "ti,ina226";
211 #io-channel-cells = <1>;
212 label = "ina226-vcc-ram";
213 reg = <0x43>;
214 shunt-resistor = <5000>;
215 };
216 vcc1v1_lp4: ina226@46 { /* u96 */
217 compatible = "ti,ina226";
218 #io-channel-cells = <1>;
219 label = "ina226-vcc1v1-lp4";
220 reg = <0x46>;
221 shunt-resistor = <5000>;
222 };
223 vcc1v2_lp4: ina226@47 { /* u98 */
224 compatible = "ti,ina226";
225 #io-channel-cells = <1>;
226 label = "ina226-vcc1v2-lp4";
227 reg = <0x47>;
228 shunt-resistor = <5000>;
229 };
230 vdd1_1v8_lp4: ina226@48 { /* u100 */
231 compatible = "ti,ina226";
232 #io-channel-cells = <1>;
233 label = "ina226-vdd1-1v8-lp4";
234 reg = <0x48>;
235 shunt-resistor = <5000>;
236 };
237 };
238 i2c@2 { /* PMBUS1 */
239 #address-cells = <1>;
240 #size-cells = <0>;
241 reg = <2>;
242 reg_vccint: tps53681@c0 { /* u69 */
243 compatible = "ti,tps53681", "ti,tps53679";
244 reg = <0xc0>;
245 };
246 reg_vcc_pmc: tps544@7 { /* u80 */
247 compatible = "ti,tps544b25";
248 reg = <0x7>;
249 };
250 reg_vcc_ram: tps544@8 { /* u82 */
251 compatible = "ti,tps544b25";
252 reg = <0x8>;
253 };
254 reg_vcc_pslp: tps544@9 { /* u83 */
255 compatible = "ti,tps544b25";
256 reg = <0x9>;
257 };
258 reg_vcc_psfp: tps544@a { /* u84 */
259 compatible = "ti,tps544b25";
260 reg = <0xa>;
261 };
262 reg_vccaux: tps544@d { /* u85 */
263 compatible = "ti,tps544b25";
264 reg = <0xd>;
265 };
266 reg_vccaux_pmc: tps544@e { /* u87 */
267 compatible = "ti,tps544b25";
268 reg = <0xe>;
269 };
270 reg_vcco_500: tps544@f { /* u88 */
271 compatible = "ti,tps544b25";
272 reg = <0xf>;
273 };
274 reg_vcco_501: tps544@10 { /* u89 */
275 compatible = "ti,tps544b25";
276 reg = <0x10>;
277 };
278 reg_vcco_502: tps544@11 { /* u90 */
279 compatible = "ti,tps544b25";
280 reg = <0x11>;
281 };
282 reg_vcco_503: tps544@12 { /* u91 */
283 compatible = "ti,tps544b25";
284 reg = <0x12>;
285 };
286 };
287 i2c@3 { /* MEM PMBUS - FIXME bug in schematics */
288 #address-cells = <1>;
289 #size-cells = <0>;
290 /* reg = <3>; */
291 };
292 i2c@4 { /* LP_I2C_SM */
293 #address-cells = <1>;
294 #size-cells = <0>;
295 reg = <4>;
296 /* connected to U20G */
297 };
298 i2c@5 { /* DDR4_SODIMM */
299 #address-cells = <1>;
300 #size-cells = <0>;
301 reg = <5>;
302 };
303 };
304};
305
306/* TODO sysctrl via J239 */
307/* TODO samtec J212G/H via J242 */
308/* TODO teensy via U30 PCA9543A bus 1 */
309&i2c1 { /* i2c1 MIO 36-37 */
310 status = "okay";
311 clock-frequency = <400000>;
312
313 /* Must be enabled via J242 */
314 eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */
315 compatible = "atmel,24c02";
316 reg = <0x51>;
317 };
318
319 i2c-mux@74 { /* u47 */
320 compatible = "nxp,pca9548";
321 #address-cells = <1>;
322 #size-cells = <0>;
323 reg = <0x74>;
324 /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */
325 dc_i2c: i2c@0 { /* DC_I2C */
326 #address-cells = <1>;
327 #size-cells = <0>;
328 reg = <0>;
329 /* Use for storing information about SC board */
330 eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */
331 compatible = "atmel,24c08";
332 reg = <0x54>;
333 };
334 si570_ref_clk: clock-generator@5d { /* u26 */
335 #clock-cells = <0>;
336 compatible = "silabs,si570";
337 reg = <0x5d>; /* FIXME addr */
338 temperature-stability = <50>;
Michal Simeka34a12f2021-03-09 12:43:42 +0100[diff] [blame]339 factory-fout = <33333333>;
Michal Simek3d5c9062019-06-28 13:53:45 +0200[diff] [blame]340 clock-frequency = <33333333>;
341 clock-output-names = "REF_CLK"; /* FIXME */
Michal Simeka34a12f2021-03-09 12:43:42 +0100[diff] [blame]342 silabs,skip-recall;
Michal Simek3d5c9062019-06-28 13:53:45 +0200[diff] [blame]343 };
344 /* Connection via Samtec U20D */
345 /* Use for storing information about X-PRC card */
346 x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */
347 compatible = "atmel,24c02";
348 reg = <0x52>;
349 };
350
351 /* Use for setting up certain features on X-PRC card */
352 x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */
353 compatible = "nxp,pca9534";
354 reg = <0x22>;
355 gpio-controller; /* IRQ not connected */
356 #gpio-cells = <2>;
357 gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
358 "", "", "", "";
359 gtr_sel0 {
360 gpio-hog;
361 gpios = <0 0>;
362 input; /* FIXME add meaning */
363 line-name = "sw4_1";
364 };
365 gtr_sel1 {
366 gpio-hog;
367 gpios = <1 0>;
368 input; /* FIXME add meaning */
369 line-name = "sw4_2";
370 };
371 gtr_sel2 {
372 gpio-hog;
373 gpios = <2 0>;
374 input; /* FIXME add meaning */
375 line-name = "sw4_3";
376 };
377 gtr_sel3 {
378 gpio-hog;
379 gpios = <3 0>;
380 input; /* FIXME add meaning */
381 line-name = "sw4_4";
382 };
383 };
384 };
385 i2c@2 { /* C0_DDR4 */
386 #address-cells = <1>;
387 #size-cells = <0>;
388 reg = <2>;
389 si570_c0_ddr4: clock-generator@55 { /* u4 */
390 #clock-cells = <0>;
391 compatible = "silabs,si570";
392 reg = <0x55>;
393 temperature-stability = <50>;
394 factory-fout = <30000000>;
395 clock-frequency = <30000000>;
396 clock-output-names = "C0_DD4_SI570_CLK";
397 };
398 };
399 i2c@3 { /* C1_SODIMM */
400 #address-cells = <1>;
401 #size-cells = <0>;
402 reg = <3>;
403 si570_c1_lp4: clock-generator@55 { /* u7 */
404 #clock-cells = <0>;
405 compatible = "silabs,si570";
406 reg = <0x55>;
407 temperature-stability = <50>;
408 factory-fout = <30000000>;
409 clock-frequency = <30000000>;
410 clock-output-names = "C1_SODIMM_SI570_CLK";
411 };
412 };
413 i2c@4 { /* C2_QDRIV */
414 #address-cells = <1>;
415 #size-cells = <0>;
416 reg = <4>;
417 si570_c2_lp4: clock-generator@55 { /* u10 */
418 #clock-cells = <0>;
419 compatible = "silabs,si570";
420 reg = <0x55>;
421 temperature-stability = <50>;
422 factory-fout = <30000000>;
423 clock-frequency = <30000000>;
424 clock-output-names = "C2_QDRIV_SI570_CLK";
425 };
426 };
427 i2c@5 { /* C3_DDR4 */
428 #address-cells = <1>;
429 #size-cells = <0>;
430 reg = <5>;
431 si570_c3_lp4: clock-generator@55 { /* u15 */
432 #clock-cells = <0>;
433 compatible = "silabs,si570";
434 reg = <0x55>;
435 temperature-stability = <50>;
436 factory-fout = <30000000>;
437 clock-frequency = <30000000>;
438 clock-output-names = "C3_LP4_SI570_CLK";
439 };
440 };
441 i2c@6 { /* HSDP_SI570 */
442 #address-cells = <1>;
443 #size-cells = <0>;
444 reg = <6>;
445 si570_hsdp: clock-generator@5d { /* u19 */
446 #clock-cells = <0>;
447 compatible = "silabs,si570";
448 reg = <0x5d>;
449 temperature-stability = <50>;
450 factory-fout = <156250000>;
451 clock-frequency = <156250000>;
452 clock-output-names = "HSDP_SI570";
453 };
454 };
455 };
456};
457
458&usb0 {
459 status = "okay";
460 xlnx,usb-polarity = <0>;
461 xlnx,usb-reset-mode = <0>;
462};
463
464&dwc3_0 {
465 status = "okay";
466 dr_mode = "host";
467 /* dr_mode = "peripheral"; */
468 maximum-speed = "high-speed";
469};
470
471&usb1 {
472 status = "disabled"; /* not at mem board */
473 xlnx,usb-polarity = <0>;
474 xlnx,usb-reset-mode = <0>;
475};
476
477&dwc3_1 {
478 /delete-property/ phy-names ;
479 /delete-property/ phys ;
480 maximum-speed = "high-speed";
481 snps,dis_u2_susphy_quirk ;
482 snps,dis_u3_susphy_quirk ;
483 status = "disabled";
484};