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Stefan Roese04386f62015-10-02 08:20:35 +02001/*
2 * (C) Copyright 2007-2013
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <command.h>
10#include <asm/ppc440.h>
11#include <asm/processor.h>
12#include <asm/ppc4xx-gpio.h>
13#include <asm/io.h>
14#include <post.h>
15#include <flash.h>
16#include <mtd/cfi_flash.h>
17
18DECLARE_GLOBAL_DATA_PTR;
19
20static phys_addr_t lwmon5_cfi_flash_bank_addr[2] = CONFIG_SYS_FLASH_BANKS_LIST;
21
22ulong flash_get_size(ulong base, int banknum);
23int misc_init_r_kbd(void);
24
25int board_early_init_f(void)
26{
27 u32 sdr0_pfc1, sdr0_pfc2;
28 u32 reg;
29
30 /* PLB Write pipelining disabled. Denali Core workaround */
31 mtdcr(PLB4A0_ACR, 0xDE000000);
32 mtdcr(PLB4A1_ACR, 0xDE000000);
33
34 /*--------------------------------------------------------------------
35 * Setup the interrupt controller polarities, triggers, etc.
36 *-------------------------------------------------------------------*/
37 mtdcr(UIC0SR, 0xffffffff); /* clear all. if write with 1 then the status is cleared */
38 mtdcr(UIC0ER, 0x00000000); /* disable all */
39 mtdcr(UIC0CR, 0x00000000); /* we have not critical interrupts at the moment */
40 mtdcr(UIC0PR, 0xFFBFF1EF); /* Adjustment of the polarity */
41 mtdcr(UIC0TR, 0x00000900); /* per ref-board manual */
42 mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
43 mtdcr(UIC0SR, 0xffffffff); /* clear all */
44
45 mtdcr(UIC1SR, 0xffffffff); /* clear all */
46 mtdcr(UIC1ER, 0x00000000); /* disable all */
47 mtdcr(UIC1CR, 0x00000000); /* all non-critical */
48 mtdcr(UIC1PR, 0xFFFFC6A5); /* Adjustment of the polarity */
49 mtdcr(UIC1TR, 0x60000040); /* per ref-board manual */
50 mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
51 mtdcr(UIC1SR, 0xffffffff); /* clear all */
52
53 mtdcr(UIC2SR, 0xffffffff); /* clear all */
54 mtdcr(UIC2ER, 0x00000000); /* disable all */
55 mtdcr(UIC2CR, 0x00000000); /* all non-critical */
56 mtdcr(UIC2PR, 0x27C00000); /* Adjustment of the polarity */
57 mtdcr(UIC2TR, 0x3C000000); /* per ref-board manual */
58 mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
59 mtdcr(UIC2SR, 0xffffffff); /* clear all */
60
61 /* Trace Pins are disabled. SDR0_PFC0 Register */
62 mtsdr(SDR0_PFC0, 0x0);
63
64 /* select Ethernet pins */
65 mfsdr(SDR0_PFC1, sdr0_pfc1);
66 /* SMII via ZMII */
67 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
68 SDR0_PFC1_SELECT_CONFIG_6;
69 mfsdr(SDR0_PFC2, sdr0_pfc2);
70 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
71 SDR0_PFC2_SELECT_CONFIG_6;
72
73 /* enable SPI (SCP) */
74 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
75
76 mtsdr(SDR0_PFC2, sdr0_pfc2);
77 mtsdr(SDR0_PFC1, sdr0_pfc1);
78
79 mtsdr(SDR0_PFC4, 0x80000000);
80
81 /* PCI arbiter disabled */
82 /* PCI Host Configuration disbaled */
83 mfsdr(SDR0_PCI0, reg);
84 reg = 0;
85 mtsdr(SDR0_PCI0, 0x00000000 | reg);
86
87 gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1);
88
89#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
90 /* enable the LSB transmitter */
91 gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1);
92 /* enable the CAN transmitter */
93 gpio_write_bit(CONFIG_SYS_GPIO_CAN_ENABLE, 1);
94
95 reg = 0; /* reuse as counter */
96 out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
97 in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR)
98 & ~CONFIG_SYS_DSPIC_TEST_MASK);
99 while (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) {
100 udelay(1000);
101 }
102 if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) {
103 /* set "boot error" flag */
104 out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
105 in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) |
106 CONFIG_SYS_DSPIC_TEST_MASK);
107 }
108#endif
109
110 /*
111 * Reset PHY's:
112 * The PHY's need a 2nd reset pulse, since the MDIO address is latched
113 * upon reset, and with the first reset upon powerup, the addresses are
114 * not latched reliable, since the IRQ line is multiplexed with an
115 * MDIO address. A 2nd reset at this time will make sure, that the
116 * correct address is latched.
117 */
118 gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
119 gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
120 udelay(1000);
121 gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 0);
122 gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 0);
123 udelay(1000);
124 gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
125 gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
126
127 return 0;
128}
129
130/*
131 * Override weak default with board specific version
132 */
133phys_addr_t cfi_flash_bank_addr(int bank)
134{
135 return lwmon5_cfi_flash_bank_addr[bank];
136}
137
138/*
139 * Override the weak default mapping function with a board specific one
140 */
141u32 flash_get_bank_size(int cs, int idx)
142{
143 return flash_info[idx].size;
144}
145
146int board_early_init_r(void)
147{
148 u32 val0, val1;
149
150 /*
151 * lwmon5 is manufactured in 2 different board versions:
152 * The lwmon5a board has 64MiB NOR flash instead of the
153 * 128MiB of the original lwmon5. Unfortunately the CFI driver
154 * will report 2 banks of 64MiB even for the smaller flash
155 * chip, since the bank is mirrored. To fix this, we bring
156 * one bank into CFI query mode and read its response. This
157 * enables us to detect the real number of flash devices/
158 * banks which will be used later on by the common CFI driver.
159 */
160
161 /* Put bank 0 into CFI command mode and read */
162 out_be32((void *)CONFIG_SYS_FLASH0, 0x00980098);
163 val0 = in_be32((void *)CONFIG_SYS_FLASH0 + FLASH_OFFSET_CFI_RESP);
164 val1 = in_be32((void *)CONFIG_SYS_FLASH1 + FLASH_OFFSET_CFI_RESP);
165
166 /* Reset flash again out of query mode */
167 out_be32((void *)CONFIG_SYS_FLASH0, 0x00f000f0);
168
169 /* When not identical, we have 2 different flash devices/banks */
170 if (val0 != val1)
171 return 0;
172
173 /*
174 * Now we're sure that we're running on a LWMON5a board with
175 * only 64MiB NOR flash in one bank:
176 *
177 * Set flash base address and bank count for CFI driver probing.
178 */
179 cfi_flash_num_flash_banks = 1;
180 lwmon5_cfi_flash_bank_addr[0] = CONFIG_SYS_FLASH0;
181
182 return 0;
183}
184
185int misc_init_r(void)
186{
187 u32 pbcr;
188 int size_val = 0;
189 u32 reg;
Stefan Roese04386f62015-10-02 08:20:35 +0200190 unsigned long usb2d0cr = 0;
191 unsigned long usb2phy0cr, usb2h0cr = 0;
192 unsigned long sdr0_pfc1, sdr0_srst;
Stefan Roese04386f62015-10-02 08:20:35 +0200193
194 /*
195 * FLASH stuff...
196 */
197
198 /* Re-do sizing to get full correct info */
199
200 /* adjust flash start and offset */
201 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
202 gd->bd->bi_flashoffset = 0;
203
204 mfebc(PB0CR, pbcr);
205 size_val = ffs(gd->bd->bi_flashsize) - 21;
206 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
207 mtebc(PB0CR, pbcr);
208
209 /*
210 * Re-check to get correct base address
211 */
212 flash_get_size(gd->bd->bi_flashstart, 0);
213
214 /* Monitor protection ON by default */
215 flash_protect(FLAG_PROTECT_SET, -CONFIG_SYS_MONITOR_LEN, 0xffffffff,
216 &flash_info[cfi_flash_num_flash_banks - 1]);
217
218 /* Env protection ON by default */
219 flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
220 CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1,
221 &flash_info[cfi_flash_num_flash_banks - 1]);
222
Stefan Roese04386f62015-10-02 08:20:35 +0200223 /*
224 * USB suff...
225 */
226
227 /* Reset USB */
228 /* Reset of USB2PHY0 must be active at least 10 us */
229 mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D);
230 udelay(2000);
231
232 mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI |
233 SDR0_SRST1_USB2HPHY | SDR0_SRST1_OPBA2 |
234 SDR0_SRST1_PLB42OPB1 | SDR0_SRST1_OPB2PLB40);
235 udelay(2000);
236
237 /* Errata CHIP_6 */
238
239 /* 1. Set internal PHY configuration */
240 /* SDR Setting */
241 mfsdr(SDR0_PFC1, sdr0_pfc1);
242 mfsdr(SDR0_USB0, usb2d0cr);
243 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
244 mfsdr(SDR0_USB2H0CR, usb2h0cr);
245
246 usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
247 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
248 usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK;
249 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
250 usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
251 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/
252 usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
253 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
254 usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
255 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
256
257 /*
258 * An 8-bit/60MHz interface is the only possible alternative
259 * when connecting the Device to the PHY
260 */
261 usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK;
262 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
263
264 mtsdr(SDR0_PFC1, sdr0_pfc1);
265 mtsdr(SDR0_USB0, usb2d0cr);
266 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
267 mtsdr(SDR0_USB2H0CR, usb2h0cr);
268
269 /* 2. De-assert internal PHY reset */
270 mfsdr(SDR0_SRST1, sdr0_srst);
271 sdr0_srst = sdr0_srst & ~SDR0_SRST1_USB20PHY;
272 mtsdr(SDR0_SRST1, sdr0_srst);
273
274 /* 3. Wait for more than 1 ms */
275 udelay(2000);
276
277 /* 4. De-assert USB 2.0 Host main reset */
278 mfsdr(SDR0_SRST0, sdr0_srst);
279 sdr0_srst = sdr0_srst &~ SDR0_SRST0_USB2H;
280 mtsdr(SDR0_SRST0, sdr0_srst);
281 udelay(1000);
282
283 /* 5. De-assert reset of OPB2 cores */
284 mfsdr(SDR0_SRST1, sdr0_srst);
285 sdr0_srst = sdr0_srst &~ SDR0_SRST1_PLB42OPB1;
286 sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPB2PLB40;
287 sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPBA2;
288 mtsdr(SDR0_SRST1, sdr0_srst);
289 udelay(1000);
290
291 /* 6. Set EHCI Configure FLAG */
292
293 /* 7. Reassert internal PHY reset: */
294 mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY);
295 udelay(1000);
Stefan Roese04386f62015-10-02 08:20:35 +0200296
297 /*
298 * Clear resets
299 */
300 mtsdr(SDR0_SRST1, 0x00000000);
301 mtsdr(SDR0_SRST0, 0x00000000);
302
Stefan Roese04386f62015-10-02 08:20:35 +0200303 printf("USB: Host(int phy) Device(ext phy)\n");
Stefan Roese04386f62015-10-02 08:20:35 +0200304
305 /*
306 * Clear PLB4A0_ACR[WRP]
307 * This fix will make the MAL burst disabling patch for the Linux
308 * EMAC driver obsolete.
309 */
310 reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
311 mtdcr(PLB4A0_ACR, reg);
312
Stefan Roese04386f62015-10-02 08:20:35 +0200313 /*
314 * Init matrix keyboard
315 */
316 misc_init_r_kbd();
Stefan Roese04386f62015-10-02 08:20:35 +0200317
318 return 0;
319}
320
321int checkboard(void)
322{
323 char buf[64];
324 int i = getenv_f("serial#", buf, sizeof(buf));
325
326 printf("Board: %s", __stringify(CONFIG_HOSTNAME));
327
328 if (i > 0) {
329 puts(", serial# ");
330 puts(buf);
331 }
332 putc('\n');
333
334 return (0);
335}
336
337void hw_watchdog_reset(void)
338{
339 int val;
340#if defined(CONFIG_WD_MAX_RATE)
341 unsigned long long ct = get_ticks();
342
343 /*
344 * Don't allow watch-dog triggering more frequently than
345 * the predefined value CONFIG_WD_MAX_RATE [ticks].
346 */
347 if (ct >= gd->arch.wdt_last) {
348 if ((ct - gd->arch.wdt_last) < CONFIG_WD_MAX_RATE)
349 return;
350 } else {
351 /* Time base counter had been reset */
352 if (((unsigned long long)(-1) - gd->arch.wdt_last + ct) <
353 CONFIG_WD_MAX_RATE)
354 return;
355 }
356 gd->arch.wdt_last = get_ticks();
357#endif
358
359 /*
360 * Toggle watchdog output
361 */
362 val = gpio_read_out_bit(CONFIG_SYS_GPIO_WATCHDOG) == 0 ? 1 : 0;
363 gpio_write_bit(CONFIG_SYS_GPIO_WATCHDOG, val);
364}
365
366int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
367{
368 if (argc < 2)
369 return cmd_usage(cmdtp);
370
371 if ((strcmp(argv[1], "on") == 0))
372 gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 1);
373 else if ((strcmp(argv[1], "off") == 0))
374 gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 0);
375 else
376 return cmd_usage(cmdtp);
377
378 return 0;
379}
380
381U_BOOT_CMD(
382 eepromwp, 2, 0, do_eeprom_wp,
383 "eeprom write protect off/on",
384 "<on|off> - enable (on) or disable (off) I2C EEPROM write protect"
385);
386
387#if defined(CONFIG_VIDEO)
388#include <video_fb.h>
389#include <mb862xx.h>
390
391extern GraphicDevice mb862xx;
392
393static const gdc_regs init_regs [] = {
394 { 0x0100, 0x00000f00 },
395 { 0x0020, 0x801401df },
396 { 0x0024, 0x00000000 },
397 { 0x0028, 0x00000000 },
398 { 0x002c, 0x00000000 },
399 { 0x0110, 0x00000000 },
400 { 0x0114, 0x00000000 },
401 { 0x0118, 0x01df0280 },
402 { 0x0004, 0x031f0000 },
403 { 0x0008, 0x027f027f },
404 { 0x000c, 0x015f028f },
405 { 0x0010, 0x020c0000 },
406 { 0x0014, 0x01df01ea },
407 { 0x0018, 0x00000000 },
408 { 0x001c, 0x01e00280 },
409 { 0x0100, 0x80010f00 },
410 { 0x0, 0x0 }
411};
412
413const gdc_regs *board_get_regs(void)
414{
415 return init_regs;
416}
417
418/* Returns Lime base address */
419unsigned int board_video_init(void)
420{
421 /*
422 * Reset Lime controller
423 */
424 gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
425 udelay(500);
426 gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
427
428 mb862xx.winSizeX = 640;
429 mb862xx.winSizeY = 480;
430 mb862xx.gdfBytesPP = 2;
431 mb862xx.gdfIndex = GDF_15BIT_555RGB;
432
433 return CONFIG_SYS_LIME_BASE_0;
434}
435
436#define DEFAULT_BRIGHTNESS 0x64
437
438static void board_backlight_brightness(int brightness)
439{
440 if (brightness > 0) {
441 /* pwm duty, lamp on */
442 out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), brightness);
443 out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x701);
444 } else {
445 /* lamp off */
446 out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), 0x00);
447 out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x00);
448 }
449}
450
451void board_backlight_switch(int flag)
452{
453 char * param;
454 int rc;
455
456 if (flag) {
457 param = getenv("brightness");
458 rc = param ? simple_strtol(param, NULL, 10) : -1;
459 if (rc < 0)
460 rc = DEFAULT_BRIGHTNESS;
461 } else {
462 rc = 0;
463 }
464 board_backlight_brightness(rc);
465}
466
467#if defined(CONFIG_CONSOLE_EXTRA_INFO)
468/*
469 * Return text to be printed besides the logo.
470 */
471void video_get_info_str(int line_number, char *info)
472{
473 if (line_number == 1)
474 strcpy(info, " Board: Lwmon5 (Liebherr Elektronik GmbH)");
475 else
476 info [0] = '\0';
477}
478#endif /* CONFIG_CONSOLE_EXTRA_INFO */
479#endif /* CONFIG_VIDEO */
480
481void board_reset(void)
482{
483 gpio_write_bit(CONFIG_SYS_GPIO_BOARD_RESET, 1);
484}
485
486#ifdef CONFIG_SPL_OS_BOOT
487/*
488 * lwmon5 specific implementation of spl_start_uboot()
489 *
490 * RETURN
491 * 0 if booting into OS is selected (default)
492 * 1 if booting into U-Boot is selected
493 */
494int spl_start_uboot(void)
495{
496 char s[8];
497
498 env_init();
499 getenv_f("boot_os", s, sizeof(s));
500 if ((s != NULL) && (strcmp(s, "yes") == 0))
501 return 0;
502
503 return 1;
504}
505
506/*
507 * This function is called from the SPL U-Boot version for
508 * early init stuff, that needs to be done for OS (e.g. Linux)
509 * booting. Doing it later in the real U-Boot would not work
510 * in case that the SPL U-Boot boots Linux directly.
511 */
512void spl_board_init(void)
513{
514 const gdc_regs *regs = board_get_regs();
515
516 /*
517 * Setup PFC registers, mainly for ethernet support
518 * later on in Linux
519 */
520 board_early_init_f();
521
522 /* enable the LSB transmitter */
523 gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1);
524
525 /*
526 * Clear resets
527 */
528 mtsdr(SDR0_SRST1, 0x00000000);
529 mtsdr(SDR0_SRST0, 0x00000000);
530
531 /*
532 * Reset Lime controller
533 */
534 gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
535 udelay(500);
536 gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
537
538 out_be32((void *)CONFIG_SYS_LIME_SDRAM_CLOCK, CONFIG_SYS_MB862xx_CCF);
539 udelay(300);
540 out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_MB862xx_MMR);
541
542 while (regs->index) {
543 out_be32((void *)(CONFIG_SYS_LIME_BASE_0 + GC_DISP_BASE) +
544 regs->index, regs->value);
545 regs++;
546 }
547
548 board_backlight_brightness(DEFAULT_BRIGHTNESS);
549}
550#endif