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Daniel Gorsulowski33b1d3f2009-06-30 21:03:37 +02001/*
2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
5 *
6 * (C) Copyright 2009
7 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
8 * esd electronic system design gmbh <www.esd.eu>
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#include <common.h>
30#include <asm/arch/at91sam9263.h>
31#include <asm/arch/at91sam9_matrix.h>
32#include <asm/arch/at91sam9_smc.h>
33#include <asm/arch/at91_common.h>
34#include <asm/arch/at91_pmc.h>
35#include <asm/arch/at91_rstc.h>
36#include <asm/arch/clk.h>
37#include <asm/arch/gpio.h>
38#include <asm/arch/hardware.h>
39#include <asm/arch/io.h>
40#include <netdev.h>
41
42DECLARE_GLOBAL_DATA_PTR;
43
44/*
45 * Miscelaneous platform dependent initialisations
46 */
47
48static int hw_rev = -1; /* hardware revision */
49
50int get_hw_rev(void)
51{
52 if (hw_rev >= 0)
53 return hw_rev;
54
55 hw_rev = at91_get_gpio_value(AT91_PIN_PB19);
56 hw_rev |= at91_get_gpio_value(AT91_PIN_PB20) << 1;
57 hw_rev |= at91_get_gpio_value(AT91_PIN_PB21) << 2;
58 hw_rev |= at91_get_gpio_value(AT91_PIN_PB22) << 3;
59
60 if (hw_rev == 15)
61 hw_rev = 0;
62
63 return hw_rev;
64}
65
66#ifdef CONFIG_CMD_NAND
67static void meesc_nand_hw_init(void)
68{
69 unsigned long csa;
70
71 /* Enable CS3 */
72 csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
73 at91_sys_write(AT91_MATRIX_EBI0CSA,
74 csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
75
76 /* Configure SMC CS3 for NAND/SmartMedia */
77 at91_sys_write(AT91_SMC_SETUP(3),
78 AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
79 AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
80 at91_sys_write(AT91_SMC_PULSE(3),
81 AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
82 AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
83 at91_sys_write(AT91_SMC_CYCLE(3),
84 AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
85 at91_sys_write(AT91_SMC_MODE(3),
86 AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
87 AT91_SMC_EXNWMODE_DISABLE |
88#ifdef CONFIG_SYS_NAND_DBW_16
89 AT91_SMC_DBW_16 |
90#else /* CONFIG_SYS_NAND_DBW_8 */
91 AT91_SMC_DBW_8 |
92#endif
93 AT91_SMC_TDF_(2));
94
95 /* Configure RDY/BSY */
96 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
97
98 /* Enable NandFlash */
99 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
100}
101#endif /* CONFIG_CMD_NAND */
102
103#ifdef CONFIG_MACB
104static void meesc_macb_hw_init(void)
105{
106 /* Enable clock */
107 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
108 at91_macb_hw_init();
109}
110#endif
111
112/*
113 * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
114 * controller debugging
115 * The ET1100 is located at physical address 0x70000000
116 * Its process memory is located at physical address 0x70001000
117 */
118static void meesc_ethercat_hw_init(void)
119{
120 /* Configure SMC EBI1_CS0 for EtherCAT */
121 at91_sys_write(AT91_SMC1_SETUP(0),
122 AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
123 AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
124 at91_sys_write(AT91_SMC1_PULSE(0),
125 AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(9) |
126 AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(9));
127 at91_sys_write(AT91_SMC1_CYCLE(0),
128 AT91_SMC_NWECYCLE_(10) | AT91_SMC_NRDCYCLE_(5));
Daniel Gorsulowskia3802792009-09-29 08:03:12 +0200129 /*
130 * Configure behavior at external wait signal, byte-select mode, 16 bit
131 * data bus width, none data float wait states and TDF optimization
132 */
Daniel Gorsulowski33b1d3f2009-06-30 21:03:37 +0200133 at91_sys_write(AT91_SMC1_MODE(0),
134 AT91_SMC_READMODE | AT91_SMC_EXNWMODE_READY |
135 AT91_SMC_BAT_SELECT | AT91_SMC_DBW_16 | AT91_SMC_TDF_(0) |
136 AT91_SMC_TDFMODE);
137
138 /* Configure RDY/BSY */
139 at91_set_B_periph(AT91_PIN_PE20, 0); /* EBI1_NWAIT */
140}
141
142int dram_init(void)
143{
144 gd->bd->bi_dram[0].start = PHYS_SDRAM;
145 gd->bd->bi_dram[0].size = get_ram_size((long *) PHYS_SDRAM, (1 << 27));
146 return 0;
147}
148
149int board_eth_init(bd_t *bis)
150{
151 int rc = 0;
152#ifdef CONFIG_MACB
153 rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00);
154#endif
155 return rc;
156}
157
158int checkboard(void)
159{
160 char str[32];
Daniel Gorsulowskia3802792009-09-29 08:03:12 +0200161 u_char hw_type; /* hardware type */
Daniel Gorsulowski33b1d3f2009-06-30 21:03:37 +0200162
Daniel Gorsulowskia3802792009-09-29 08:03:12 +0200163 /* read the "Type" register of the ET1100 controller */
164 hw_type = readb(CONFIG_ET1100_BASE);
165
166 switch (hw_type) {
167 case 0x11:
168 case 0x3F:
169 /* ET1100 present, arch number of MEESC-Board */
170 gd->bd->bi_arch_number = MACH_TYPE_MEESC;
171 puts("Board: CAN-EtherCAT Gateway");
172 break;
173 case 0xFF:
174 /* no ET1100 present, arch number of EtherCAN/2-Board */
175 gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
176 puts("Board: EtherCAN/2 Gateway");
177 /* switch on LED1D */
178 at91_set_gpio_output(AT91_PIN_PB12, 1);
179 break;
180 default:
181 /* assume, no ET1100 present, arch number of EtherCAN/2-Board */
182 gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
183 printf("ERROR! Read invalid hw_type: %02X\n", hw_type);
184 puts("Board: EtherCAN/2 Gateway");
185 break;
186 }
Daniel Gorsulowski33b1d3f2009-06-30 21:03:37 +0200187 if (getenv_r("serial#", str, sizeof(str)) > 0) {
188 puts(", serial# ");
189 puts(str);
190 }
191 printf("\nHardware-revision: 1.%d\n", get_hw_rev());
192 printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
193 return 0;
194}
195
Daniel Gorsulowskia3802792009-09-29 08:03:12 +0200196#ifdef CONFIG_SERIAL_TAG
197void get_board_serial(struct tag_serialnr *serialnr)
198{
199 char *str;
200
201 char *serial = getenv("serial#");
202 if (serial) {
203 str = strchr(serial, '_');
204 if (str && (strlen(str) >= 4)) {
205 serialnr->high = (*(str + 1) << 8) | *(str + 2);
206 serialnr->low = simple_strtoul(str + 3, NULL, 16);
207 }
208 } else {
209 serialnr->high = 0;
210 serialnr->low = 0;
211 }
212}
213#endif
214
215#ifdef CONFIG_REVISION_TAG
216u32 get_board_rev(void)
217{
218 return hw_rev | 0x100;
219}
220#endif
221
Daniel Gorsulowskia3f38972010-01-20 08:00:11 +0100222#ifdef CONFIG_MISC_INIT_R
223int misc_init_r(void)
224{
225 char *str;
226 char buf[32];
227
228 /*
229 * Normally the processor clock has a divisor of 2.
230 * In some cases this this needs to be set to 4.
231 * Check the user has set environment mdiv to 4 to change the divisor.
232 */
233 if ((str = getenv("mdiv")) && (strcmp(str, "4") == 0)) {
234 at91_sys_write(AT91_PMC_MCKR,
235 (at91_sys_read(AT91_PMC_MCKR) & ~AT91_PMC_MDIV) |
236 AT91SAM9_PMC_MDIV_4);
237 at91_clock_init(0);
238 serial_setbrg();
239 /* Notify the user that the clock is not default */
240 printf("Setting master clock to %s MHz\n",
241 strmhz(buf, get_mck_clk_rate()));
242 }
243
244 return 0;
245}
246#endif /* CONFIG_MISC_INIT_R */
247
Daniel Gorsulowski33b1d3f2009-06-30 21:03:37 +0200248int board_init(void)
249{
250 /* Peripheral Clock Enable Register */
251 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA |
252 1 << AT91SAM9263_ID_PIOB |
253 1 << AT91SAM9263_ID_PIOCDE);
254
Daniel Gorsulowskia3802792009-09-29 08:03:12 +0200255 /* initialize ET1100 Controller */
256 meesc_ethercat_hw_init();
Daniel Gorsulowski33b1d3f2009-06-30 21:03:37 +0200257
258 /* adress of boot parameters */
259 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
260
261 at91_serial_hw_init();
262#ifdef CONFIG_CMD_NAND
263 meesc_nand_hw_init();
264#endif
Daniel Gorsulowski33b1d3f2009-06-30 21:03:37 +0200265#ifdef CONFIG_HAS_DATAFLASH
266 at91_spi0_hw_init(1 << 0);
267#endif
268#ifdef CONFIG_MACB
269 meesc_macb_hw_init();
270#endif
271#ifdef CONFIG_AT91_CAN
272 at91_can_hw_init();
273#endif
274 return 0;
275}