| Michael Walle | 4ceb5c6 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_TARGET_SL28=y |
| 3 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 4 | CONFIG_SPL_LIBGENERIC_SUPPORT=y |
| 5 | CONFIG_SYS_MALLOC_F_LEN=0x4000 |
| 6 | CONFIG_NR_DRAM_BANKS=2 |
| 7 | CONFIG_ENV_SIZE=0x2000 |
| 8 | CONFIG_ENV_OFFSET=0x3e0000 |
| 9 | CONFIG_ENV_SECT_SIZE=0x10000 |
| Tom Rini | 7cfbba3 | 2021-08-28 21:34:49 -0400 | [diff] [blame] | 10 | CONFIG_SYS_MALLOC_LEN=0x202000 |
| Tom Rini | 2bba780 | 2021-06-28 10:17:29 -0400 | [diff] [blame] | 11 | CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-kontron-sl28" |
| Michael Walle | 4ceb5c6 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 12 | CONFIG_SPL_TEXT_BASE=0x18010000 |
| 13 | CONFIG_SYS_FSL_SDHC_CLK_DIV=1 |
| Simon Glass | 2a73606 | 2021-08-08 12:20:12 -0600 | [diff] [blame] | 14 | CONFIG_SPL_SERIAL=y |
| Michael Walle | 4ceb5c6 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 15 | CONFIG_SPL_SIZE_LIMIT=0x20000 |
| 16 | CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x0 |
| 17 | CONFIG_SPL=y |
| 18 | CONFIG_ENV_OFFSET_REDUND=0x3f0000 |
| 19 | CONFIG_SPL_SPI_FLASH_SUPPORT=y |
| Simon Glass | ea2ca7e | 2021-08-08 12:20:14 -0600 | [diff] [blame] | 20 | CONFIG_SPL_SPI=y |
| Michael Walle | 4ceb5c6 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 21 | # CONFIG_PSCI_RESET is not set |
| Michael Walle | 4ceb5c6 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 22 | CONFIG_AHCI=y |
| 23 | CONFIG_DISTRO_DEFAULTS=y |
| Tom Rini | 49c8ef0 | 2021-08-23 10:25:31 -0400 | [diff] [blame] | 24 | CONFIG_SYS_LOAD_ADDR=0x82000000 |
| Michael Walle | 4ceb5c6 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 25 | CONFIG_FIT=y |
| 26 | CONFIG_SPL_LOAD_FIT=y |
| 27 | # CONFIG_USE_SPL_FIT_GENERATOR is not set |
| 28 | CONFIG_OF_BOARD_SETUP=y |
| 29 | CONFIG_OF_STDOUT_VIA_ALIAS=y |
| 30 | CONFIG_BOOTDELAY=10 |
| 31 | CONFIG_USE_BOOTARGS=y |
| 32 | CONFIG_BOARD_LATE_INIT=y |
| 33 | CONFIG_PCI_INIT_R=y |
| 34 | CONFIG_SPL_BOARD_INIT=y |
| 35 | CONFIG_SPL_SEPARATE_BSS=y |
| Simon Glass | 6f004ad | 2021-08-08 12:20:16 -0600 | [diff] [blame^] | 36 | CONFIG_SPL_MPC8XXX_INIT_DDR=y |
| Michael Walle | 4ceb5c6 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 37 | CONFIG_SPL_SPI_LOAD=y |
| Tom Rini | 3e5b62f | 2021-08-10 15:08:46 -0400 | [diff] [blame] | 38 | CONFIG_SYS_SPI_U_BOOT_OFFS=0x230000 |
| Michael Walle | 4ceb5c6 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 39 | CONFIG_CMD_ASKENV=y |
| 40 | CONFIG_CMD_GREPENV=y |
| 41 | CONFIG_CMD_NVEDIT_EFI=y |
| 42 | CONFIG_CMD_DM=y |
| 43 | CONFIG_CMD_GPT=y |
| 44 | CONFIG_CMD_I2C=y |
| 45 | CONFIG_CMD_MMC=y |
| 46 | CONFIG_CMD_PCI=y |
| 47 | CONFIG_CMD_USB=y |
| 48 | CONFIG_CMD_CACHE=y |
| 49 | CONFIG_CMD_EFIDEBUG=y |
| 50 | CONFIG_CMD_RNG=y |
| 51 | CONFIG_MP=y |
| 52 | CONFIG_OF_CONTROL=y |
| 53 | CONFIG_SPL_OF_CONTROL=y |
| 54 | CONFIG_OF_LIST="" |
| 55 | CONFIG_ENV_OVERWRITE=y |
| 56 | CONFIG_ENV_IS_IN_SPI_FLASH=y |
| 57 | CONFIG_SYS_REDUNDAND_ENVIRONMENT=y |
| 58 | CONFIG_NET_RANDOM_ETHADDR=y |
| 59 | CONFIG_NETCONSOLE=y |
| Michael Walle | 4ceb5c6 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 60 | CONFIG_SPL_DM_SEQ_ALIAS=y |
| 61 | CONFIG_SCSI_AHCI=y |
| Michael Walle | 805b242 | 2021-01-08 00:08:59 +0100 | [diff] [blame] | 62 | CONFIG_SATA_CEVA=y |
| Michael Walle | 4ceb5c6 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 63 | CONFIG_FSL_CAAM=y |
| 64 | CONFIG_SYS_FSL_DDR3=y |
| Tom Rini | 9537216 | 2021-08-21 13:50:18 -0400 | [diff] [blame] | 65 | CONFIG_DDR_ECC=y |
| 66 | CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y |
| Michael Walle | 4ceb5c6 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 67 | CONFIG_I2C_SET_DEFAULT_BUS_NUM=y |
| Michael Walle | 4ceb5c6 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 68 | CONFIG_I2C_MUX=y |
| Michael Walle | 1fc9346 | 2021-03-17 15:01:38 +0100 | [diff] [blame] | 69 | CONFIG_MMC_HS400_SUPPORT=y |
| Michael Walle | 4ceb5c6 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 70 | CONFIG_FSL_ESDHC=y |
| 71 | CONFIG_FSL_ESDHC_SUPPORT_ADMA2=y |
| Michael Walle | 46fdf76 | 2020-12-09 10:53:26 +0100 | [diff] [blame] | 72 | # CONFIG_SPI_FLASH_UNLOCK_ALL is not set |
| Michael Walle | 4ceb5c6 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 73 | CONFIG_SPI_FLASH_WINBOND=y |
| 74 | # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set |
| 75 | CONFIG_PHYLIB=y |
| 76 | CONFIG_PHY_ATHEROS=y |
| Tom Rini | 20ecfbe | 2021-03-02 09:36:23 -0500 | [diff] [blame] | 77 | CONFIG_PHY_FIXED=y |
| Tom Rini | 20ecfbe | 2021-03-02 09:36:23 -0500 | [diff] [blame] | 78 | CONFIG_DM_DSA=y |
| Michael Walle | 4ceb5c6 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 79 | CONFIG_PHY_GIGE=y |
| 80 | CONFIG_E1000=y |
| Alex Marginean | d003434 | 2021-01-25 14:23:57 +0200 | [diff] [blame] | 81 | CONFIG_MSCC_FELIX_SWITCH=y |
| Michael Walle | 4ceb5c6 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 82 | CONFIG_NVME=y |
| 83 | CONFIG_PCI=y |
| Michael Walle | 4ceb5c6 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 84 | CONFIG_PCIE_ECAM_GENERIC=y |
| 85 | CONFIG_PCIE_LAYERSCAPE_RC=y |
| Michael Walle | 4ceb5c6 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 86 | CONFIG_RTC_RV8803=y |
| 87 | CONFIG_SCSI=y |
| Michael Walle | 4ceb5c6 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 88 | CONFIG_SYS_NS16550=y |
| 89 | CONFIG_SPI=y |
| Michael Walle | 4ceb5c6 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 90 | CONFIG_FSL_DSPI=y |
| 91 | CONFIG_NXP_FSPI=y |
| 92 | CONFIG_USB=y |
| Michael Walle | 4ceb5c6 | 2020-10-15 23:08:57 +0200 | [diff] [blame] | 93 | # CONFIG_SPL_DM_USB is not set |
| 94 | CONFIG_USB_XHCI_HCD=y |
| 95 | CONFIG_USB_XHCI_DWC3=y |
| 96 | CONFIG_OF_LIBFDT_ASSUME_MASK=0x0 |
| 97 | CONFIG_OF_LIBFDT_OVERLAY=y |