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wdenk4a9cbbe2002-08-27 09:48:53 +00001/*
wdenkd4ca31c2004-01-02 14:00:00 +00002 * (C) Copyright 2000-2004
wdenk4a9cbbe2002-08-27 09:48:53 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <mpc8xx.h>
26#include <asm/processor.h>
27
Wolfgang Denkd87080b2006-03-31 18:32:53 +020028DECLARE_GLOBAL_DATA_PTR;
29
Wolfgang Denk4d302d62005-08-12 22:32:29 +020030#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) || defined(CFG_MEASURE_CPUCLK) || defined(DEBUG)
wdenkc178d3d2004-01-24 20:25:54 +000031
wdenk4a9cbbe2002-08-27 09:48:53 +000032#define PITC_SHIFT 16
33#define PITR_SHIFT 16
34/* pitc values to time for 58/8192 seconds (about 70.8 milliseconds) */
35#define SPEED_PIT_COUNTS 58
36#define SPEED_PITC ((SPEED_PIT_COUNTS - 1) << PITC_SHIFT)
37#define SPEED_PITC_INIT ((SPEED_PIT_COUNTS + 1) << PITC_SHIFT)
38
wdenk4a9cbbe2002-08-27 09:48:53 +000039/* Access functions for the Machine State Register */
40static __inline__ unsigned long get_msr(void)
41{
42 unsigned long msr;
43
44 asm volatile("mfmsr %0" : "=r" (msr) :);
45 return msr;
46}
47
48static __inline__ void set_msr(unsigned long msr)
49{
50 asm volatile("mtmsr %0" : : "r" (msr));
51}
wdenk4a9cbbe2002-08-27 09:48:53 +000052
53/* ------------------------------------------------------------------------- */
54
55/*
56 * Measure CPU clock speed (core clock GCLK1, GCLK2),
57 * also determine bus clock speed (checking bus divider factor)
58 *
59 * (Approx. GCLK frequency in Hz)
60 *
61 * Initializes timer 2 and PIT, but disables them before return.
62 * [Use timer 2, because MPC823 CPUs mask 0.x do not have timers 3 and 4]
63 *
64 * When measuring the CPU clock against the PIT, we count cpu clocks
65 * for 58/8192 seconds with a prescale divide by 177 for the cpu clock.
66 * These strange values for the timing interval and prescaling are used
67 * because the formula for the CPU clock is:
68 *
wdenka2d18bb2004-02-11 21:35:18 +000069 * CPU clock = count * (177 * (8192 / 58))
wdenk4a9cbbe2002-08-27 09:48:53 +000070 *
wdenka2d18bb2004-02-11 21:35:18 +000071 * = count * 24999.7241
wdenk4a9cbbe2002-08-27 09:48:53 +000072 *
wdenka2d18bb2004-02-11 21:35:18 +000073 * which is very close to
wdenk4a9cbbe2002-08-27 09:48:53 +000074 *
wdenka2d18bb2004-02-11 21:35:18 +000075 * = count * 25000
wdenk4a9cbbe2002-08-27 09:48:53 +000076 *
77 * Since the count gives the CPU clock divided by 25000, we can get
78 * the CPU clock rounded to the nearest 0.1 MHz by
79 *
wdenka2d18bb2004-02-11 21:35:18 +000080 * CPU clock = ((count + 2) / 4) * 100000;
wdenk4a9cbbe2002-08-27 09:48:53 +000081 *
82 * The rounding is important since the measurement is sometimes going
83 * to be high or low by 0.025 MHz, depending on exactly how the clocks
84 * and counters interact. By rounding we get the exact answer for any
85 * CPU clock that is an even multiple of 0.1 MHz.
86 */
87
wdenk2535d602003-07-17 23:16:40 +000088unsigned long measure_gclk(void)
wdenk4a9cbbe2002-08-27 09:48:53 +000089{
wdenk4a9cbbe2002-08-27 09:48:53 +000090 volatile immap_t *immr = (immap_t *) CFG_IMMR;
wdenk4a9cbbe2002-08-27 09:48:53 +000091 volatile cpmtimer8xx_t *timerp = &immr->im_cpmtimer;
92 ulong timer2_val;
93 ulong msr_val;
94
wdenk11142572004-06-06 21:35:06 +000095#ifdef CFG_8XX_XIN
wdenk42d1f032003-10-15 23:53:47 +000096 /* dont use OSCM, only use EXTCLK/512 */
97 immr->im_clkrst.car_sccr |= SCCR_RTSEL | SCCR_RTDIV;
wdenk2535d602003-07-17 23:16:40 +000098#else
wdenk42d1f032003-10-15 23:53:47 +000099 immr->im_clkrst.car_sccr &= ~(SCCR_RTSEL | SCCR_RTDIV);
wdenk2535d602003-07-17 23:16:40 +0000100#endif
101
wdenk4a9cbbe2002-08-27 09:48:53 +0000102 /* Reset + Stop Timer 2, no cascading
103 */
104 timerp->cpmt_tgcr &= ~(TGCR_CAS2 | TGCR_RST2);
105
106 /* Keep stopped, halt in debug mode
107 */
108 timerp->cpmt_tgcr |= (TGCR_FRZ2 | TGCR_STP2);
109
110 /* Timer 2 setup:
111 * Output ref. interrupt disable, int. clock
112 * Prescale by 177. Note that prescaler divides by value + 1
113 * so we must subtract 1 here.
114 */
115 timerp->cpmt_tmr2 = ((177 - 1) << TMR_PS_SHIFT) | TMR_ICLK_IN_GEN;
116
wdenka2d18bb2004-02-11 21:35:18 +0000117 timerp->cpmt_tcn2 = 0; /* reset state */
118 timerp->cpmt_tgcr |= TGCR_RST2; /* enable timer 2 */
wdenk4a9cbbe2002-08-27 09:48:53 +0000119
120 /*
121 * PIT setup:
122 *
wdenk8bde7f72003-06-27 21:31:46 +0000123 * We want to time for SPEED_PITC_COUNTS counts (of 8192 Hz),
124 * so the count value would be SPEED_PITC_COUNTS - 1.
125 * But there would be an uncertainty in the start time of 1/4
126 * count since when we enable the PIT the count is not
127 * synchronized to the 32768 Hz oscillator. The trick here is
128 * to start the count higher and wait until the PIT count
129 * changes to the required value before starting timer 2.
wdenk4a9cbbe2002-08-27 09:48:53 +0000130 *
wdenk8bde7f72003-06-27 21:31:46 +0000131 * One count high should be enough, but occasionally the start
132 * is off by 1 or 2 counts of 32768 Hz. With the start value
133 * set two counts high it seems very reliable.
134 */
wdenk4a9cbbe2002-08-27 09:48:53 +0000135
136 immr->im_sitk.sitk_pitck = KAPWR_KEY; /* PIT initialization */
137 immr->im_sit.sit_pitc = SPEED_PITC_INIT;
138
139 immr->im_sitk.sitk_piscrk = KAPWR_KEY;
140 immr->im_sit.sit_piscr = CFG_PISCR;
141
142 /*
143 * Start measurement - disable interrupts, just in case
144 */
145 msr_val = get_msr ();
146 set_msr (msr_val & ~MSR_EE);
147
148 immr->im_sit.sit_piscr |= PISCR_PTE;
149
150 /* spin until get exact count when we want to start */
151 while (immr->im_sit.sit_pitr > SPEED_PITC);
152
wdenka2d18bb2004-02-11 21:35:18 +0000153 timerp->cpmt_tgcr &= ~TGCR_STP2; /* Start Timer 2 */
wdenk4a9cbbe2002-08-27 09:48:53 +0000154 while ((immr->im_sit.sit_piscr & PISCR_PS) == 0);
wdenka2d18bb2004-02-11 21:35:18 +0000155 timerp->cpmt_tgcr |= TGCR_STP2; /* Stop Timer 2 */
wdenk4a9cbbe2002-08-27 09:48:53 +0000156
157 /* re-enable external interrupts if they were on */
158 set_msr (msr_val);
159
160 /* Disable timer and PIT
161 */
162 timer2_val = timerp->cpmt_tcn2; /* save before reset timer */
163
164 timerp->cpmt_tgcr &= ~(TGCR_RST2 | TGCR_FRZ2 | TGCR_STP2);
165 immr->im_sit.sit_piscr &= ~PISCR_PTE;
166
wdenk11142572004-06-06 21:35:06 +0000167#if defined(CFG_8XX_XIN)
wdenk42d1f032003-10-15 23:53:47 +0000168 /* not using OSCM, using XIN, so scale appropriately */
wdenk2535d602003-07-17 23:16:40 +0000169 return (((timer2_val + 2) / 4) * (CFG_8XX_XIN/512))/8192 * 100000L;
170#else
wdenka2d18bb2004-02-11 21:35:18 +0000171 return ((timer2_val + 2) / 4) * 100000L; /* convert to Hz */
wdenk2535d602003-07-17 23:16:40 +0000172#endif
173}
wdenk4a9cbbe2002-08-27 09:48:53 +0000174
wdenk75d1ea72004-01-31 20:06:54 +0000175#endif
176
wdenk66ca92a2004-09-28 17:59:53 +0000177#if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
wdenk75d1ea72004-01-31 20:06:54 +0000178
wdenk2535d602003-07-17 23:16:40 +0000179/*
180 * get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ
181 * or (if it is not defined) measure_gclk() (which uses the ref clock)
182 * from above.
183 */
184int get_clocks (void)
185{
wdenk11142572004-06-06 21:35:06 +0000186 uint immr = get_immr (0); /* Return full IMMR contents */
187 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
188 uint sccr = immap->im_clkrst.car_sccr;
wdenk4a9cbbe2002-08-27 09:48:53 +0000189 /*
wdenk8bde7f72003-06-27 21:31:46 +0000190 * If for some reason measuring the gclk frequency won't
191 * work, we return the hardwired value.
192 * (For example, the cogent CMA286-60 CPU module has no
193 * separate oscillator for PITRTCLK)
wdenk4a9cbbe2002-08-27 09:48:53 +0000194 */
wdenk11142572004-06-06 21:35:06 +0000195#if defined(CONFIG_8xx_GCLK_FREQ)
wdenk4a9cbbe2002-08-27 09:48:53 +0000196 gd->cpu_clk = CONFIG_8xx_GCLK_FREQ;
wdenk11142572004-06-06 21:35:06 +0000197#elif defined(CONFIG_8xx_OSCLK)
198#define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
199 uint pll = immap->im_clkrst.car_plprcr;
200 uint clk;
wdenk4a9cbbe2002-08-27 09:48:53 +0000201
wdenk11142572004-06-06 21:35:06 +0000202 if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */
203 clk = ((CONFIG_8xx_OSCLK / (PLPRCR_val(PDF)+1)) *
204 (PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD)+1))) /
205 (1<<PLPRCR_val(S));
206 } else {
207 clk = CONFIG_8xx_OSCLK * (PLPRCR_val(MF)+1);
208 }
209 if (pll & PLPRCR_CSRC) { /* Low frequency division factor is used */
210 gd->cpu_clk = clk / (2 << ((sccr >> 8) & 7));
211 } else { /* High frequency division factor is used */
212 gd->cpu_clk = clk / (1 << ((sccr >> 5) & 7));
213 }
214#else
215 gd->cpu_clk = measure_gclk();
wdenk4a9cbbe2002-08-27 09:48:53 +0000216#endif /* CONFIG_8xx_GCLK_FREQ */
217
wdenk11142572004-06-06 21:35:06 +0000218 if ((sccr & SCCR_EBDF11) == 0) {
wdenk4a9cbbe2002-08-27 09:48:53 +0000219 /* No Bus Divider active */
220 gd->bus_clk = gd->cpu_clk;
221 } else {
222 /* The MPC8xx has only one BDF: half clock speed */
223 gd->bus_clk = gd->cpu_clk / 2;
224 }
225
226 return (0);
227}
228
wdenk66ca92a2004-09-28 17:59:53 +0000229#else /* CONFIG_8xx_CPUCLK_DEFAULT defined, use dynamic clock setting */
wdenkc178d3d2004-01-24 20:25:54 +0000230
231static long init_pll_866 (long clk);
232
233/* This function sets up PLL (init_pll_866() is called) and
234 * fills gd->cpu_clk and gd->bus_clk according to the environment
wdenk66ca92a2004-09-28 17:59:53 +0000235 * variable 'cpuclk' or to CONFIG_8xx_CPUCLK_DEFAULT (if 'cpuclk'
wdenkc178d3d2004-01-24 20:25:54 +0000236 * contains invalid value).
wdenk66ca92a2004-09-28 17:59:53 +0000237 * This functions requires an MPC866 or newer series CPU.
wdenkc178d3d2004-01-24 20:25:54 +0000238 */
239int get_clocks_866 (void)
240{
wdenkc178d3d2004-01-24 20:25:54 +0000241 volatile immap_t *immr = (immap_t *) CFG_IMMR;
wdenka2d18bb2004-02-11 21:35:18 +0000242 char tmp[64];
243 long cpuclk = 0;
244 long sccr_reg;
wdenkc178d3d2004-01-24 20:25:54 +0000245
246 if (getenv_r ("cpuclk", tmp, sizeof (tmp)) > 0)
247 cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000;
248
wdenk66ca92a2004-09-28 17:59:53 +0000249 if ((CFG_8xx_CPUCLK_MIN > cpuclk) || (CFG_8xx_CPUCLK_MAX < cpuclk))
250 cpuclk = CONFIG_8xx_CPUCLK_DEFAULT;
wdenkc178d3d2004-01-24 20:25:54 +0000251
252 gd->cpu_clk = init_pll_866 (cpuclk);
wdenk75d1ea72004-01-31 20:06:54 +0000253#if defined(CFG_MEASURE_CPUCLK)
254 gd->cpu_clk = measure_gclk ();
255#endif
wdenkc178d3d2004-01-24 20:25:54 +0000256
wdenka2d18bb2004-02-11 21:35:18 +0000257 /* if cpu clock <= 66 MHz then set bus division factor to 1,
258 * otherwise set it to 2
259 */
260 sccr_reg = immr->im_clkrst.car_sccr;
261 sccr_reg &= ~SCCR_EBDF11;
Jens Gehrlein22d1a562007-09-26 17:55:54 +0200262
wdenka2d18bb2004-02-11 21:35:18 +0000263 if (gd->cpu_clk <= 66000000) {
264 sccr_reg |= SCCR_EBDF00; /* bus division factor = 1 */
wdenkc178d3d2004-01-24 20:25:54 +0000265 gd->bus_clk = gd->cpu_clk;
wdenka2d18bb2004-02-11 21:35:18 +0000266 } else {
267 sccr_reg |= SCCR_EBDF01; /* bus division factor = 2 */
wdenkc178d3d2004-01-24 20:25:54 +0000268 gd->bus_clk = gd->cpu_clk / 2;
wdenka2d18bb2004-02-11 21:35:18 +0000269 }
270 immr->im_clkrst.car_sccr = sccr_reg;
wdenkc178d3d2004-01-24 20:25:54 +0000271
272 return (0);
273}
274
275/* Adjust sdram refresh rate to actual CPU clock.
276 */
277int sdram_adjust_866 (void)
278{
wdenkc178d3d2004-01-24 20:25:54 +0000279 volatile immap_t *immr = (immap_t *) CFG_IMMR;
wdenka2d18bb2004-02-11 21:35:18 +0000280 long mamr;
wdenkc178d3d2004-01-24 20:25:54 +0000281
282 mamr = immr->im_memctl.memc_mamr;
283 mamr &= ~MAMR_PTA_MSK;
wdenk66ca92a2004-09-28 17:59:53 +0000284 mamr |= ((gd->cpu_clk / CFG_PTA_PER_CLK) << MAMR_PTA_SHIFT);
wdenkc178d3d2004-01-24 20:25:54 +0000285 immr->im_memctl.memc_mamr = mamr;
286
287 return (0);
288}
289
wdenk66ca92a2004-09-28 17:59:53 +0000290/* Configure PLL for MPC866/859/885 CPU series
wdenkc178d3d2004-01-24 20:25:54 +0000291 * PLL multiplication factor is set to the value nearest to the desired clk,
292 * assuming a oscclk of 10 MHz.
293 */
294static long init_pll_866 (long clk)
295{
296 extern void plprcr_write_866 (long);
297
298 volatile immap_t *immr = (immap_t *) CFG_IMMR;
wdenka2d18bb2004-02-11 21:35:18 +0000299 long n, plprcr;
300 char mfi, mfn, mfd, s, pdf;
301 long step_mfi, step_mfn;
wdenkc178d3d2004-01-24 20:25:54 +0000302
wdenk75d1ea72004-01-31 20:06:54 +0000303 if (clk < 20000000) {
304 clk *= 2;
305 pdf = 1;
306 } else {
307 pdf = 0;
308 }
309
310 if (clk < 40000000) {
311 s = 2;
wdenk66ca92a2004-09-28 17:59:53 +0000312 step_mfi = CONFIG_8xx_OSCLK / 4;
wdenk75d1ea72004-01-31 20:06:54 +0000313 mfd = 7;
wdenk66ca92a2004-09-28 17:59:53 +0000314 step_mfn = CONFIG_8xx_OSCLK / 30;
wdenk75d1ea72004-01-31 20:06:54 +0000315 } else if (clk < 80000000) {
wdenkc178d3d2004-01-24 20:25:54 +0000316 s = 1;
wdenk66ca92a2004-09-28 17:59:53 +0000317 step_mfi = CONFIG_8xx_OSCLK / 2;
wdenkc178d3d2004-01-24 20:25:54 +0000318 mfd = 14;
wdenk66ca92a2004-09-28 17:59:53 +0000319 step_mfn = CONFIG_8xx_OSCLK / 30;
wdenkc178d3d2004-01-24 20:25:54 +0000320 } else {
321 s = 0;
wdenk66ca92a2004-09-28 17:59:53 +0000322 step_mfi = CONFIG_8xx_OSCLK;
wdenkc178d3d2004-01-24 20:25:54 +0000323 mfd = 29;
wdenk66ca92a2004-09-28 17:59:53 +0000324 step_mfn = CONFIG_8xx_OSCLK / 30;
wdenkc178d3d2004-01-24 20:25:54 +0000325 }
326
327 /* Calculate integer part of multiplication factor
328 */
329 n = clk / step_mfi;
330 mfi = (char)n;
331
332 /* Calculate numerator of fractional part of multiplication factor
333 */
334 n = clk - (n * step_mfi);
335 mfn = (char)(n / step_mfn);
336
337 /* Calculate effective clk
338 */
wdenk75d1ea72004-01-31 20:06:54 +0000339 n = ((mfi * step_mfi) + (mfn * step_mfn)) / (pdf + 1);
wdenkc178d3d2004-01-24 20:25:54 +0000340
341 immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
342
343 plprcr = (immr->im_clkrst.car_plprcr & ~(PLPRCR_MFN_MSK
344 | PLPRCR_MFD_MSK | PLPRCR_S_MSK
wdenk75d1ea72004-01-31 20:06:54 +0000345 | PLPRCR_MFI_MSK | PLPRCR_DBRMO
346 | PLPRCR_PDF_MSK))
wdenkc178d3d2004-01-24 20:25:54 +0000347 | (mfn << PLPRCR_MFN_SHIFT)
348 | (mfd << PLPRCR_MFD_SHIFT)
349 | (s << PLPRCR_S_SHIFT)
350 | (mfi << PLPRCR_MFI_SHIFT)
351 | (pdf << PLPRCR_PDF_SHIFT);
352
353 if( (mfn > 0) && ((mfd / mfn) > 10) )
354 plprcr |= PLPRCR_DBRMO;
355
356 plprcr_write_866 (plprcr); /* set value using SIU4/9 workaround */
357 immr->im_clkrstk.cark_plprcrk = 0x00000000;
358
359 return (n);
360}
361
wdenk66ca92a2004-09-28 17:59:53 +0000362#endif /* CONFIG_8xx_CPUCLK_DEFAULT */
wdenkc178d3d2004-01-24 20:25:54 +0000363
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200364#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
365 && !defined(CONFIG_TQM885D)
wdenke9132ea2004-04-24 23:23:30 +0000366/*
367 * Adjust sdram refresh rate to actual CPU clock
368 * and set timebase source according to actual CPU clock
369 */
370int adjust_sdram_tbs_8xx (void)
371{
wdenke9132ea2004-04-24 23:23:30 +0000372 volatile immap_t *immr = (immap_t *) CFG_IMMR;
373 long mamr;
374 long sccr;
375
376 mamr = immr->im_memctl.memc_mamr;
377 mamr &= ~MAMR_PTA_MSK;
378 mamr |= ((gd->cpu_clk / CFG_PTA_PER_CLK) << MAMR_PTA_SHIFT);
379 immr->im_memctl.memc_mamr = mamr;
380
381 if (gd->cpu_clk < 67000000) {
382 sccr = immr->im_clkrst.car_sccr;
383 sccr |= SCCR_TBS;
384 immr->im_clkrst.car_sccr = sccr;
385 }
386
387 return (0);
388}
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200389#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */
wdenke9132ea2004-04-24 23:23:30 +0000390
wdenk4a9cbbe2002-08-27 09:48:53 +0000391/* ------------------------------------------------------------------------- */