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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405GP 1 /* This is a PPC405 CPU */
37#define CONFIG_4xx 1 /* ...member of PPC4xx family */
38#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
39#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
40
41#define CONFIG_BOARD_PRE_INIT 1 /* call board_pre_init() */
42
43#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
44
45#define CONFIG_BAUDRATE 9600
46#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
47
48#if 0
49#define CONFIG_PREBOOT \
50 "crc32 f0207004 ffc 0;" \
51 "if cmp 0 f0207000 1;" \
52 "then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;" \
53 "else;echo Old CRC is bad;fi"
54#endif
55
56#undef CONFIG_BOOTARGS
57#define CONFIG_RAMBOOTCOMMAND \
58 "setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) " \
59 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
60 "bootm ffc00000 ffca0000"
61#define CONFIG_NFSBOOTCOMMAND \
62 "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
63 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
64 "bootm ffc00000"
65#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
66
67#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
68#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
69
70#define CONFIG_MII 1 /* MII PHY management */
71#define CONFIG_PHY_ADDR 0 /* PHY address */
72
73#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
74
75#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
76 CFG_CMD_PCI | \
77 CFG_CMD_IRQ | \
78 CFG_CMD_IDE | \
79 CFG_CMD_ELF | \
80 CFG_CMD_DATE | \
81 CFG_CMD_JFFS2 | \
82 CFG_CMD_I2C | \
stroesead10dd92003-02-14 11:21:23 +000083 CFG_CMD_MII | \
wdenkc6097192002-11-03 00:24:07 +000084 CFG_CMD_EEPROM )
85
86#define CONFIG_MAC_PARTITION
87#define CONFIG_DOS_PARTITION
88
89/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
90#include <cmd_confdefs.h>
91
92#undef CONFIG_WATCHDOG /* watchdog disabled */
93
94#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
95
96/*
97 * Miscellaneous configurable options
98 */
99#define CFG_LONGHELP /* undef to save memory */
100#define CFG_PROMPT "=> " /* Monitor Command Prompt */
101
102#undef CFG_HUSH_PARSER /* use "hush" command parser */
103#ifdef CFG_HUSH_PARSER
104#define CFG_PROMPT_HUSH_PS2 "> "
105#endif
106
107#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
108#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
109#else
110#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
111#endif
112#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
113#define CFG_MAXARGS 16 /* max number of command args */
114#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
115
116#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
117
118#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
119
120#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
121#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
122
123#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
124#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
125#define CFG_BASE_BAUD 691200
126
127/* The following table includes the supported baudrates */
128#define CFG_BAUDRATE_TABLE \
129 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
130 57600, 115200, 230400, 460800, 921600 }
131
132#define CFG_LOAD_ADDR 0x100000 /* default load address */
133#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
134
135#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
136
137#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
138
139/*-----------------------------------------------------------------------
140 * PCI stuff
141 *-----------------------------------------------------------------------
142 */
143#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
144#define PCI_HOST_FORCE 1 /* configure as pci host */
145#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
146
147#define CONFIG_PCI /* include pci support */
148#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
149#define CONFIG_PCI_PNP /* do pci plug-and-play */
150 /* resource configuration */
151
152#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
153
stroesead10dd92003-02-14 11:21:23 +0000154#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
155
wdenkc6097192002-11-03 00:24:07 +0000156#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
157#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
158#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
159#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
160#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
161#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
162#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
163#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
164#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
165#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
166
167/*-----------------------------------------------------------------------
168 * IDE/ATA stuff
169 *-----------------------------------------------------------------------
170 */
171#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
172#undef CONFIG_IDE_LED /* no led for ide supported */
173#define CONFIG_IDE_RESET 1 /* reset for ide supported */
174
175#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
176#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
177
178#define CFG_ATA_BASE_ADDR 0xF0100000
179#define CFG_ATA_IDE0_OFFSET 0x0000
180
181#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
182#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
183#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
184
185/*-----------------------------------------------------------------------
186 * Start addresses for the final memory configuration
187 * (Set up by the startup code)
188 * Please note that CFG_SDRAM_BASE _must_ start at 0
189 */
190#define CFG_SDRAM_BASE 0x00000000
191#define CFG_FLASH_BASE 0xFFFC0000
192#define CFG_MONITOR_BASE CFG_FLASH_BASE
193#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
194#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
195
196/*
197 * For booting Linux, the board info and command line data
198 * have to be in the first 8 MB of memory, since this is
199 * the maximum mapped by the Linux kernel during initialization.
200 */
201#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
202/*-----------------------------------------------------------------------
203 * FLASH organization
204 */
205#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
206#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
207
208#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
209#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
210
211#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
212#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
213#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
214/*
215 * The following defines are added for buggy IOP480 byte interface.
216 * All other boards should use the standard values (CPCI405 etc.)
217 */
218#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
219#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
220#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
221
222#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
223
224#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
225#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
226
227#if 0 /* Use NVRAM for environment variables */
228/*-----------------------------------------------------------------------
229 * NVRAM organization
230 */
231#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
232#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
233#define CFG_ENV_ADDR \
234 (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8)) /* Env */
235
236#else /* Use EEPROM for environment variables */
237
238#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
239#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
240#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
241 /* total size of a CAT24WC16 is 2048 bytes */
242#endif
243
244#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
245#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */
246#define CFG_NVRAM_VXWORKS_OFFS 0x6900 /* Offset for VxWorks eth-addr */
247
248/*-----------------------------------------------------------------------
249 * I2C EEPROM (CAT24WC16) for environment
250 */
251#define CONFIG_HARD_I2C /* I2c with hardware support */
252#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
253#define CFG_I2C_SLAVE 0x7F
254
255#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
256#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
257/* mask of address bits that overflow into the "EEPROM chip address" */
258#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
259#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
260 /* 16 byte page write mode using*/
261 /* last 4 bits of the address */
262#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
263#define CFG_EEPROM_PAGE_WRITE_ENABLE
264
265/*-----------------------------------------------------------------------
266 * Cache Configuration
267 */
268#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
269 /* have only 8kB, 16kB is save here */
270#define CFG_CACHELINE_SIZE 32 /* ... */
271#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
272#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
273#endif
274
275/*
276 * Init Memory Controller:
277 *
278 * BR0/1 and OR0/1 (FLASH)
279 */
280
281#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
282#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
283
284/*-----------------------------------------------------------------------
285 * External Bus Controller (EBC) Setup
286 */
287
288/* Memory Bank 0 (Flash Bank 0) initialization */
289#define CFG_EBC_PB0AP 0x92015480
290#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
291
292/* Memory Bank 1 (Flash Bank 1) initialization */
293#define CFG_EBC_PB1AP 0x92015480
294#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
295
296/* Memory Bank 2 (CAN0, 1) initialization */
297#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
298#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
stroese6f4474e2003-03-20 15:31:19 +0000299#define CFG_LED_ADDR 0xF0000380
wdenkc6097192002-11-03 00:24:07 +0000300
301/* Memory Bank 3 (CompactFlash IDE) initialization */
302#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
303#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
304
305/* Memory Bank 4 (NVRAM/RTC) initialization */
stroese6f4474e2003-03-20 15:31:19 +0000306//#define CFG_EBC_PB4AP 0x01805280 /* TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */
307#define CFG_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */
wdenkc6097192002-11-03 00:24:07 +0000308#define CFG_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
309
310/* Memory Bank 5 (optional Quart) initialization */
311#define CFG_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
312#define CFG_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
313
314/* Memory Bank 6 (FPGA internal) initialization */
315#define CFG_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
316#define CFG_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
317#define CFG_FPGA_BASE_ADDR 0xF0400000
318
319/*-----------------------------------------------------------------------
320 * FPGA stuff
321 */
322/* FPGA internal regs */
323#define CFG_FPGA_MODE 0x00
324#define CFG_FPGA_STATUS 0x02
325#define CFG_FPGA_TS 0x04
326#define CFG_FPGA_TS_LOW 0x06
327#define CFG_FPGA_TS_CAP0 0x10
328#define CFG_FPGA_TS_CAP0_LOW 0x12
329#define CFG_FPGA_TS_CAP1 0x14
330#define CFG_FPGA_TS_CAP1_LOW 0x16
331#define CFG_FPGA_TS_CAP2 0x18
332#define CFG_FPGA_TS_CAP2_LOW 0x1a
333#define CFG_FPGA_TS_CAP3 0x1c
334#define CFG_FPGA_TS_CAP3_LOW 0x1e
335
336/* FPGA Mode Reg */
stroese6f4474e2003-03-20 15:31:19 +0000337#define CFG_FPGA_MODE_CF_RESET 0x0001
338#define CFG_FPGA_MODE_DUART_RESET 0x0002
339#define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */
wdenkc6097192002-11-03 00:24:07 +0000340#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
341#define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000
stroese6f4474e2003-03-20 15:31:19 +0000342#define CFG_FPGA_MODE_TS_CLEAR 0x2000
wdenkc6097192002-11-03 00:24:07 +0000343
344/* FPGA Status Reg */
345#define CFG_FPGA_STATUS_DIP0 0x0001
346#define CFG_FPGA_STATUS_DIP1 0x0002
347#define CFG_FPGA_STATUS_DIP2 0x0004
348#define CFG_FPGA_STATUS_FLASH 0x0008
349#define CFG_FPGA_STATUS_TS_IRQ 0x1000
350
351#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
352#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */
353
354/* FPGA program pin configuration */
355#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
356#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
357#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
358#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
359#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
360
361/*-----------------------------------------------------------------------
362 * Definitions for initial stack pointer and data area (in data cache)
363 */
wdenkc6097192002-11-03 00:24:07 +0000364#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
365
366#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */
wdenkc6097192002-11-03 00:24:07 +0000367#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
368#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
369#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
370#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
371
372
373/*
374 * Internal Definitions
375 *
376 * Boot Flags
377 */
378#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
379#define BOOTFLAG_WARM 0x02 /* Software reboot */
380
381#endif /* __CONFIG_H */