blob: a7c927759cd8ff31cf0b3b858e96e4457a6e2cf5 [file] [log] [blame]
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +00001/*
2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +00005 */
6
7/*
8 * BSC9131 RDB board configuration file
9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
harninder rai4aafbb42014-12-02 15:55:47 +053014#define CONFIG_SYS_GENERIC_BOARD
15#define CONFIG_DISPLAY_BOARDINFO
16
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +000017#ifdef CONFIG_BSC9131RDB
18#define CONFIG_BSC9131
19#define CONFIG_NAND_FSL_IFC
20#endif
21
22#ifdef CONFIG_SPIFLASH
23#define CONFIG_RAMBOOT_SPIFLASH
24#define CONFIG_SYS_RAMBOOT
25#define CONFIG_SYS_EXTRA_ENV_RELOC
26#define CONFIG_SYS_TEXT_BASE 0x11000000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053027#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +000028#endif
29
Prabhakar Kushwahaf1593262013-04-16 13:28:25 +053030#ifdef CONFIG_NAND
Prabhakar Kushwahaf1593262013-04-16 13:28:25 +053031#define CONFIG_SPL_INIT_MINIMAL
32#define CONFIG_SPL_SERIAL_SUPPORT
33#define CONFIG_SPL_NAND_SUPPORT
Prabhakar Kushwahafbe76ae2013-12-11 12:42:11 +053034#define CONFIG_SPL_NAND_BOOT
Prabhakar Kushwahaf1593262013-04-16 13:28:25 +053035#define CONFIG_SPL_FLUSH_IMAGE
36#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
37
38#define CONFIG_SYS_TEXT_BASE 0x00201000
39#define CONFIG_SPL_TEXT_BASE 0xFFFFE000
40#define CONFIG_SPL_MAX_SIZE 8192
41#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
42#define CONFIG_SPL_RELOC_STACK 0x00100000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053043#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
Prabhakar Kushwahaf1593262013-04-16 13:28:25 +053044#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
45#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
46#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
47#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +000048#endif
49
Prabhakar Kushwahaf1593262013-04-16 13:28:25 +053050#ifdef CONFIG_SPL_BUILD
51#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
52#else
53#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
54#endif
55
56
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +000057/* High Level Configuration Options */
58#define CONFIG_BOOKE /* BOOKE */
59#define CONFIG_E500 /* BOOKE e500 family */
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +000060#define CONFIG_FSL_IFC /* Enable IFC Support */
Ruchika Gupta737537e2014-10-15 11:35:31 +053061#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +000062
63#define CONFIG_FSL_LAW /* Use common FSL init code */
64#define CONFIG_TSEC_ENET
65#define CONFIG_ENV_OVERWRITE
66
67#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */
Priyanka Jain087cf442013-04-01 12:12:45 +053068#if defined(CONFIG_SYS_CLK_100)
69#define CONFIG_SYS_CLK_FREQ 100000000 /* SYSCLK for 9131 RDB */
70#else
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +000071#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */
Priyanka Jain087cf442013-04-01 12:12:45 +053072#endif
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +000073
74#define CONFIG_HWCONFIG
75/*
76 * These can be toggled for performance analysis, otherwise use default.
77 */
78#define CONFIG_L2_CACHE /* toggle L2 cache */
79#define CONFIG_BTB /* enable branch predition */
80
81#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
82#define CONFIG_SYS_MEMTEST_END 0x01ffffff
83
84/* DDR Setup */
York Sun5614e712013-09-30 09:22:09 -070085#define CONFIG_SYS_FSL_DDR3
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +000086#undef CONFIG_SYS_DDR_RAW_TIMING
87#undef CONFIG_DDR_SPD
88#define CONFIG_SYS_SPD_BUS_NUM 0
89#define SPD_EEPROM_ADDRESS 0x52 /* I2C access */
90
91#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
92
93#ifndef __ASSEMBLY__
94extern unsigned long get_sdram_size(void);
95#endif
96#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
97#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
98#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
99
100#define CONFIG_NUM_DDR_CONTROLLERS 1
101#define CONFIG_DIMM_SLOTS_PER_CTLR 1
102#define CONFIG_CHIP_SELECTS_PER_CTRL 1
103
104#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
105#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
106#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
107
108#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
109#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
110#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
111#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
112
113#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
114#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
115#define CONFIG_SYS_DDR_RCW_1 0x00000000
116#define CONFIG_SYS_DDR_RCW_2 0x00000000
117#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
118#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
119#define CONFIG_SYS_DDR_TIMING_4 0x00000001
120#define CONFIG_SYS_DDR_TIMING_5 0x02401400
121
122#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
123#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
124#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
125#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf
126#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
127#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
128#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
129#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
130#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
131
132/*
133 * Base addresses -- Note these are effective addresses where the
134 * actual resources get mapped (not physical addresses)
135 */
136/* relocated CCSRBAR */
137#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
138#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
139
140#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
141 /* CONFIG_SYS_IMMR */
Priyanka Jain765b0bd2013-04-04 09:31:54 +0530142/* DSP CCSRBAR */
143#define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
144#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000145
146/*
147 * Memory map
148 *
149 * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable
150 * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M
Priyanka Jain765b0bd2013-04-04 09:31:54 +0530151 * 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000152 * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
153 * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K
154 * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K
155 * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
Priyanka Jain765b0bd2013-04-04 09:31:54 +0530156 * 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000157 * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
158 * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M
159 *
160 */
161
162/*
163 * IFC Definitions
164 */
165#define CONFIG_SYS_NO_FLASH
166
167/* NAND Flash on IFC */
168#define CONFIG_SYS_NAND_BASE 0xff800000
169#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
170
171#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
172 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \
173 | CSPR_MSEL_NAND /* MSEL = NAND */ \
174 | CSPR_V)
175#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
176
177#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
178 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
179 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
180 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
181 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
182 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
183 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
184
185/* NAND Flash Timing Params */
Prabhakar Kushwaha4544fd22013-09-10 17:33:12 +0530186#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
187 | FTIM0_NAND_TWP(0x05) \
188 | FTIM0_NAND_TWCHT(0x02) \
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000189 | FTIM0_NAND_TWH(0x04))
Prabhakar Kushwaha4544fd22013-09-10 17:33:12 +0530190#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \
191 | FTIM1_NAND_TWBE(0x1E) \
192 | FTIM1_NAND_TRR(0x07) \
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000193 | FTIM1_NAND_TRP(0x05))
194#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
195 | FTIM2_NAND_TREH(0x04) \
Prabhakar Kushwaha4544fd22013-09-10 17:33:12 +0530196 | FTIM2_NAND_TWHRE(0x11))
197#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000198
199#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
200#define CONFIG_SYS_MAX_NAND_DEVICE 1
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000201#define CONFIG_CMD_NAND
202#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
203
204#define CONFIG_SYS_NAND_DDR_LAW 11
205
206/* Set up IFC registers for boot location NAND */
207#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
208#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
209#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
210#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
211#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
212#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
213#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
214
215#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
216
217#define CONFIG_SYS_INIT_RAM_LOCK
218#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
219#define CONFIG_SYS_INIT_RAM_END 0x00004000/* End of used area in RAM */
220
221#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
222 - GENERATED_GBL_DATA_SIZE)
223#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
224
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530225#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000226#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
227
228/* Serial Port */
229#define CONFIG_CONS_INDEX 1
230#undef CONFIG_SERIAL_SOFTWARE_FIFO
231#define CONFIG_SYS_NS16550
232#define CONFIG_SYS_NS16550_SERIAL
233#define CONFIG_SYS_NS16550_REG_SIZE 1
234#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Prabhakar Kushwahaf1593262013-04-16 13:28:25 +0530235#ifdef CONFIG_SPL_BUILD
236#define CONFIG_NS16550_MIN_FUNCTIONS
237#endif
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000238
239#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
240
241#define CONFIG_SYS_BAUDRATE_TABLE \
242 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
243
244#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
245
246/* Use the HUSH parser */
247#define CONFIG_SYS_HUSH_PARSER
248#ifdef CONFIG_SYS_HUSH_PARSER
249#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
250#endif
251
252/*
253 * Pass open firmware flat tree
254 */
255#define CONFIG_OF_LIBFDT
256#define CONFIG_OF_BOARD_SETUP
257#define CONFIG_OF_STDOUT_VIA_ALIAS
258
259/* new uImage format support */
260#define CONFIG_FIT
261#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
262
Heiko Schocher00f792e2012-10-24 13:48:22 +0200263#define CONFIG_SYS_I2C
264#define CONFIG_SYS_I2C_FSL
265#define CONFIG_SYS_FSL_I2C_SPEED 400000
266#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
267#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000268
269/* I2C EEPROM */
270#define CONFIG_CMD_EEPROM
271#define CONFIG_SYS_I2C_MULTI_EEPROMS
272#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
273#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
274#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
275
276#define CONFIG_CMD_I2C
277
278
279#define CONFIG_FSL_ESPI
280/* eSPI - Enhanced SPI */
281#ifdef CONFIG_FSL_ESPI
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000282#define CONFIG_SPI_FLASH_SPANSION
283#define CONFIG_CMD_SF
284#define CONFIG_SF_DEFAULT_SPEED 10000000
285#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
286#endif
287
288#if defined(CONFIG_TSEC_ENET)
289
290#define CONFIG_MII /* MII PHY management */
291#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
292#define CONFIG_TSEC1 1
293#define CONFIG_TSEC1_NAME "eTSEC1"
294#define CONFIG_TSEC2 1
295#define CONFIG_TSEC2_NAME "eTSEC2"
296
297#define TSEC1_PHY_ADDR 0
298#define TSEC2_PHY_ADDR 3
299
300#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
301#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
302
303#define TSEC1_PHYIDX 0
304
305#define TSEC2_PHYIDX 0
306
307#define CONFIG_ETHPRIME "eTSEC1"
308
309#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
310
311#endif /* CONFIG_TSEC_ENET */
312
313/*
314 * Environment
315 */
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000316#if defined(CONFIG_RAMBOOT_SPIFLASH)
317#define CONFIG_ENV_IS_IN_SPI_FLASH
318#define CONFIG_ENV_SPI_BUS 0
319#define CONFIG_ENV_SPI_CS 0
320#define CONFIG_ENV_SPI_MAX_HZ 10000000
321#define CONFIG_ENV_SPI_MODE 0
322#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
323#define CONFIG_ENV_SECT_SIZE 0x10000
324#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwahaf1593262013-04-16 13:28:25 +0530325#elif defined(CONFIG_NAND)
326#define CONFIG_ENV_IS_IN_NAND
327#define CONFIG_SYS_EXTRA_ENV_RELOC
328#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530329#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
Prabhakar Kushwahaf1593262013-04-16 13:28:25 +0530330#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
331#elif defined(CONFIG_SYS_RAMBOOT)
332#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000333#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Prabhakar Kushwahaf1593262013-04-16 13:28:25 +0530334#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000335#endif
336
337#define CONFIG_LOADS_ECHO /* echo on for serial download */
338#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
339
340/*
341 * Command line configuration.
342 */
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000343#define CONFIG_CMD_DHCP
344#define CONFIG_CMD_ERRATA
345#define CONFIG_CMD_ELF
346#define CONFIG_CMD_EXT2
347#define CONFIG_CMD_FAT
348#define CONFIG_CMD_IRQ
349#define CONFIG_CMD_MII
350#define CONFIG_DOS_PARTITION
351#define CONFIG_CMD_PING
352#define CONFIG_CMD_REGINFO
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000353
354/*
355 * Miscellaneous configurable options
356 */
357#define CONFIG_SYS_LONGHELP /* undef to save memory */
358#define CONFIG_CMDLINE_EDITING /* Command-line editing */
359#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
360#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000361
362#if defined(CONFIG_CMD_KGDB)
363#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
364#else
365#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
366#endif
367#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
368 /* Print Buffer Size */
369#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
370#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000371
372/*
373 * For booting Linux, the board info and command line data
374 * have to be in the first 64 MB of memory, since this is
375 * the maximum mapped by the Linux kernel during initialization.
376 */
377#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
378#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
379
380#if defined(CONFIG_CMD_KGDB)
381#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000382#endif
383
Ruchika Gupta737537e2014-10-15 11:35:31 +0530384/* Hash command with SHA acceleration supported in hardware */
385#ifdef CONFIG_FSL_CAAM
386#define CONFIG_CMD_HASH
387#define CONFIG_SHA_HW_ACCEL
388#endif
389
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000390#define CONFIG_USB_EHCI
391
392#ifdef CONFIG_USB_EHCI
393#define CONFIG_CMD_USB
394#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
395#define CONFIG_USB_EHCI_FSL
396#define CONFIG_USB_STORAGE
397#define CONFIG_HAS_FSL_DR_USB
398#endif
399
400/*
Ashish Kumar7ac1a242014-10-07 18:02:23 +0530401 * Dynamic MTD Partition support with mtdparts
402 */
403#define CONFIG_MTD_DEVICE
404#define CONFIG_MTD_PARTITIONS
405#define CONFIG_CMD_MTDPARTS
406#define MTDIDS_DEFAULT "nand0=ff800000.flash,"
407#define MTDPARTS_DEFAULT "mtdparts=ff800000.flash:1m(uboot)," \
408 "8m(kernel),512k(dtb),-(fs)"
409/*
410 * Override partitions in device tree using info
411 * in "mtdparts" environment variable
412 */
413#ifdef CONFIG_CMD_MTDPARTS
414#define CONFIG_FDT_FIXUP_PARTITIONS
415#endif
416
417/*
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000418 * Environment Configuration
419 */
420
421#if defined(CONFIG_TSEC_ENET)
422#define CONFIG_HAS_ETH0
423#endif
424
425#define CONFIG_HOSTNAME BSC9131rdb
426#define CONFIG_ROOTPATH "/opt/nfsroot"
427#define CONFIG_BOOTFILE "uImage"
428#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
429
430#define CONFIG_BAUDRATE 115200
harninder rai37811ec2014-12-15 12:58:45 +0530431#define CONFIG_BOOTDELAY 10 /* -1 disable auto-boot */
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000432
433#define CONFIG_EXTRA_ENV_SETTINGS \
434 "netdev=eth0\0" \
435 "uboot=" CONFIG_UBOOTPATH "\0" \
436 "loadaddr=1000000\0" \
437 "bootfile=uImage\0" \
438 "consoledev=ttyS0\0" \
439 "ramdiskaddr=2000000\0" \
440 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
441 "fdtaddr=c00000\0" \
442 "fdtfile=bsc9131rdb.dtb\0" \
443 "bdev=sda1\0" \
444 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
Priyanka Jain1d2949a2013-04-04 14:40:32 +0530445 "bootm_size=0x37000000\0" \
446 "othbootargs=ramdisk_size=600000 " \
447 "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000448 "usbext2boot=setenv bootargs root=/dev/ram rw " \
449 "console=$consoledev,$baudrate $othbootargs; " \
450 "usb start;" \
451 "ext2load usb 0:4 $loadaddr $bootfile;" \
452 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
453 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
454 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
455
456#define CONFIG_RAMBOOTCOMMAND \
457 "setenv bootargs root=/dev/ram rw " \
458 "console=$consoledev,$baudrate $othbootargs; " \
459 "tftp $ramdiskaddr $ramdiskfile;" \
460 "tftp $loadaddr $bootfile;" \
461 "tftp $fdtaddr $fdtfile;" \
462 "bootm $loadaddr $ramdiskaddr $fdtaddr"
463
464#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
465
466#endif /* __CONFIG_H */