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Stefan Roese13b4f632012-08-14 15:04:19 +02001/*
Stefan Roese8aa34492013-04-25 23:20:23 +00002 * Copyright 2012-2013 Stefan Roese <sr@denx.de>
Stefan Roese13b4f632012-08-14 15:04:19 +02003 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese13b4f632012-08-14 15:04:19 +02005 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
10/*
11 * High Level Configuration Options
12 * (easy to change)
13 */
14
15#define CONFIG_MPC5200
Masahiro Yamadab2a6dfe2014-01-16 11:03:07 +090016#define CONFIG_A3M071 /* A3M071 board */
Stefan Roesec07e8da2014-11-19 09:37:47 +010017#define CONFIG_DISPLAY_BOARDINFO
18#define CONFIG_SYS_GENERIC_BOARD
Stefan Roese13b4f632012-08-14 15:04:19 +020019
20#define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */
21
Stefan Roesed4451d32013-02-07 02:10:11 +000022#define CONFIG_SPL_TARGET "u-boot-img.bin"
23
Stefan Roese13b4f632012-08-14 15:04:19 +020024#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
25
26#define CONFIG_MISC_INIT_R
27#define CONFIG_SYS_LOWBOOT /* Enable lowboot */
28
Stefan Roesed4451d32013-02-07 02:10:11 +000029#ifdef CONFIG_A4M2K
30#define CONFIG_HOSTNAME a4m2k
31#else
32#define CONFIG_HOSTNAME a3m071
33#endif
34
Stefan Roesed62a89b2013-06-22 16:16:25 +020035#define CONFIG_BOOTCOUNT_LIMIT
36
Stefan Roese13b4f632012-08-14 15:04:19 +020037/*
38 * Serial console configuration
39 */
40#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
41#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
42#define CONFIG_SYS_BAUDRATE_TABLE \
43 { 9600, 19200, 38400, 57600, 115200, 230400 }
44
45/*
46 * Command line configuration.
47 */
Stefan Roese13b4f632012-08-14 15:04:19 +020048#define CONFIG_CMD_BSP
49#define CONFIG_CMD_CACHE
Stefan Roese13b4f632012-08-14 15:04:19 +020050#define CONFIG_CMD_MII
51#define CONFIG_CMD_REGINFO
Stefan Roese8aa34492013-04-25 23:20:23 +000052#define CONFIG_CMD_DHCP
53#define CONFIG_BOOTP_SEND_HOSTNAME
54#define CONFIG_BOOTP_SERVERIP
55#define CONFIG_BOOTP_MAY_FAIL
56#define CONFIG_BOOTP_BOOTPATH
57#define CONFIG_BOOTP_GATEWAY
58#define CONFIG_BOOTP_SERVERIP
59#define CONFIG_NET_RETRY_COUNT 3
60#define CONFIG_CMD_LINK_LOCAL
61#define CONFIG_NETCONSOLE
62#define CONFIG_SYS_CONSOLE_IS_IN_ENV
63#define CONFIG_CMD_PING
64#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
65#define CONFIG_MTD_PARTITIONS /* needed for UBI */
66#define CONFIG_FLASH_CFI_MTD
67#define MTDIDS_DEFAULT "nor0=fc000000.flash"
68#define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:512k(u-boot)," \
Stefan Roesed62a89b2013-06-22 16:16:25 +020069 "128k(env1)," \
70 "128k(env2)," \
Stefan Roese8aa34492013-04-25 23:20:23 +000071 "128k(hwinfo)," \
72 "1M(nvramsim)," \
73 "128k(dtb)," \
74 "5M(kernel)," \
75 "128k(sysinfo)," \
76 "7552k(root)," \
77 "4M(app)," \
Stefan Roesed62a89b2013-06-22 16:16:25 +020078 "5376k(data)," \
79 "8M(install)"
80
Stefan Roese8aa34492013-04-25 23:20:23 +000081#define CONFIG_LZO /* needed for UBI */
82#define CONFIG_RBTREE /* needed for UBI */
83#define CONFIG_CMD_MTDPARTS
84#define CONFIG_CMD_UBI
85#define CONFIG_CMD_UBIFS
86#define CONFIG_FIT
Stefan Roese13b4f632012-08-14 15:04:19 +020087
88/*
89 * IPB Bus clocking configuration.
90 */
91#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
92/* define for 66MHz speed - undef for 33MHz PCI clock speed */
Stefan Roesed4451d32013-02-07 02:10:11 +000093#ifdef CONFIG_A4M2K
94#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
95#else
Stefan Roese13b4f632012-08-14 15:04:19 +020096#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
Stefan Roesed4451d32013-02-07 02:10:11 +000097#endif
Stefan Roese13b4f632012-08-14 15:04:19 +020098
99/* pass open firmware flat tree */
100#define CONFIG_OF_LIBFDT
101#define CONFIG_OF_BOARD_SETUP
102
103/* maximum size of the flat tree (8K) */
104#define OF_FLAT_TREE_MAX_SIZE 8192
105
106#define OF_CPU "PowerPC,5200@0"
107#define OF_SOC "soc5200@f0000000"
108#define OF_TBCLK (bd->bi_busfreq / 4)
109#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
110
111/*
Stefan Roese13b4f632012-08-14 15:04:19 +0200112 * NOR flash configuration
113 */
114#define CONFIG_SYS_FLASH_BASE 0xfc000000
Stefan Roesed4451d32013-02-07 02:10:11 +0000115#define CONFIG_SYS_FLASH_SIZE 0x02000000
Stefan Roese8aa34492013-04-25 23:20:23 +0000116#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000)
Stefan Roese13b4f632012-08-14 15:04:19 +0200117
118#define CONFIG_SYS_MAX_FLASH_BANKS 1
119#define CONFIG_SYS_MAX_FLASH_SECT 256
120#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
121#define CONFIG_SYS_FLASH_WRITE_TOUT 500
122#define CONFIG_SYS_FLASH_LOCK_TOUT 5
123#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000
124#define CONFIG_SYS_FLASH_PROTECTION
125#define CONFIG_FLASH_CFI_DRIVER
126#define CONFIG_SYS_FLASH_CFI
127#define CONFIG_SYS_FLASH_EMPTY_INFO
128#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Stefan Roesef8945512013-04-04 03:55:42 +0000129#define CONFIG_FLASH_VERIFY
Stefan Roese13b4f632012-08-14 15:04:19 +0200130
131/*
132 * Environment settings
133 */
134#define CONFIG_ENV_IS_IN_FLASH
135#define CONFIG_ENV_SIZE 0x10000
136#define CONFIG_ENV_SECT_SIZE 0x20000
137#define CONFIG_ENV_OVERWRITE
Stefan Roese8aa34492013-04-25 23:20:23 +0000138#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
139#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Stefan Roese13b4f632012-08-14 15:04:19 +0200140
141/*
142 * Memory map
143 */
144#define CONFIG_SYS_MBAR 0xf0000000
145#define CONFIG_SYS_SDRAM_BASE 0x00000000
146#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
147
148/* Use SRAM until RAM will be available */
149#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
150#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
151
Stefan Roese13b4f632012-08-14 15:04:19 +0200152#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
Stefan Roese704afcc2013-04-25 23:10:02 +0000153 GENERATED_GBL_DATA_SIZE)
Stefan Roese13b4f632012-08-14 15:04:19 +0200154#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
155
156#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
157
Stefan Roese8aa34492013-04-25 23:20:23 +0000158#define CONFIG_SYS_MONITOR_LEN (512 << 10)
159#define CONFIG_SYS_MALLOC_LEN (4 << 20)
Stefan Roese13b4f632012-08-14 15:04:19 +0200160#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
161
162/*
163 * Ethernet configuration
164 */
165#define CONFIG_MPC5xxx_FEC
166#define CONFIG_MPC5xxx_FEC_MII100
Stefan Roesed4451d32013-02-07 02:10:11 +0000167#ifdef CONFIG_A4M2K
168#define CONFIG_PHY_ADDR 0x01
169#else
Stefan Roese13b4f632012-08-14 15:04:19 +0200170#define CONFIG_PHY_ADDR 0x00
Stefan Roesed4451d32013-02-07 02:10:11 +0000171#endif
Stefan Roese13b4f632012-08-14 15:04:19 +0200172
173/*
174 * GPIO configuration
175 */
176
177/*
178 * GPIO-config depends on failsave-level
179 * failsave 0 means just MPX-config, no digiboard, no fpga
180 * 1 means digiboard ok
181 * 2 means fpga ok
182 */
183
Stefan Roesed4451d32013-02-07 02:10:11 +0000184#ifdef CONFIG_A4M2K
Stefan Roese8aa34492013-04-25 23:20:23 +0000185#define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C805
Stefan Roesed4451d32013-02-07 02:10:11 +0000186#else
Stefan Roese13b4f632012-08-14 15:04:19 +0200187/* for failsave-level 0 - full failsave */
188#define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C005
189/* for failsave-level 1 - only digiboard ok */
Stefan Roese8aa34492013-04-25 23:20:23 +0000190#define CONFIG_SYS_GPS_PORT_CONFIG_1 0x1005C065
Stefan Roese13b4f632012-08-14 15:04:19 +0200191/* for failsave-level 2 - all ok */
Stefan Roese8aa34492013-04-25 23:20:23 +0000192#define CONFIG_SYS_GPS_PORT_CONFIG_2 0x1005C065
Stefan Roesed4451d32013-02-07 02:10:11 +0000193#endif
Stefan Roese13b4f632012-08-14 15:04:19 +0200194
Stefan Roeseaed75482013-02-07 02:10:28 +0000195#define CONFIG_WDOG_GPIO_PIN GPIO_WKUP_7
196#if defined(CONFIG_A4M2K) && !defined(CONFIG_SPL_BUILD)
197#define CONFIG_HW_WATCHDOG /* Use external HW-Watchdog */
198#endif
199
Stefan Roese13b4f632012-08-14 15:04:19 +0200200/*
201 * Configuration matrix
Stefan Roese8aa34492013-04-25 23:20:23 +0000202 * MSB LSB
Stefan Roesed4451d32013-02-07 02:10:11 +0000203 * failsave 0 0x1005C005 00010000000001011100000000000101 ( full failsave )
Stefan Roese8aa34492013-04-25 23:20:23 +0000204 * failsave 1 0x1005C065 00010000000001011100000001100101 ( digib.-ver ok )
205 * failsave 2 0x1005C065 00010000000001011100000001100101 ( all ok )
Stefan Roese13b4f632012-08-14 15:04:19 +0200206 * || ||| || | ||| | | | |
207 * || ||| || | ||| | | | | bit rev name
208 * ++-+++-++--+---+++-+---+---+---+- 0 31 CS1
209 * +-+++-++--+---+++-+---+---+---+- 1 30 LPTZ
210 * ||| || | ||| | | | | 2 29 ALTs
211 * +++-++--+---+++-+---+---+---+- 3 28 ALTs
212 * ++-++--+---+++-+---+---+---+- 4 27 CS7
213 * +-++--+---+++-+---+---+---+- 5 26 CS6
214 * || | ||| | | | | 6 25 ATA
215 * ++--+---+++-+---+---+---+- 7 24 ATA
216 * +--+---+++-+---+---+---+- 8 23 IR_USB_CLK
217 * | ||| | | | | 9 22 IRDA
218 * | ||| | | | | 10 21 IRDA
219 * +---+++-+---+---+---+- 11 20 IRDA
220 * ||| | | | | 12 19 Ether
221 * ||| | | | | 13 18 Ether
222 * ||| | | | | 14 17 Ether
223 * +++-+---+---+---+- 15 16 Ether
224 * ++-+---+---+---+- 16 15 PCI_DIS
225 * +-+---+---+---+- 17 14 USB_SE
226 * | | | | 18 13 USB
227 * +---+---+---+- 19 12 USB
228 * | | | 20 11 PSC3
229 * | | | 21 10 PSC3
230 * | | | 22 9 PSC3
231 * +---+---+- 23 8 PSC3
232 * | | 24 7 -
233 * | | 25 6 PSC2
234 * | | 26 5 PSC2
235 * +---+- 27 4 PSC2
236 * | 28 3 -
237 * | 29 2 PSC1
238 * | 30 1 PSC1
239 * +- 31 0 PSC1
240 */
241
242
243/*
244 * Miscellaneous configurable options
245 */
246#define CONFIG_SYS_LONGHELP
Stefan Roese13b4f632012-08-14 15:04:19 +0200247
248#define CONFIG_CMDLINE_EDITING
249#define CONFIG_SYS_HUSH_PARSER
250#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
251
252#if defined(CONFIG_CMD_KGDB)
253#define CONFIG_SYS_CBSIZE 1024
254#else
255#define CONFIG_SYS_CBSIZE 256
256#endif
257#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
258#define CONFIG_SYS_MAXARGS 16
259#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
260
261#define CONFIG_SYS_MEMTEST_START 0x00100000
262#define CONFIG_SYS_MEMTEST_END 0x00f00000
263
264#define CONFIG_SYS_LOAD_ADDR 0x00100000
265
Stefan Roese13b4f632012-08-14 15:04:19 +0200266#define CONFIG_LOOPW
267#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
268
269/*
270 * Various low-level settings
271 */
272#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI)
273#define CONFIG_SYS_HID0_FINAL HID0_ICE
274
275#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
276#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
277#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
278#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
Stefan Roesed4451d32013-02-07 02:10:11 +0000279
280#ifdef CONFIG_A4M2K
281/* external MRAM */
282#define CONFIG_SYS_CS1_START 0xf1000000
283#define CONFIG_SYS_CS1_SIZE (512 << 10) /* 512KiB MRAM */
284#endif
285
Stefan Roese13b4f632012-08-14 15:04:19 +0200286#define CONFIG_SYS_CS2_START 0xe0000000
287#define CONFIG_SYS_CS2_SIZE 0x00100000
288
Stefan Roesed4451d32013-02-07 02:10:11 +0000289/* FPGA slave io (512kiB / 1MiB) - see ticket #66 */
Stefan Roese13b4f632012-08-14 15:04:19 +0200290#define CONFIG_SYS_CS3_START 0xE9000000
Stefan Roesed4451d32013-02-07 02:10:11 +0000291#ifdef CONFIG_A4M2K
292#define CONFIG_SYS_CS3_SIZE 0x00100000
293#else
Stefan Roese13b4f632012-08-14 15:04:19 +0200294#define CONFIG_SYS_CS3_SIZE 0x00080000
Stefan Roesed4451d32013-02-07 02:10:11 +0000295#endif
Stefan Roese13b4f632012-08-14 15:04:19 +0200296/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
297#define CONFIG_SYS_CS3_CFG 0x0032B900
298
Stefan Roesed4451d32013-02-07 02:10:11 +0000299#ifndef CONFIG_A4M2K
Stefan Roese13b4f632012-08-14 15:04:19 +0200300/* Diagnosis Interface - see ticket #63 */
301#define CONFIG_SYS_CS4_START 0xEA000000
302#define CONFIG_SYS_CS4_SIZE 0x00000001
303/* 00000000 00000010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0002B900 */
304#define CONFIG_SYS_CS4_CFG 0x0002B900
Stefan Roesed4451d32013-02-07 02:10:11 +0000305#endif
Stefan Roese13b4f632012-08-14 15:04:19 +0200306
Stefan Roesed4451d32013-02-07 02:10:11 +0000307/* FPGA master io (64kiB / 1MiB) - see ticket #66 */
Stefan Roese13b4f632012-08-14 15:04:19 +0200308#define CONFIG_SYS_CS5_START 0xE8000000
Stefan Roesed4451d32013-02-07 02:10:11 +0000309#ifdef CONFIG_A4M2K
310#define CONFIG_SYS_CS5_SIZE 0x00100000
311#else
Stefan Roese13b4f632012-08-14 15:04:19 +0200312#define CONFIG_SYS_CS5_SIZE 0x00010000
Stefan Roesed4451d32013-02-07 02:10:11 +0000313#endif
Stefan Roese13b4f632012-08-14 15:04:19 +0200314/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
315#define CONFIG_SYS_CS5_CFG 0x0032B900
316
317#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for pci_clk = 66 MHz */
318#define CONFIG_SYS_BOOTCS_CFG 0x0006F900
Stefan Roesed4451d32013-02-07 02:10:11 +0000319#define CONFIG_SYS_CS1_CFG 0x0008FD00
Stefan Roese13b4f632012-08-14 15:04:19 +0200320#define CONFIG_SYS_CS2_CFG 0x0006F90C
321#else /* for pci_clk = 33 MHz */
322#define CONFIG_SYS_BOOTCS_CFG 0x0002F900
323#define CONFIG_SYS_CS1_CFG 0x0001FB00
324#define CONFIG_SYS_CS2_CFG 0x0002F90C
325#endif
326
327#define CONFIG_SYS_CS_BURST 0x00000000
328/* set DC for FPGA CS5 and CS3 to 0 - see ticket #66 */
329/* R 7 R 6 R 5 R 4 R 3 R 2 R 1 R 0 */
330/* 00 11 00 11 00 00 00 11 00 00 00 00 00 00 00 00 */
331#define CONFIG_SYS_CS_DEADCYCLE 0x33030000
332
333#define CONFIG_SYS_RESET_ADDRESS 0xff000000
334
335/*
336 * Environment Configuration
337 */
338
Stefan Roese8aa34492013-04-25 23:20:23 +0000339#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
Stefan Roese13b4f632012-08-14 15:04:19 +0200340#undef CONFIG_BOOTARGS
341#define CONFIG_ZERO_BOOTDELAY_CHECK
342
Stefan Roese8aa34492013-04-25 23:20:23 +0000343#define CONFIG_SYS_AUTOLOAD "n"
344
Stefan Roese13b4f632012-08-14 15:04:19 +0200345#define CONFIG_PREBOOT "echo;" \
346 "echo Type \"run flash_mtd\" to boot from flash with mtd filesystem;" \
347 "echo Type \"run net_nfs\" to boot from tftp with nfs filesystem;" \
348 "echo"
349
350#undef CONFIG_BOOTARGS
351
Stefan Roese8aa34492013-04-25 23:20:23 +0000352#define CONFIG_SYS_OS_BASE 0xfc200000
353#define CONFIG_SYS_FDT_BASE 0xfc1e0000
Stefan Roese13b4f632012-08-14 15:04:19 +0200354
Stefan Roese13b4f632012-08-14 15:04:19 +0200355#define CONFIG_EXTRA_ENV_SETTINGS \
356 "netdev=eth0\0" \
357 "verify=no\0" \
Stefan Roesed4451d32013-02-07 02:10:11 +0000358 "loadaddr=200000\0" \
359 "kernel_addr=" __stringify(CONFIG_SYS_OS_BASE) "\0" \
360 "kernel_addr_r=1000000\0" \
361 "fdt_addr=" __stringify(CONFIG_SYS_FDT_BASE) "\0" \
362 "fdt_addr_r=1800000\0" \
363 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
364 "fdtfile=" __stringify(CONFIG_HOSTNAME) "/" \
365 __stringify(CONFIG_HOSTNAME) ".dtb\0" \
366 "rootpath=/opt/eldk-5.2.1/powerpc/" \
367 "core-image-minimal-mtdutils-dropbear-generic\0" \
Stefan Roese13b4f632012-08-14 15:04:19 +0200368 "consoledev=ttyPSC0\0" \
369 "nfsargs=setenv bootargs root=/dev/nfs rw " \
370 "nfsroot=${serverip}:${rootpath}\0" \
371 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Stefan Roesed62a89b2013-06-22 16:16:25 +0200372 "mtdargs=setenv bootargs root=/dev/mtdblock8 " \
Stefan Roese8aa34492013-04-25 23:20:23 +0000373 "rootfstype=squashfs,jffs2\0" \
374 "addhost=setenv bootargs ${bootargs} " \
375 "hostname=${hostname}\0" \
Stefan Roese13b4f632012-08-14 15:04:19 +0200376 "addip=setenv bootargs ${bootargs} " \
377 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
378 ":${hostname}:${netdev}:off panic=1\0" \
379 "addtty=setenv bootargs ${bootargs} " \
380 "console=${consoledev},${baudrate}\0" \
Stefan Roesed62a89b2013-06-22 16:16:25 +0200381 "flash_nfs=run nfsargs addip addtty addmtd addhost;" \
Stefan Roese8aa34492013-04-25 23:20:23 +0000382 "bootm ${kernel_addr} - ${fdt_addr}\0" \
Stefan Roesed62a89b2013-06-22 16:16:25 +0200383 "flash_mtd=run mtdargs addip addtty addmtd addhost;" \
Stefan Roese8aa34492013-04-25 23:20:23 +0000384 "bootm ${kernel_addr} - ${fdt_addr}\0" \
Stefan Roesed62a89b2013-06-22 16:16:25 +0200385 "flash_self=run ramargs addip addtty addmtd addhost;" \
Stefan Roesed4451d32013-02-07 02:10:11 +0000386 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
387 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
388 "tftp ${fdt_addr_r} ${fdtfile};" \
Stefan Roesed62a89b2013-06-22 16:16:25 +0200389 "run nfsargs addip addtty addmtd addhost;" \
Stefan Roesed4451d32013-02-07 02:10:11 +0000390 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
391 "load=tftp ${loadaddr} " __stringify(CONFIG_HOSTNAME) \
392 "/u-boot-img.bin\0" \
Stefan Roesed62a89b2013-06-22 16:16:25 +0200393 "update=protect off fc000000 fc07ffff;" \
Stefan Roese8aa34492013-04-25 23:20:23 +0000394 "era fc000000 fc07ffff;" \
395 "cp.b ${loadaddr} fc000000 ${filesize}\0" \
Stefan Roese13b4f632012-08-14 15:04:19 +0200396 "upd=run load;run update\0" \
Stefan Roesed62a89b2013-06-22 16:16:25 +0200397 "upd_fdt=tftp 1800000 a3m071/a3m071.dtb;" \
398 "run mtdargs addip addtty addmtd addhost;" \
399 "fdt addr 1800000;fdt boardsetup;fdt chosen;" \
400 "erase fc1e0000 fc1fffff;cp.b 1800000 fc1e0000 20000" \
401 "upd_kernel=tftp 1000000 a3m071/uImage-uncompressed;" \
402 "erase fc200000 fc6fffff;" \
403 "cp.b 1000000 fc200000 ${filesize}" \
404 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
405 "mtdids=" MTDIDS_DEFAULT "\0" \
406 "mtdparts=" MTDPARTS_DEFAULT "\0" \
Stefan Roese13b4f632012-08-14 15:04:19 +0200407 ""
408
409#define CONFIG_BOOTCOMMAND "run flash_mtd"
410
411/*
412 * SPL related defines
413 */
Stefan Roese13b4f632012-08-14 15:04:19 +0200414#define CONFIG_SPL_FRAMEWORK
Stefan Roesed4451d32013-02-07 02:10:11 +0000415#define CONFIG_SPL_BOARD_INIT
Stefan Roese13b4f632012-08-14 15:04:19 +0200416#define CONFIG_SPL_NOR_SUPPORT
417#define CONFIG_SPL_TEXT_BASE 0xfc000000
Stefan Roese13b4f632012-08-14 15:04:19 +0200418#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
419#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
420#define CONFIG_SPL_SERIAL_SUPPORT
421
422/* Place BSS for SPL near end of SDRAM */
423#define CONFIG_SPL_BSS_START_ADDR ((128 - 1) << 20)
424#define CONFIG_SPL_BSS_MAX_SIZE (64 << 10)
425
426#define CONFIG_SPL_OS_BOOT
Ying Zhangba1bee42013-05-20 14:07:25 +0800427#define CONFIG_SPL_ENV_SUPPORT
Stefan Roese13b4f632012-08-14 15:04:19 +0200428/* Place patched DT blob (fdt) at this address */
429#define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000
430
431/* Settings for real U-Boot to be loaded from NOR flash */
432#ifndef __ASSEMBLY__
433extern char __spl_flash_end[];
434#endif
435#define CONFIG_SYS_UBOOT_BASE __spl_flash_end
436#define CONFIG_SYS_SPL_MAX_LEN (32 << 10)
437#define CONFIG_SYS_UBOOT_START 0x1000100
438
439#endif /* __CONFIG_H */