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Dirk Eibachb9944a72013-06-26 15:55:17 +02001/*
2 * (C) Copyright 2013
3 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
4 *
5 * based on P1022DS.h
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29#ifdef CONFIG_36BIT
30#define CONFIG_PHYS_64BIT
31#endif
32
33#ifdef CONFIG_SDCARD
34#define CONFIG_RAMBOOT_SDCARD
35#endif
36
37#ifdef CONFIG_SPIFLASH
38#define CONFIG_RAMBOOT_SPIFLASH
39#endif
40
41/* High Level Configuration Options */
42#define CONFIG_BOOKE /* BOOKE */
43#define CONFIG_E500 /* BOOKE e500 family */
Dirk Eibachb9944a72013-06-26 15:55:17 +020044#define CONFIG_P1022
45#define CONFIG_CONTROLCENTERD
46#define CONFIG_MP /* support multiple processors */
47
Dirk Eibachd9f923f2014-07-25 10:10:24 +020048#define CONFIG_SYS_GENERIC_BOARD
49
Dirk Eibachb9944a72013-06-26 15:55:17 +020050#define CONFIG_SYS_NO_FLASH
51#define CONFIG_ENABLE_36BIT_PHYS
52#define CONFIG_FSL_LAW /* Use common FSL init code */
53
54#ifdef CONFIG_TRAILBLAZER
55#define CONFIG_IDENT_STRING " controlcenterd trailblazer 0.01"
56#else
57#define CONFIG_IDENT_STRING " controlcenterd 0.01"
58#endif
59
60#ifdef CONFIG_PHYS_64BIT
61#define CONFIG_ADDR_MAP
62#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
63#endif
64
65#define CONFIG_L2_CACHE
66#define CONFIG_BTB
67
68#define CONFIG_SYS_CLK_FREQ 66666600
69#define CONFIG_DDR_CLK_FREQ 66666600
70
71#define CONFIG_SYS_RAMBOOT
72
73#ifdef CONFIG_TRAILBLAZER
74
75#define CONFIG_SYS_TEXT_BASE 0xf8fc0000
76#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
77#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
78
79/*
80 * Config the L2 Cache
81 */
82#define CONFIG_SYS_INIT_L2_ADDR 0xf8fc0000
83#ifdef CONFIG_PHYS_64BIT
84#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8fc0000ull
85#else
86#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
87#endif
88#define CONFIG_SYS_L2_SIZE (256 << 10)
89#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
90
91#else /* CONFIG_TRAILBLAZER */
92
93#define CONFIG_SYS_TEXT_BASE 0x11000000
94#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
95#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
96
97#endif /* CONFIG_TRAILBLAZER */
98
99#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
100#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
101
102
103/*
104 * Memory map
105 *
106 * 0x0000_0000 0x3fff_ffff DDR 1G Cacheable
107 * 0xc000_0000 0xdfff_ffff PCI Express Mem 512M non-cacheable
108 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
109 *
110 * Localbus non-cacheable
111 * 0xe000_0000 0xe00f_ffff eLBC 1M non-cacheable
112 * 0xf8fc0000 0xf8ff_ffff L2 SRAM 256k Cacheable
113 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
114 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
115 */
116
117#define CONFIG_SYS_INIT_RAM_LOCK
118#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
119#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* used area in RAM */
120#define CONFIG_SYS_GBL_DATA_OFFSET \
121 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
122#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
123
124#ifdef CONFIG_TRAILBLAZER
125/* leave CCSRBAR at default, because u-boot expects it to be exactly there */
126#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
127#else
128#define CONFIG_SYS_CCSRBAR 0xffe00000
129#endif
130#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
131#define CONFIG_SYS_MPC85xx_GPIO3_ADDR (CONFIG_SYS_CCSRBAR+0xf200)
132
133/*
134 * DDR Setup
135 */
136
137#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
138#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
139#define CONFIG_SYS_SDRAM_SIZE 1024
140#define CONFIG_VERY_BIG_RAM
141
York Sun5614e712013-09-30 09:22:09 -0700142#define CONFIG_SYS_FSL_DDR3
Dirk Eibachb9944a72013-06-26 15:55:17 +0200143#define CONFIG_NUM_DDR_CONTROLLERS 1
144#define CONFIG_DIMM_SLOTS_PER_CTLR 1
145#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
146
147#define CONFIG_SYS_MEMTEST_START 0x00000000
148#define CONFIG_SYS_MEMTEST_END 0x3fffffff
149
150#ifdef CONFIG_TRAILBLAZER
151#define CONFIG_SPD_EEPROM
152#define SPD_EEPROM_ADDRESS 0x52
153/*#define CONFIG_FSL_DDR_INTERACTIVE*/
154#endif
155
156/*
157 * Local Bus Definitions
158 */
159#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
160
161#define CONFIG_SYS_ELBC_BASE 0xe0000000
162#ifdef CONFIG_PHYS_64BIT
163#define CONFIG_SYS_ELBC_BASE_PHYS 0xfe0000000ull
164#else
165#define CONFIG_SYS_ELBC_BASE_PHYS CONFIG_SYS_ELBC_BASE
166#endif
167
168#define CONFIG_UART_BR_PRELIM \
169 (BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V)
170#define CONFIG_UART_OR_PRELIM (OR_AM_32KB | 0xff7)
171
172#define CONFIG_SYS_BR0_PRELIM 0 /* CS0 was originally intended for FPGA */
173#define CONFIG_SYS_OR0_PRELIM 0 /* debugging, was never used */
174
175#define CONFIG_SYS_BR1_PRELIM CONFIG_UART_BR_PRELIM
176#define CONFIG_SYS_OR1_PRELIM CONFIG_UART_OR_PRELIM
177
178/*
179 * Serial Port
180 */
181#define CONFIG_CONS_INDEX 2
182#define CONFIG_SYS_NS16550
183#define CONFIG_SYS_NS16550_SERIAL
184#define CONFIG_SYS_NS16550_REG_SIZE 1
185#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
186
187#define CONFIG_SYS_BAUDRATE_TABLE \
188 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
189
190#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
191#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
192
193/*
194 * I2C
195 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200196#define CONFIG_SYS_I2C
197#define CONFIG_SYS_I2C_FSL
198#define CONFIG_SYS_FSL_I2C_SPEED 400000
199#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
200#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
201#define CONFIG_SYS_FSL_I2C2_SPEED 400000
202#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
203#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Dirk Eibach5568fb42014-07-03 09:28:21 +0200204
205#ifndef CONFIG_TRAILBLAZER
206#define CONFIG_CMD_I2C
207#endif
Dirk Eibachb9944a72013-06-26 15:55:17 +0200208
209#define CONFIG_PCA9698 /* NXP PCA9698 */
210
211#define CONFIG_CMD_EEPROM
212#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
213#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
214
215#ifndef CONFIG_TRAILBLAZER
216/*
217 * eSPI - Enhanced SPI
218 */
219#define CONFIG_HARD_SPI
220#define CONFIG_FSL_ESPI
221
Dirk Eibachb9944a72013-06-26 15:55:17 +0200222#define CONFIG_SPI_FLASH_STMICRO
223
224#define CONFIG_CMD_SF
225#define CONFIG_SF_DEFAULT_SPEED 10000000
226#define CONFIG_SF_DEFAULT_MODE 0
227#endif
228
229/*
230 * TPM
231 */
232#define CONFIG_TPM_ATMEL_TWI
233#define CONFIG_TPM
234#define CONFIG_TPM_AUTH_SESSIONS
235#define CONFIG_SHA1
236#define CONFIG_CMD_TPM
237
238/*
239 * MMC
240 */
241#define CONFIG_MMC
242#define CONFIG_GENERIC_MMC
243#define CONFIG_CMD_MMC
244
245#define CONFIG_FSL_ESDHC
246#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
247
248
249#ifndef CONFIG_TRAILBLAZER
250
251/*
252 * Video
253 */
254#define CONFIG_FSL_DIU_FB
255#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
256#define CONFIG_VIDEO
257#define CONFIG_CFB_CONSOLE
258#define CONFIG_VGA_AS_SINGLE_DEVICE
259#define CONFIG_CMD_BMP
260
261/*
262 * General PCI
263 * Memory space is mapped 1-1, but I/O space must start from 0.
264 */
265#define CONFIG_PCI /* Enable PCI/PCIE */
266#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
267#define CONFIG_PCI_INDIRECT_BRIDGE
268#define CONFIG_PCI_PNP /* do pci plug-and-play */
269#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
270#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
271#define CONFIG_CMD_PCI
272
273#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
274#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
275
276#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
277#ifdef CONFIG_PHYS_64BIT
278#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
279#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
280#else
281#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
282#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
283#endif
284#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
285#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
286#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
287#ifdef CONFIG_PHYS_64BIT
288#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
289#else
290#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
291#endif
292#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
293
294/*
295 * SATA
296 */
297#define CONFIG_LIBATA
298#define CONFIG_LBA48
299#define CONFIG_CMD_SATA
300
301#define CONFIG_FSL_SATA
302#define CONFIG_SYS_SATA_MAX_DEVICE 2
303#define CONFIG_SATA1
304#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
305#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
306#define CONFIG_SATA2
307#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
308#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
309
310/*
311 * Ethernet
312 */
313#define CONFIG_TSEC_ENET
314
315#define CONFIG_TSECV2
316
317#define CONFIG_MII /* MII PHY management */
318#define CONFIG_TSEC1 1
319#define CONFIG_TSEC1_NAME "eTSEC1"
320#define CONFIG_TSEC2 1
321#define CONFIG_TSEC2_NAME "eTSEC2"
322
323#define TSEC1_PHY_ADDR 0
324#define TSEC2_PHY_ADDR 1
325
326#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
327#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
328
329#define TSEC1_PHYIDX 0
330#define TSEC2_PHYIDX 0
331
332#define CONFIG_ETHPRIME "eTSEC1"
333
334#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
335
336/*
337 * USB
338 */
339#define CONFIG_USB_EHCI
340#define CONFIG_CMD_USB
341#define CONFIG_USB_STORAGE
342
343#define CONFIG_HAS_FSL_DR_USB
344#define CONFIG_USB_EHCI_FSL
345#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
346
347#endif /* CONFIG_TRAILBLAZER */
348
349/*
350 * Environment
351 */
352#if defined(CONFIG_TRAILBLAZER)
353#define CONFIG_ENV_IS_NOWHERE
354#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
Dirk Eibachb9944a72013-06-26 15:55:17 +0200355#elif defined(CONFIG_RAMBOOT_SPIFLASH)
356#define CONFIG_ENV_IS_IN_SPI_FLASH
357#define CONFIG_ENV_SPI_BUS 0
358#define CONFIG_ENV_SPI_CS 0
359#define CONFIG_ENV_SPI_MAX_HZ 10000000
360#define CONFIG_ENV_SPI_MODE 0
361#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
362#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
363#define CONFIG_ENV_SECT_SIZE 0x10000
364#elif defined(CONFIG_RAMBOOT_SDCARD)
365#define CONFIG_ENV_IS_IN_MMC
366#define CONFIG_FSL_FIXED_MMC_LOCATION
367#define CONFIG_ENV_SIZE 0x2000
368#define CONFIG_SYS_MMC_ENV_DEV 0
369#endif
370
371#define CONFIG_SYS_EXTRA_ENV_RELOC
372
373#define CONFIG_SYS_CONSOLE_IS_IN_ENV
374
375/*
376 * Command line configuration.
377 */
378#ifndef CONFIG_TRAILBLAZER
379#define CONFIG_SYS_HUSH_PARSER
380#define CONFIG_SYS_LONGHELP
381#define CONFIG_CMDLINE_EDITING /* Command-line editing */
382#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
383#endif /* CONFIG_TRAILBLAZER */
384
385#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Dirk Eibachb9944a72013-06-26 15:55:17 +0200386#ifdef CONFIG_CMD_KGDB
387#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
388#else
389#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
390#endif
391/* Print Buffer Size */
392#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
393#define CONFIG_SYS_MAXARGS 16
394#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
395
Dirk Eibachb9944a72013-06-26 15:55:17 +0200396#ifndef CONFIG_TRAILBLAZER
397
398#define CONFIG_CMD_ELF
399#define CONFIG_CMD_ERRATA
400#define CONFIG_CMD_EXT2
401#define CONFIG_CMD_FAT
402#define CONFIG_CMD_IRQ
403#define CONFIG_CMD_MII
Dirk Eibachb9944a72013-06-26 15:55:17 +0200404#define CONFIG_CMD_PING
Dirk Eibachb9944a72013-06-26 15:55:17 +0200405#define CONFIG_CMD_REGINFO
406
407/*
408 * Board initialisation callbacks
409 */
410#define CONFIG_BOARD_EARLY_INIT_F
411#define CONFIG_BOARD_EARLY_INIT_R
412#define CONFIG_MISC_INIT_R
413#define CONFIG_LAST_STAGE_INIT
414
415/*
416 * Pass open firmware flat tree
417 */
418#define CONFIG_OF_LIBFDT
419#define CONFIG_OF_BOARD_SETUP
420#define CONFIG_OF_STDOUT_VIA_ALIAS
421
422/* new uImage format support */
423#define CONFIG_FIT
424#define CONFIG_FIT_VERBOSE
425
426#else /* CONFIG_TRAILBLAZER */
427
428#define CONFIG_BOARD_EARLY_INIT_F
429#define CONFIG_BOARD_EARLY_INIT_R
430#define CONFIG_LAST_STAGE_INIT
Dirk Eibachb9944a72013-06-26 15:55:17 +0200431
432#endif /* CONFIG_TRAILBLAZER */
433
434/*
435 * Miscellaneous configurable options
436 */
Dirk Eibachb9944a72013-06-26 15:55:17 +0200437#define CONFIG_HW_WATCHDOG
438#define CONFIG_LOADS_ECHO
439#define CONFIG_SYS_LOADS_BAUD_CHANGE
440#define CONFIG_DOS_PARTITION
441
442/*
443 * For booting Linux, the board info and command line data
444 * have to be in the first 64 MB of memory, since this is
445 * the maximum mapped by the Linux kernel during initialization.
446 */
447#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Linux Memory map */
448#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
449
450/*
451 * Environment Configuration
452 */
453
454#ifdef CONFIG_TRAILBLAZER
455
456#define CONFIG_BOOTDELAY 0 /* -1 disables auto-boot */
457#define CONFIG_BAUDRATE 115200
458
459#define CONFIG_EXTRA_ENV_SETTINGS \
460 "mp_holdoff=1\0"
461
462#else
463
464#define CONFIG_HOSTNAME controlcenterd
465#define CONFIG_ROOTPATH "/opt/nfsroot"
466#define CONFIG_BOOTFILE "uImage"
467#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP */
468
469#define CONFIG_LOADADDR 1000000
470
471#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
472
473#define CONFIG_BAUDRATE 115200
474
475#define CONFIG_EXTRA_ENV_SETTINGS \
476 "netdev=eth0\0" \
477 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
478 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
479 "tftpflash=tftpboot $loadaddr $uboot && " \
480 "protect off $ubootaddr +$filesize && " \
481 "erase $ubootaddr +$filesize && " \
482 "cp.b $loadaddr $ubootaddr $filesize && " \
483 "protect on $ubootaddr +$filesize && " \
484 "cmp.b $loadaddr $ubootaddr $filesize\0" \
485 "consoledev=ttyS1\0" \
486 "ramdiskaddr=2000000\0" \
487 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
488 "fdtaddr=c00000\0" \
489 "fdtfile=controlcenterd.dtb\0" \
490 "bdev=sda3\0"
491
492/* these are used and NUL-terminated in env_default.h */
493#define CONFIG_NFSBOOTCOMMAND \
494 "setenv bootargs root=/dev/nfs rw " \
495 "nfsroot=$serverip:$rootpath " \
496 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
497 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
498 "tftp $loadaddr $bootfile;" \
499 "tftp $fdtaddr $fdtfile;" \
500 "bootm $loadaddr - $fdtaddr"
501
502#define CONFIG_RAMBOOTCOMMAND \
503 "setenv bootargs root=/dev/ram rw " \
504 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
505 "tftp $ramdiskaddr $ramdiskfile;" \
506 "tftp $loadaddr $bootfile;" \
507 "tftp $fdtaddr $fdtfile;" \
508 "bootm $loadaddr $ramdiskaddr $fdtaddr"
509
510#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
511
512#endif /* CONFIG_TRAILBLAZER */
513
514#endif